KR100501184B1 - Dielectric Ceramic Composition Having High Breakdown Voltage Properties and Multilayer Ceramic Chip Capacitor Using The Same - Google Patents
Dielectric Ceramic Composition Having High Breakdown Voltage Properties and Multilayer Ceramic Chip Capacitor Using The Same Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
- H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
- H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
- H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
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- C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
- C04B35/01—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics
- C04B35/46—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates
- C04B35/462—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates based on titanates
- C04B35/465—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates based on titanates based on alkaline earth metal titanates
- C04B35/468—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates based on titanates based on alkaline earth metal titanates based on barium titanates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
Abstract
본 발명은 유전체 자기 조성물과 그것을 사용한 적층 세라믹 커패시터에 관한 것으로, 그 목적은 X7R특성을 지니고, 파괴전압과 절연저항이 높은 유전체 자기조성물과 이 유전체 자기조성물을 이용한 적층세라믹 커패시터를 제공하는 것이다. The present invention relates to a dielectric ceramic composition and a multilayer ceramic capacitor using the same, and an object thereof is to provide a dielectric ceramic composition having X7R characteristics, high breakdown voltage and high insulation resistance, and a multilayer ceramic capacitor using the dielectric ceramic composition.
상기 목적을 달성하기 위한 본 발명은, aBaTiO3 + bMnO2 + cMgCO3 + dR 2O3(R; Y, 또는 란탄계열원소에서 선택된 적어도 1종) + eBaxCa(1-x)SiO3 또는 여기에 fSrZrO3가 추가로 포함되어 조성되고, 여기서 a=100일 때 0<b≤0.5, 0.02≤c≤3, 0.05≤d≤5 , 0.02≤e≤1.5, 0.5≤f≤3을 만족하는 내전압 특성이 우수한 유전체 자기조성물과, 상기 유전체 자기조성물로 이루어진 2이상의 유전체층과 이 유전체층을 사이에 두도록 형성된 1개 이상의 내부전극을 포함하여 이루어지는 적층세라믹 커패시터에 관한 것을 그 기술요지로 한다.The present invention for achieving the above object, aBaTiO 3 + bMnO 2 + cMgCO 3 + dR 2 O 3 (R; at least one selected from Y, or lanthanum-based element) + eBa x Ca (1-x) SiO 3 or FSrZrO 3 is further included in the composition, and when a = 100, 0 <b≤0.5, 0.02≤c≤3, 0.05≤d≤5, 0.02≤e≤1.5, and 0.5≤f≤3 The present invention relates to a dielectric ceramic composition having excellent withstand voltage characteristics, a multilayer ceramic capacitor comprising at least two dielectric layers made of the dielectric magnetic composition and at least one internal electrode formed to sandwich the dielectric layer.
Description
발명은 유전체 자기 조성물과 그것을 사용한 적층 세라믹 커패시터에 관한 것이다. The present invention relates to a dielectric ceramic composition and a multilayer ceramic capacitor using the same.
종래부터 세라믹 커패시터에 사용되는 유전체 자기 조성물로서, 티탄산바륨(BaTiO3)을 주제로 하는 것이 많이 알려져 있다. BaTiO3을 주제로 한 유전체는 내부전극과 번갈아 적층하는 적층세라믹 커패시터(이하, MLCC라 함)로 많이 사용되고 있다.Background Art Conventionally, barium titanate (BaTiO 3 ) is known as a dielectric ceramic composition used in ceramic capacitors. Dielectrics based on BaTiO 3 are commonly used as multilayer ceramic capacitors (hereinafter referred to as MLCCs) alternately stacked with internal electrodes.
최근 MLCC의 소형화 경향이 일면서 유전체층의 두께를 얇게 하고 적층수를 많게 하는 방법이 알려지고 있다. 그러나, 유전체층의 두께를 지나치게 얇게 하면 비교적 낮은 전압에서 파괴되어 고압에 적용하기 어렵다. 특히, 파괴전압(breakdown voltage)에 대한 신뢰성이 중요하게 여겨지는 X7R 특성을 가지는 적층세라믹 커패시터의 경우에는 중요한 문제이다. Recently, there is a trend toward miniaturization of MLCCs, and a method of reducing the thickness of the dielectric layer and increasing the number of stacked layers is known. However, if the thickness of the dielectric layer is made too thin, it is broken at a relatively low voltage and is difficult to apply to high pressure. In particular, it is an important problem in the case of a multilayer ceramic capacitor having X7R characteristics in which reliability of breakdown voltage is considered important.
X7R특성을 요구하는 적층세라믹 커패시터에는 BaTiO3에 Cr2O3와 V2 O5 등의 부성분을 첨가한 저전압 유전체 조성물이 알려져 있다. 따라서, 이 유전체를 고전압에 적용하는 경우에는 유전체의 두께를 크게 하여 두께당 적용되는 전압을 작게함으로써 높은 전압에 견디도록 설계하고 있다. 또한, 내부전극의 인쇄패턴을 도 1에서 내부전극간의 겹칩부분을 작게 (low screen)하여 내부 세라믹에 적용되는 전압을 작게 하고 있다. 즉, 상하 내부전극의 겹칩길이(a)가 a=0.3L~0.4L의 조건을 만족하도록 설계하고 있다. 이러한 방법은 제품의 두께를 두껍게 유지하여야 하므로 높은 용량의 칩제조를 어렵게 할 뿐 아니라, 전자회로의 고밀도화에 역행하는 결과를 낳고 있다.BACKGROUND ART As a multilayer ceramic capacitor requiring X7R characteristics, a low voltage dielectric composition in which subsidiary components such as Cr 2 O 3 and V 2 O 5 are added to BaTiO 3 is known. Therefore, when this dielectric is applied to a high voltage, it is designed to withstand high voltage by increasing the thickness of the dielectric and decreasing the voltage applied per thickness. In addition, as shown in FIG. 1, the printed chip of the internal electrode is made small by overlapping the overlapping chip portions between the internal electrodes, thereby reducing the voltage applied to the internal ceramic. That is, the stacking chip length a of the upper and lower internal electrodes is designed to satisfy the condition of a = 0.3L to 0.4L. This method has to keep the thickness of the product thick, making it difficult to manufacture a high-capacity chip, and also results in a high density of electronic circuits.
본 발명은 X7R특성을 지니고, 파괴전압과 절연저항이 높은 유전체 자기조성물을 제공하는데 그 목적이 있다. 나아가, 본 발명에서는 이 유전체 자기조성물을 이용한 적층세라믹 커패시터를 제공하는데도 그 목적이 있다. An object of the present invention is to provide a dielectric magnetic composition having X7R characteristics and high breakdown voltage and high insulation resistance. Furthermore, the present invention also provides a multilayer ceramic capacitor using the dielectric magnetic composition.
상기 목적을 달성하기 위한 본 발명의 유전체 자기조성물은, aBaTiO3 + bMnO2 + cMgCO3 + dR2O3(R: Y 또는 란탄계열원소에서 선택된 적어도 1종) + eBa xCa(1-x)SiO3 으로 조성되고, 여기서 a=100일 때 0<b≤0.5, 0.02≤c≤3, 0.05≤d≤5, 0.5≤e ≤3을 만족하는 것이다.Dielectric self-composition of the present invention for achieving the above object, aBaTiO 3 + bMnO 2 + cMgCO 3 + dR 2 O 3 (R: at least one selected from Y or lanthanum-based element) + eBa x Ca (1-x) It is composed of SiO 3 , where 0 <b ≦ 0.5, 0.02 ≦ c ≦ 3, 0.05 ≦ d ≦ 5, and 0.5 ≦ e ≦ 3 when a = 100.
또한, 본 발명의 유전체 자기조성물은, aBaTiO3 + bMnO2 + cMgCO3 + dR 2O3(R: Y 또는 란탄계열원소에서 선택된 적어도 1종) + eBaxCa(1-x)SiO3 + fSrZrO 3으로 조성되고, 여기서 a=100일 때 0<b≤0.5, 0.02≤c≤3, 0.05≤d≤5, 0.5≤e≤3, 0.02≤f≤1.5,을 만족하는 것이다.In addition, the dielectric magnetic composition of the present invention is aBaTiO 3 + bMnO 2 + cMgCO 3 + dR 2 O 3 (at least one selected from R: Y or lanthanum-based element) + eBa x Ca (1-x) SiO 3 + fSrZrO 3 , where a = 100, 0 <b ≦ 0.5, 0.02 ≦ c ≦ 3, 0.05 ≦ d ≦ 5, 0.5 ≦ e ≦ 3, and 0.02 ≦ f ≦ 1.5, are satisfied.
또한, 본 발명의 자기커패시터는, aBaTiO3 + bMnO2 + cMgCO3 + dR2 O3(R: Y 또는 란탄계열원소에서 선택된 적어도 1종) + eBaxCa(1-x)SiO3 으로 조성되고, 여기서 a=100일 때 0<b≤0.5, 0.02≤c≤3, 0.05≤d≤5, 0.5≤e ≤3을 만족하는 2이상의 유전체층과 이 유전체층을 사이에 두도록 형성된 1개 이상의 내부전극을 포함하여 구성된다.In addition, the magnetic capacitor of the present invention is composed of aBaTiO 3 + bMnO 2 + cMgCO 3 + dR 2 O 3 (at least one selected from R: Y or lanthanide) + eBa x Ca (1-x) SiO 3 Where at least one dielectric layer satisfying 0 <b≤0.5, 0.02≤c≤3, 0.05≤d≤5, and 0.5≤e≤3, and at least one internal electrode formed to sandwich the dielectric layer It is configured to include.
또한, 본 발명의 자기커패시터는, aBaTiO3 + bMnO2 + cMgCO3 + dR2 O3(R: Y 또는 란탄계열원소에서 선택된 적어도 1종) + eBaxCa(1-x)SiO3 + fSrZrO3으로 조성되고 여기서 a=100일 때 0<b≤0.5, 0.02≤c≤3, 0.05≤d≤5, 0.5≤e≤3, 0.02≤f≤1.5,을 만족하는 2이상의 유전체층과 이 유전체층을 사이에 두도록 형성된 1개 이상의 내부전극을 포함하여 구성된다.In addition, the magnetic capacitor of the present invention, aBaTiO 3 + bMnO 2 + cMgCO 3 + dR 2 O 3 (R: Y or at least one selected from lanthanum-based element) + eBa x Ca (1-x) SiO 3 + fSrZrO 3 Wherein when a = 100, between 0 and 2 dielectric layers satisfying 0 <b≤0.5, 0.02≤c≤3, 0.05≤d≤5, 0.5≤e≤3, 0.02≤f≤1.5, It comprises one or more internal electrodes formed to be placed in.
이하, 본 발명을 상세히 설명한다. Hereinafter, the present invention will be described in detail.
본 발명은 aBaTiO3 + bMnO2 + cMgCO3 + dR2O3(R: Y 또는 란탄계열원소에서 선택된 적어도 1종) + eBaxCa(1-x)SiO3을 포함하여 조성되는 유전체 조성물과, 여기에 추가로 fSrZrO3을 포함하는 유전체 조성물을 특징으로 한다.The present invention provides a dielectric composition comprising aBaTiO 3 + bMnO 2 + cMgCO 3 + dR 2 O 3 (at least one selected from R: Y or lanthanide) + eBa x Ca (1-x) SiO 3 , It is further characterized by a dielectric composition comprising fSrZrO 3 .
본 발명의 유전체 조성물은 BaTiO3계에서 V2O5나 Cr2O3 를 배제한 조건에서 bMnO2 + cMgCO3 + dR2O3을 복합첨가하면 그 상호작용에 의해 절연저항과 파괴전압이 개선된다는 사실에 주목하여 완성된 것이다. 나아가, 이 유전체 조성물에 추가로 SrZrO3를 포함하면, 파괴전압의 분산(편차)를 줄일 수 있다. 이러한 본 발명의 유전체 조성물의 조성범위에 대해 설명한다.In the dielectric composition of the present invention, when bMnO 2 + cMgCO 3 + dR 2 O 3 is added in a condition that excludes V 2 O 5 or Cr 2 O 3 from BaTiO 3 system, the insulation resistance and breakdown voltage are improved by the interaction thereof. It was completed by paying attention to facts. Furthermore, when SrZrO 3 is further included in the dielectric composition, dispersion (deviation) of breakdown voltage can be reduced. The composition range of the dielectric composition of the present invention will be described.
먼저, MnO2: BaTiO3 100몰에 대해 0.5몰이하First, 0.5 mol or less relative to 100 mol of MnO 2 : BaTiO 3
Mn은 BaTiO3의 Ti 사이트(site)에 치환되어 억셉터로서 작용을 하는데, MnO2의 첨가량이 0.5몰 초과의 경우에는 절연저항이 낮아진다.Mn is substituted on the Ti site of BaTiO 3 to act as an acceptor. When the amount of MnO 2 added is more than 0.5 mol, the insulation resistance is lowered.
MgCO3: BaTiO3 100몰에 대해 0.02~3몰MgCO 3 : 0.02 to 3 mol based on 100 mol of BaTiO 3
Mg은 이온 반경이 Ti보다 크고 Ba 보다 작으므로 Ti 사이트에 치환되면서 입성장을 제어한다. Mg이온이 적으면 코어셀(core-shell) 구조를 형성하지 못하고 입자가 커져서 X7R 온도특성(△C=±15%이내, -55~125℃)을 만족하지 못하므로, MgCO3를 BaTiO3 100몰에 대해 0.02몰 이상 첨가한다. 또한, Mg이온의 양이 과다하면 Ti사이트에 치환하지 못하고 석출되는데, 석출, 편석된 상은 커패시터의 절연저항과 BDV에 악영향을 줄 수 있으므로, MgCO3을 BaTiO3 100몰에 대해 3몰이하로 첨가한다.Mg is larger than Ti and smaller than Ba, so Mg is substituted at the Ti site to control grain growth. If Mg ion is small, MgCO 3 is not BaTiO 3 100 because it does not form a core-shell structure and the particles are large and do not satisfy X7R temperature characteristics (△ C = ± 15%, -55 ~ 125 ℃). Add at least 0.02 moles to moles. On the other hand, if the amount of Mg ions over there is precipitated does not substituted at the Ti site, the addition of precipitation,, MgCO 3, because the insulation resistance of the segregation phase is a capacitor and may impair the BDV to less than 3 mol based on BaTiO 3 100 mole do.
R2O3:BaTiO3 100몰에 대해 0.05~5몰R 2 O 3 : 0.05 to 5 moles based on 100 moles of BaTiO 3
희토류(Y 또는 란탄계열원소에서 선택된 적어도 1종)는 Mg와 Mn이 Ti사이트에 치환되면서 발생하는 산소공공(Oxygen vacancy)에 대한 전하 보상을 하는 역할을 한다. 희토류는 Ba 사이트에 치환되어 도너(donor)로 작용하고, 이때 Ba공공이 발생하는데 이는 음이온의 성격을 띄므로 양이온 성격을 갖는 산소공공과 작용하여 전하보상 된다. 산소공공은 고온에서 전도체로 작용하므로 절연저항을 떨어뜨리는데, 희토류치환으로 생성된 Ba공공이 산소공공과 작용하여 전하 보상되므로 절연저항 감소를 막는 역할을 한다. 따라서, 이를 위해 R2O3는 BaTiO3 100몰에 대해 0.05몰 이상 첨가하는 것이 바람직하다. 그러나, Ba공공이 너무 많으면 오히려 상온에서 절연저항을 떨어뜨릴 뿐 아니라, R2O3가 과다하면 BaTiO3에 치환되지 못하고 석출하여 전기적특성(IR, BDV)를 떨어뜨리므로, R2O3는 BaTiO3 100몰에 대해 5몰이하로 첨가하는 것이 바람직하다. 본 발명에서 R은 Y 또는 란탄계열원소에서 선택된 1종이상으로 한다.Rare earth (at least one selected from Y or a lanthanum series element) plays a role of charge compensation for oxygen vacancies generated when Mg and Mn are substituted for Ti sites. Rare earth is replaced by a Ba site acts as a donor, and at this time, Ba pores are generated, which are charged with an oxygen pore having a cationic character because they have an anionic character. Oxygen vacancy acts as a conductor at high temperature, which lowers the insulation resistance. Ba vacancy produced by rare earth substitution acts as oxygen vacancy to compensate for charge, thus preventing the reduction of insulation resistance. Therefore, for this purpose, R 2 O 3 is preferably added at 0.05 moles or more with respect to 100 moles of BaTiO 3 . However, since Ba public the drop too much, but rather dropped, as well as degrade the insulation resistance at room temperature, R 2 O 3 is when electrical characteristics by precipitation does not substituted on BaTiO 3 (IR, BDV) excess, R 2 O 3 is about 100 mol BaTiO 3 is preferable to add no more than 5 mol. In the present invention, R is one or more selected from Y or lanthanide series elements.
BaxCa(1-x)SiO3:BaTiO3 100몰에 대해 0.5~3몰Ba x Ca (1-x) SiO 3 : 0.5 to 3 moles per 100 moles of BaTiO 3
BaxCa(1-x)SiO3는 융점이 1150℃로 낮아 소성온도를 낮추는 소결조제로 역할을 하는데, 이를 위해 BaxCa(1-x)SiO3는 BaTiO3 100몰에 대해 0.5몰 이상 첨가하는 것이 바람직하다. BaxCa(1-x)SiO3의 첨가량이 BaTiO3 100몰에 대해 3몰 초과의 경우에는 석출되어 2상으로 존재하므로 파괴전압을 낮춘다. 본 발명에서는 x는 0~1의 값을 갖는다.Ba x Ca (1-x) SiO 3 has a melting point of 1150 ℃ to serve as a sintering aid to lower the firing temperature. For this purpose, Ba x Ca (1-x) SiO 3 is 0.5 mol or more with respect to 100 mol of BaTiO 3 It is preferable to add. When the added amount of Ba x Ca (1-x) SiO 3 is more than 3 moles with respect to 100 moles of BaTiO 3 , it is precipitated and exists in two phases, thereby lowering the breakdown voltage. In the present invention, x has a value of 0 to 1.
상기와 같이 조성되는 BaTiO3 + MnO2 + MgCO3 + R2O3(R: Y 또는 란탄계열원소에서 선택된 적어도 1종) + BaxCa(1-x)SiO3에 SrZrO3가 추가되는 경우에는 파괴전압 분산(편차)를 줄이는 효과가 있다. 이를 위해 SrZrO3는 BaTiO3 100몰에 대해 0.02~1.5몰 첨가하는 것이 바람직하다. SrZrO3는 파괴전압의 분산(편차)을 줄이는 효과가 있으므로, BaTiO3 100몰에 대해 0.02몰 이상 첨가하는 것이 바람직하다. SrZrO3는 유전율이 BaTiO3에 비해 작으므로 BaTiO3 100몰에 대해 1.5몰 초과의 경우 유전율을 감소시킨다. 또한, SrZrO3가 1.5몰 초과의 경우 Tc를 바꾸어 온도에 따른 용량변화(TCC)를 크게 한다. 본 발명에서 SrZrO3 대신 CaTiO3, CaZrO3, SrTiO3를 사용할 수 있다.When SrZrO 3 is added to BaTiO 3 + MnO 2 + MgCO 3 + R 2 O 3 (R: Y or at least one selected from lanthanide) + Ba x Ca (1-x) SiO 3 This has the effect of reducing breakdown voltage dispersion (deviation). For this purpose, SrZrO 3 is preferably added in an amount of 0.02 to 1.5 moles based on 100 moles of BaTiO 3 . Since SrZrO 3 has the effect of reducing the dispersion (deviation) of the breakdown voltage, it is preferable to add 0.02 mol or more to 100 mol of BaTiO 3 . Since SrZrO 3 has a smaller dielectric constant than BaTiO 3 , the dielectric constant of SrZrO 3 is more than 1.5 mol relative to 100 mol of BaTiO 3 . In addition, when SrZrO 3 is more than 1.5 mol, Tc is changed to increase the capacity change (TCC) with temperature. SrZrO 3 instead of in the present invention may be used CaTiO 3, CaZrO 3, SrTiO 3 .
본 발명에서는 bMnO2 + cMgCO3 + dR2O3을 복합첨가에 의해 절연저항과 파괴전압이 개선되는데, 그 첨가량이 c≥d>b을 만족할 때 절연저항과 파괴전압이 더 높아진다. 상기 bMnO2, cMgCO3, dR2O3의 첨가량은 b:d:c가 0.1:1.0:2.0의 비를 만족할 때 절연저항과 파괴전압이 가장 좋다.In the present invention, by adding bMnO 2 + cMgCO 3 + dR 2 O 3 , the insulation resistance and the breakdown voltage are improved. When the addition amount satisfies c≥d> b, the insulation resistance and the breakdown voltage are higher. The added amount of bMnO 2 , cMgCO 3 , dR 2 O 3 has the best insulation resistance and breakdown voltage when b: d: c satisfies the ratio of 0.1: 1.0: 2.0.
다음으로, 본 발명의 적층세라믹 커패시터에 대해 설명한다. Next, the multilayer ceramic capacitor of the present invention will be described.
본 발명의 적층세라믹 커패시터는 상술한 본 발명의 유전체 자기조성물을 이용하여 2이상의 유전체층과 이 유전체층을 사이에 두도록 형성된 1개 이상의 내부전극을 포함하여 구성된다. 이러한 적층세라믹 커패시터는 유전율 k=2200~2500, 비저항이 1.0E5㏁·m이상인 전기적 특성을 가지며 시트 두께(t), t=125㎛으로 MLCC 제조시 평균 BDV/㎛≒50V 값을 갖는다.The multilayer ceramic capacitor of the present invention comprises two or more dielectric layers and one or more internal electrodes formed to sandwich the dielectric layers by using the above-described dielectric magnetic composition of the present invention. These multilayer ceramic capacitors have electrical characteristics of dielectric constant k = 2200 ~ 2500, resistivity of 1.0E5㏁ · m or more, and have an average BDV / μm ≒ 50V value when manufacturing MLCC with sheet thickness (t) and t = 125㎛.
이와 같이 파괴전압이 높아지므로, 유전체층의 두께를 얇게 할 수 있을 뿐 아니라, 상하 내부전극간의 겹칩길이(a)가 내부전극의 길이(L)에 대해 길게 할 수 있는 것이다. 즉, 도 1에서 내부전극의 길이(L)에 대해 상하 내부전극간의 겹침길이(a)를 a=0.7L~0.8L로 하여 내부전극의 겹침면적을 크게 할 수 있는 것이다. Since the breakdown voltage is increased in this manner, the thickness of the dielectric layer can be reduced, and the overlapping chip length a between the upper and lower internal electrodes can be made longer with respect to the length L of the internal electrodes. That is, in FIG. 1, the overlapping area a between the upper and lower inner electrodes is a = 0.7L to 0.8L with respect to the length L of the inner electrode, thereby increasing the overlapping area of the inner electrode.
이하, 본 발명을 실시예를 통하여 보다 구체적으로 설명한다. Hereinafter, the present invention will be described in more detail with reference to Examples.
[실시예]EXAMPLE
2L mill jar에 직경 3mm의 볼을 3.5kg 채운 후 아래 표 1와 동일한 조성으로 파우더 총 무게 400g이 되도록 칭량하여 용매 138g, 바인더 121.44g, 분산제 1.2g과 함께 조합하여 24시간 분쇄하였다. 이때, 용매는 에탄올(Ethanol): 톨루엔(Toluene)=6:4로 조합된 것을 사용했으며, 바인더는 B-79 수지와 용매가 1:3, 가소제/수지=30%가 되도록 조합된 것을 사용했다.After filling 3.5 kg of a ball having a diameter of 3 mm in a 2 L mill jar, it was weighed to have a total weight of 400 g with the same composition as in Table 1 below, and pulverized for 24 hours in combination with a solvent 138 g, a binder 121.44 g, and a dispersant 1.2 g. In this case, the solvent used was a combination of ethanol: toluene = 6: 4, and the binder used was a combination of B-79 resin and solvent 1: 3, plasticizer / resin = 30%. .
상기에서 얻은 슬러리를 닥터 블레이드법으로 25㎛두께로 성형하여 시트를 얻고, 이 시트를 5개씩 겹쳐 1층의 세라믹층을 형성한 다음, 이 세라믹층위에 내부전극재료인 금속 페이스트를 인쇄한 후 다시 세라믹 층을 올리고 인쇄하는 것을 반복 하여 가운데 세라믹 층이 7층이 되도록 쌓았다. The slurry obtained above was molded to a thickness of 25 μm by a doctor blade method to obtain a sheet, and the sheets were stacked five by one to form a single ceramic layer, and then the metal paste, which is an internal electrode material, was printed on the ceramic layer. Raising and printing the ceramic layer was repeated so that the middle ceramic layer was stacked to seven layers.
이 적층체를 박스오븐에서 6시간 건조하여 금속의 용매를 제거한 후 등방향 압축기(iso press)에 넣고 700kg의 압력을 가해 압착했다. 이 압착된 적층체를 (3.2×1.6)㎟ 크기로 절단하여 칩을 얻었다.The laminate was dried in a box oven for 6 hours to remove the solvent from the metal, placed in an iso press, and pressed under a pressure of 700 kg. This compressed laminate was cut into a (3.2 × 1.6) mm 2 size to obtain a chip.
이 칩을 박스오븐에 넣어 250℃에서 22시간 가열하여 바인더를 제거하고 연속식(continuous type) 로에서 1290℃에 2시간 유지 되도록 (총 profile 26시간) 소성 하였다. The chip was placed in a box oven and heated at 250 ° C. for 22 hours to remove the binder and calcined to be kept at 1290 ° C. for 2 hours in a continuous furnace (total profile 26 hours).
소성된 칩을 바렐에서 볼, SiC 가루와 함께 넣어 35시간 회전하여 연마하였다. The calcined chips were put together with balls and SiC powder in a barrel and rotated and polished for 35 hours.
연마후 칩의 양 끝에 Cu 전극을 도포하고 915℃에서 가열하여 전극을 소성하였다. After polishing, a Cu electrode was applied to both ends of the chip and heated at 915 ° C. to bake the electrode.
전극 소성이 끝난 칩을 Ni/Sn-Pb로 도금 처리하여 최종 MLCC를 얻었다. 이 MLCC의 전기적 특성을 측정하고 그 결과를 표 2에 나타내었다. The chip after electrode firing was plated with Ni / Sn-Pb to obtain a final MLCC. The electrical properties of this MLCC were measured and the results are shown in Table 2.
표 1, 2에 나타난 바와 같이, 발명재(1~3)은 절연저항(IR)과 파괴전압(BDV)이 비교재에 비해 높은 것을 알 수 있다. SrZrO3가 첨가된 발명재(2)가 절연저항과 파괴전압이 가장 높다.As shown in Tables 1 and 2, it can be seen that the inventive materials 1 to 3 have higher insulation resistance IR and breakdown voltage BDV than the comparative material. Invention material 2 to which SrZrO 3 was added has the highest insulation resistance and breakdown voltage.
한편, 표 1의 유전체중에서 비교재(1, 3)과 발명재(1, 2, 3)에 대해 동일조성으로 여러개 적층세라믹 커패시터를 제조하고, 동일조성으로 제조된 적층세라믹 커패시터의 파괴전압을 측정하여 파괴전압의 분산정도를 도 2에 나타내었다. Meanwhile, among the dielectrics of Table 1, a plurality of multilayer ceramic capacitors were manufactured in the same composition for the comparative materials (1, 3) and the inventive materials (1, 2, 3), and the breakdown voltage of the multilayer ceramic capacitors manufactured in the same composition was measured. The dispersion degree of breakdown voltage is shown in FIG.
도 2에 나타난 바와 같이, 파괴전압의 분산정도 발명재 2가 가장 적음을 알 수 있다. 즉, 발명재 2의 기울기(Weiull 계수치)가 가장 크게 나타났다. 발명재2는 BaTiO3 + MnO2 + MgCO3 + R2O3(R: Y 또는 란탄계열원소에서 선택된 적어도 1종) + BaxCa(1-x)SiO3에 SrZrO3가 추가된 것이다.As shown in FIG. 2, it can be seen that Inventive Material 2 has the least degree of dispersion of breakdown voltage. That is, the slope (Weiull coefficient value) of Inventive Material 2 was the largest. Invention, material 2 is BaTiO 3 + MnO 2 + MgCO 3 + R 2 O 3: to which the (R at least one member selected from Y, or lanthanides) + Ba x Ca (1- x) SrZrO 3 to SiO 3 added.
[실시예 2]Example 2
실시예 1에서 BaTiO3 100몰에 대해 BaxCa(1-x)SiO3를 1.9몰 첨가하고(SrZrO3 배제), 여기에 MnO2, MgCO3 , R2O3는 표 3과 같이 첨가하여 유전체를 조성하는 것을 제외하여 실시예 1과 동일한 방법으로 하여 슬러리를 얻고, 이 슬러리를 닥터브레이드법으로 성형하여 23㎛의 시트를 얻고 이 시트를 5개씩 겹쳐 1층의 세라믹층을 형성한 다음, 이 세라믹층위에 내부전극재료인 금속페이스트를 인쇄한 후 다시 세라믹층을 올리고 인쇄하는 것을 반복하여 세라믹층이 7층이 되도록 쌓았다.In Example 1, 1.9 moles of Ba x Ca (1-x) SiO 3 was added to 100 moles of BaTiO 3 ( excluding SrZrO 3 ), and MnO 2 , MgCO 3 , and R 2 O 3 were added as shown in Table 3 below. A slurry was obtained in the same manner as in Example 1 except that a dielectric was formed, and the slurry was molded by a doctor blade method to obtain a sheet having a thickness of 23 µm, and the sheets were stacked five by one to form a ceramic layer of one layer. After printing the metal paste, which is an internal electrode material, on the ceramic layer, the ceramic layer was repeatedly raised and printed, and the ceramic layers were stacked to form seven layers.
이 세라믹층을 실시예 1과 동일하게 압착후의 공정을 적용하여 최종 MLCC를 제조하였다. This ceramic layer was applied in the same manner as in Example 1 after the compression to prepare a final MLCC.
표 3, 4에 나타난 바와 같이, MgCO3≥R2O3>MnO2를 만족하는 발명예(4, 5)의 경우 파괴전압과 절연저항이 높았다. 발명예(4)의 경우 bMnO2, cMgCO3, dR2O3 의 첨가량의 비가 0.1(b):1.0(d):2.0(c)의 비를 만족한 것으로, 발명예(5)가 고온 절연저항이 낮아진데 반해 고온절연저항도 좋았다.As shown in Tables 3 and 4, inventive examples (4 and 5) satisfying MgCO 3 ≧ R 2 O 3 > MnO 2 had high breakdown voltage and insulation resistance. In the case of invention example (4), the ratio of the addition amount of bMnO 2 , cMgCO 3 , dR 2 O 3 satisfied the ratio of 0.1 (b): 1.0 (d): 2.0 (c). While the resistance is low, the high temperature insulation resistance is also good.
상술한 바와 같이, 본 발명에 따르면, 종래의 유전체와 동일 두께로 성형 할 때 더 높은 절연저항과 파괴전압을 갖는다. 따라서, MLCC 제조시 비교적 얇은 유전체층으로 하더라도 동일 수준이상의 특성을 가지게 되므로, 제품 두께가 더 얇게 할 수 있어 높은 용량을 설계할 수 있는 유용한 효과가 있다. As described above, according to the present invention, when molded to the same thickness as a conventional dielectric, it has a higher insulation resistance and breakdown voltage. Therefore, even when a relatively thin dielectric layer has a characteristic of the same level or more when manufacturing the MLCC, the product thickness can be made thinner, there is a useful effect that can design a high capacity.
도 1은 적층세라믹 커패시터의 일례도1 is an example of a multilayer ceramic capacitor
도 2는 적층세라믹 커패시터의 파괴전압의 분산정도를 나타내는 그래프2 is a graph showing the dispersion degree of breakdown voltage of a multilayer ceramic capacitor
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521267A (en) * | 1991-07-15 | 1993-01-29 | Tdk Corp | Laminated ceramic chip capacitor |
| US5335139A (en) * | 1992-07-13 | 1994-08-02 | Tdk Corporation | Multilayer ceramic chip capacitor |
| JPH06215979A (en) * | 1993-01-21 | 1994-08-05 | Tdk Corp | Reduction-resistant ferroelectric porcelain composite |
| US5862034A (en) * | 1994-10-19 | 1999-01-19 | Tdk Corporation | Multilayer ceramic chip capacitor |
| US6185087B1 (en) * | 1999-04-08 | 2001-02-06 | Kemet Electronics Corp. | Multilayer ceramic chip capacitor with high reliability compatible with nickel electrodes |
| JP2001089231A (en) * | 1999-07-21 | 2001-04-03 | Tdk Corp | Dielectric porcelain composition and electronic parts |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521267A (en) * | 1991-07-15 | 1993-01-29 | Tdk Corp | Laminated ceramic chip capacitor |
| US5335139A (en) * | 1992-07-13 | 1994-08-02 | Tdk Corporation | Multilayer ceramic chip capacitor |
| JPH06215979A (en) * | 1993-01-21 | 1994-08-05 | Tdk Corp | Reduction-resistant ferroelectric porcelain composite |
| US5862034A (en) * | 1994-10-19 | 1999-01-19 | Tdk Corporation | Multilayer ceramic chip capacitor |
| US6185087B1 (en) * | 1999-04-08 | 2001-02-06 | Kemet Electronics Corp. | Multilayer ceramic chip capacitor with high reliability compatible with nickel electrodes |
| JP2001089231A (en) * | 1999-07-21 | 2001-04-03 | Tdk Corp | Dielectric porcelain composition and electronic parts |
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