KR100499637B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100499637B1 KR100499637B1 KR10-2003-0020508A KR20030020508A KR100499637B1 KR 100499637 B1 KR100499637 B1 KR 100499637B1 KR 20030020508 A KR20030020508 A KR 20030020508A KR 100499637 B1 KR100499637 B1 KR 100499637B1
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- buried portion
- metal buried
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- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Abstract
본 발명은 TFR(Thin Film Resistor)의 콘택을 TFR의 하부에 형성함으로써, 식각 정지층 형성 공정을 생략함으로써 공정의 단순화와 TFR의 손상을 방지하는 반도체 소자의 제조 방법에 관한 것이다. 본 발명에 따른 반도체 소자 제조 방법은 반도체 기판 상부의 소정 영역을 식각하여 제1 비아, 제2 비아 및 제3 비아를 각각 형성하는 단계와, 상기 제1 비아, 제2 비아 및 제3 비아를 각각 매립하는 제1 금속 매립부, 제2 금속 매립부 및 제3 금속 매립부를 형성하는 단계와, 상기 제1 금속 매립부, 제2 금속 매립부 및 제3 금속 매립부의 소정 영역을 각각 노출시키는 개구부들을 구비한 식각 정지층 패턴을 전체 표면 상부에 형성하는 단계와, 전체 표면 상부에 상기 개구부들을 매립하는 배리어 금속층을 형성하는 단계와, 상기 제1 금속 매립부 상부의 배리어 금속층 상에 캐패시터용 절연층 및 상부 전극의 적층 구조를 형성하는 단계와, 상기 배리어 금속층을 패터닝하여 하부 전극과 상기 제2 금속 매립부 및 제3 금속 매립부를 접속하는 박막 레지스터를 형성하는 단계와, 전체 표면 상부에 평탄화된 층간 절연막을 형성하는 단계와, 상기 층간 절연막 및 식각 정지층 패턴을 선택적으로 식각하여 상기 상부 전극, 상기 제1, 제2 및 제3 금속 매립부의 소정 영역을 각각 노출시키는 콘택홀들을 형성하는 단계 및 상기 콘택홀들을 매립하는 콘택 플러그를 각각 형성하는 단계를 포함한다.The present invention relates to a method of fabricating a semiconductor device that forms a contact of a thin film resistor (TFR) under the TFR, thereby eliminating an etch stop layer forming process and thus preventing the damage to the TFR. A method of manufacturing a semiconductor device according to the present invention may include forming first vias, second vias, and third vias by etching predetermined regions on a semiconductor substrate, and forming the first vias, the second vias, and the third vias, respectively. Forming a buried first metal buried portion, a second metal buried portion, and a third metal buried portion, and openings exposing predetermined regions of the first metal buried portion, the second metal buried portion, and the third metal buried portion, respectively; Forming an etch stop layer pattern on the entire surface, forming a barrier metal layer filling the openings on the entire surface, an insulating layer for a capacitor on the barrier metal layer on the first metal buried portion, and Forming a stacked structure of an upper electrode, and patterning the barrier metal layer to form a thin film resistor that connects the lower electrode to the second metal buried portion and the third metal buried portion. Forming a planarized interlayer insulating film over the entire surface, and selectively etching the interlayer insulating film and the etch stop layer pattern to form a predetermined region of the upper electrode, the first, second and third metal buried portions. Forming contact holes exposing each of the contact holes and forming contact plugs respectively filling the contact holes.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 TFR(Thin Film Resistor)의 콘택을 TFR의 하부에 형성하고, 1개의 식각 정지층만을 사용함으로써 공정의 단순화를 가능하게 하며 TFR의 손상을 방지하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a contact of a thin film resistor (TFR) is formed under the TFR, and a single etch stop layer is used to simplify the process and prevent damage to the TFR. A method for manufacturing a semiconductor device.
도면을 참조하여 종래 기술에 따른 반도체 소자 제조 방법 및 문제점을 설명하면 다음과 같다.Referring to the drawings, a semiconductor device manufacturing method and a problem according to the prior art will be described.
도 1a 내지 도 1f는 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단면도들이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체 기판(10) 상부의 소정 영역을 식각 및 매립하여 금속 매립부(20)를 형성한다.Referring to FIG. 1A, a metal buried portion 20 is formed by etching and filling a predetermined region on an upper portion of the semiconductor substrate 10.
도 1b를 참조하면, 금속 매립부(20)의 소정 영역을 각각 노출시키는 개구부를 구비한 제1 식각 정지층(30)을 전체 표면 상부에 형성한다.Referring to FIG. 1B, a first etch stop layer 30 having openings for exposing predetermined regions of the metal buried portion 20 is formed on the entire surface.
도 1c를 참조하면, 전체 표면 상부에 상기 개구부를 매립하는 배리어 금속층(40), 캐패시터용 절연층(50) 및 상부 전극용 도전층(60)을 순차적으로 형성한다.Referring to FIG. 1C, the barrier metal layer 40, the capacitor insulating layer 50, and the upper electrode conductive layer 60 filling the openings are sequentially formed on the entire surface.
도 1d를 참조하면, 캐패시터용 절연층(50) 및 상부 전극용 도전층(60)을 선택적으로 식각하여 금속 매립부(20) 상부에 캐패시터 절연막(55) 및 상부 전극(65)의 적층 구조를 형성한 후 배리어 금속층(40)을 패터닝하여 하부 전극(45)과 박막 레지스터를 형성한다.Referring to FIG. 1D, the capacitor insulating layer 50 and the upper electrode conductive layer 60 are selectively etched to form a stacked structure of the capacitor insulating layer 55 and the upper electrode 65 on the metal buried portion 20. After forming, the barrier metal layer 40 is patterned to form the lower electrode 45 and the thin film resistor.
도 1e를 참조하면, 전체 표면 상부에 제2 식각 정지층(70)을 형성한다.Referring to FIG. 1E, the second etch stop layer 70 is formed on the entire surface.
도 1f를 참조하면, 전체 표면 상부에 평탄화된 층간 절연막(80)을 형성한 후 층간 절연막(80), 제2 식각 정지층(70) 및 제1 식각 정지층(30)을 선택적으로 식각하여 상부 전극(65) 및 금속 매립부(20)의 소정 영역을 각각 노출시키는 콘택홀들을 형성한 후 상기 콘택홀들을 매립하여 콘택 플러그(90a, 90b, 90c, 90d)를 각각 형성한다.Referring to FIG. 1F, after the planarized interlayer insulating layer 80 is formed on the entire surface, the interlayer insulating layer 80, the second etch stop layer 70, and the first etch stop layer 30 are selectively etched. After forming contact holes exposing predetermined regions of the electrode 65 and the metal buried portion 20, the contact holes are filled to form contact plugs 90a, 90b, 90c, and 90d, respectively.
상기의 종래 기술에 따른 반도체 소자의 제조 방법은 캐패시터의 하부 전극과의 콘택을 형성하기 위하여 2층 구조의 식각 정지층을 식각 하여야 하는 반면, 상부 전극 및 TFR과의 콘택을 형성하기 위하여 단일층으로 이루어진 식각 정지층을 식각하여야 하므로, TFR이 손상되어 특성이 저하되며, 2개의 식각 정지층을 형성하여야 하므로 공정이 복잡하다는 문제가 있다.In the method of manufacturing the semiconductor device according to the related art, the etch stop layer having a two-layer structure must be etched to form a contact with the lower electrode of the capacitor, while the single layer is used to form a contact with the upper electrode and the TFR. Since the etch stop layer has to be etched, the TFR is damaged to deteriorate the characteristics, and the process is complicated because two etch stop layers must be formed.
상기 문제점을 해결하기 위하여, 1개의 식각 정지층만을 사용하여 공정을 단순화하며, TFR의 콘택을 TFR의 하부에 형성하여 식각 공정시 TFR의 손상을 방지하는 반도체 소자의 제조 방법을 제공하는 것을 그 목적으로 한다.In order to solve the above problems, to simplify the process using only one etch stop layer, to provide a method of manufacturing a semiconductor device that prevents damage to the TFR during the etching process by forming a contact of the TFR under the TFR. It is done.
본 발명에 따른 반도체 소자 제조 방법은 MIM 캐패시터와 박막 레지스터를 구비한 반도체 소자의 제조 방법에 있어서, 반도체 기판 상부의 소정 영역을 식각하여 제1 비아, 제2 비아 및 제3 비아를 각각 형성하는 단계와, 상기 제1 비아, 제2 비아 및 제3 비아를 각각 매립하는 제1 금속 매립부, 제2 금속 매립부 및 제3 금속 매립부를 형성하는 단계와, 상기 제1 금속 매립부, 제2 금속 매립부 및 제3 금속 매립부의 소정 영역을 각각 노출시키는 개구부들을 구비한 식각 정지층 패턴을 형성하는 단계와, 전체 표면 상부에 상기 개구부들을 매립하는 배리어 금속층을 형성하는 단계와, 상기 제1 금속 매립부 상부의 배리어 금속층 상에 캐패시터용 절연층 및 상부 전극의 적층 구조를 형성하는 단계와, 상기 적층 구조 및 배리어 금속층을 패터닝하여 상기 제1 금속 매립부에 접속되는 하부 전극과 상기 제2 금속 매립부 및 제3 금속 매립부에 접속되는 박막 레지스터를 형성하는 단계와, 전체 표면 상부에 평탄화된 층간 절연막을 형성하는 단계와, 상기 층간 절연막 및 식각 정지층 패턴을 선택적으로 식각하여 상기 상부 전극, 상기 제1 금속 매립부, 제2 금속 매립부 및 제3 금속 매립부의 소정 영역을 각각 노출시키는 콘택홀들을 형성하는 단계 및 상기 콘택홀들을 매립하여 상기 제1 금속 매립부, 제2 금속 매립부 및 제3 금속 매립부에 각각 접속되는 콘택 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.In the method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device having a MIM capacitor and a thin film resistor, forming a first via, a second via, and a third via by etching a predetermined region on the semiconductor substrate, respectively. And forming a first metal buried portion, a second metal buried portion, and a third metal buried portion filling the first via, the second via, and the third via, respectively, and forming the first metal buried portion and the second metal buried portion. Forming an etch stop layer pattern having openings for exposing predetermined regions of the buried portion and the third metal buried portion, forming a barrier metal layer filling the openings over the entire surface, and forming the first metal buried portion Forming a stacked structure of a capacitor insulating layer and an upper electrode on the barrier metal layer on the upper portion of the upper portion; patterning the stacked structure and the barrier metal layer to form the first metal Forming a lower electrode connected to the lip portion and a thin film resistor connected to the second metal buried portion and the third metal buried portion, forming a planarized interlayer insulating film over the entire surface, the interlayer insulating film and the etch stop Selectively etching the layer pattern to form contact holes exposing predetermined regions of the upper electrode, the first metal buried part, the second metal buried part, and the third metal buried part; and filling the contact holes And forming contact plugs respectively connected to the first metal buried portion, the second metal buried portion, and the third metal buried portion.
이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 2a를 참조하면, 반도체 기판(100) 상부의 소정 영역을 식각하여 제1 비아, 제2 비아 및 제3 비아를 각각 형성하고 이를 매립하여 제1 금속 매립부(120a), 제2 금속 매립부(120b) 및 제3 금속 매립부(120c)를 각각 형성한다. 여기서, 제1 금속 매립부(120a), 제2 금속 매립부(120b) 및 제3 금속 매립부(120c)는 반도체 기판(100) 표면에 상기 제1 비아, 제2 비아 및 제3 비아를 매립하는 금속층(미도시), 바람직하게는 Cu층을 형성하고 이를 평탄화하여 형성한다. 또한 제1 금속 매립부(120a), 제2 금속 매립부(120b) 및 제3 금속 매립부(120c)는 반도체 기판(100)과의 계면에 배리어층(미도시)을 각각 구비할 수 있다.Referring to FIG. 2A, a first region, a second via, and a third via are formed by etching a predetermined region of the upper portion of the semiconductor substrate 100, and filling the first via, the second buried portion 120a and the second metal buried portion. 120b and the third metal buried portion 120c are formed, respectively. Here, the first metal buried portion 120a, the second metal buried portion 120b, and the third metal buried portion 120c fill the first via, the second via, and the third via on the surface of the semiconductor substrate 100. To form a metal layer (not shown), preferably Cu layer and planarizing it. In addition, the first metal buried portion 120a, the second metal buried portion 120b, and the third metal buried portion 120c may include barrier layers (not shown) at interfaces with the semiconductor substrate 100, respectively.
도 2b를 참조하면, 제1 금속 매립부(120a), 제2 금속 매립부(120b) 및 제3 금속 매립부(120c)의 소정 영역을 각각 노출시키는 개구부들을 구비한 식각 정지층 패턴(130)을 전체 표면 상부에 형성한다. 식각 정지층 패턴(130)은 전체 표면 상부에 식각 정지층(미도시)를 형성하고 사진 및 식각 공정에 의해서 형성하는 것이 바람직하다.Referring to FIG. 2B, an etch stop layer pattern 130 having openings exposing predetermined regions of the first metal buried portion 120a, the second metal buried portion 120b, and the third metal buried portion 120c, respectively. On top of the entire surface. The etch stop layer pattern 130 is preferably formed by forming an etch stop layer (not shown) on the entire surface and by a photograph and an etching process.
도 2c를 참조하면, 전체 표면 상부에 상기 개구부들을 매립하는 배리어 금속층(140), 캐패시터용 절연층(150) 및 상부 전극용 도전층(160)을 순차적으로 형성한다. 여기서, 배리어 금속층(140)은 TaN, Ta, Ti, TiN 또는 Ru로 형성하는 것이 바람직하며, TaN 또는 TiN를 이용하는 경우에는 질소 농도는 각각 0 내지 95%인 것이 바람직하다. 또한, 배리어 금속층(140)은 바람직하게는 CVD법, ALD법 또는 스퍼터링법을 비정질로 형성하는 것이 바람직하며, 캐패시터용 절연층(150)은 SiN, SiO2, SiC, SiON, SiOC, Ta2O5, HfO2, Al2O3 또는 ZrO2로 형성하며, 상부 전극용 도전층(160)은 TaN, Ta, Ti, TiN 또는 Ru로 형성하는 것이 바람직하다.Referring to FIG. 2C, the barrier metal layer 140 filling the openings, the insulating layer 150 for the capacitor, and the conductive layer 160 for the upper electrode are sequentially formed on the entire surface. Here, the barrier metal layer 140 is preferably formed of TaN, Ta, Ti, TiN or Ru, and when using TaN or TiN, the nitrogen concentration is preferably 0 to 95%, respectively. In addition, the barrier metal layer 140 is preferably formed of an amorphous CVD method, ALD method or sputtering method, the capacitor insulating layer 150 is SiN, SiO 2 , SiC, SiON, SiOC, Ta 2 O 5 , HfO 2 , Al 2 O 3, or ZrO 2 , and the upper electrode conductive layer 160 is preferably formed of TaN, Ta, Ti, TiN, or Ru.
도 2d를 참조하면, 캐패시터용 절연층(150) 및 상부 전극용 도전층(160)을 선택적으로 식각하여 제1 금속 매립부(120a) 상부에 캐패시터 절연막(155) 및 상부 전극(165)의 적층 구조를 형성한 후 배리어 금속층(140)을 패터닝하여 하부 전극(145)과 제2 금속 매립부(120b) 및 제3 금속 매립부(120c)를 접속하는 박막 레지스터를 형성한다.Referring to FIG. 2D, the capacitor insulating layer 150 and the upper electrode conductive layer 160 are selectively etched to stack the capacitor insulating layer 155 and the upper electrode 165 on the first metal buried portion 120a. After forming the structure, the barrier metal layer 140 is patterned to form a thin film resistor that connects the lower electrode 145, the second metal buried portion 120b, and the third metal buried portion 120c.
도 2e를 참조하면, 전체 표면 상부에 평탄화된 층간 절연막(180)을 형성한다.Referring to FIG. 2E, the planarized interlayer insulating layer 180 is formed on the entire surface.
도 2f를 참조하면, 층간 절연막(180) 및 식각 정지층 패턴(130)을 선택적으로 식각하여 상부 전극(165), 제1, 제2 및 제3 금속 매립부(120a, 120b, 120c)의 소정 영역을 각각 노출시키는 콘택홀들을 형성한 후 상기 콘택홀들을 매립하여 콘택 플러그(190a, 190b, 190c, 190d)를 각각 형성한다. 여기서, 콘택 플러그(190a, 190b, 190c, 190d)는 층간 절연막(180) 및 상부 전극(165), 상기 제1, 제2 및 제3 금속 매립부(120a, 120b, 120c)와의 계면에 배리어층(미도시)을 각각 구비할 수도 있다.Referring to FIG. 2F, the interlayer insulating layer 180 and the etch stop layer pattern 130 may be selectively etched to determine the upper electrode 165, the first, second, and third metal buried portions 120a, 120b, and 120c. After contact holes are formed to expose regions, the contact holes are filled to form contact plugs 190a, 190b, 190c, and 190d, respectively. The contact plugs 190a, 190b, 190c, and 190d may have a barrier layer at an interface between the interlayer insulating layer 180, the upper electrode 165, and the first, second, and third metal buried portions 120a, 120b, and 120c. (Not shown) may be provided, respectively.
본 발명에 따른 반도체 소자의 제조 방법은 1개의 식각 정지층만을 사용하여 공정을 단순화하며, TFR의 콘택을 TFR의 하부에 형성하여 식각 공정시 TFR의 손상을 방지하여 소자의 특성을 향상시키는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention simplifies the process by using only one etch stop layer, and forms a contact of the TFR under the TFR to prevent damage to the TFR during the etching process, thereby improving the characteristics of the device. have.
도 1a 내지 도 1f는 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단면도.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
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