KR100498229B1 - Apparatus for burst-mode clock and data recovery employing jitter reduction method - Google Patents

Abstract

The present invention relates to a burst-mode clock and data reproducing apparatus which prevents the accumulation of phase errors of reproduction clocks generated when the same data is continuously input and thereby the error of reproduction data. By using the jitter reduction method, the jitter of the reproduction clock is reduced by preventing the phase error of the reproduction clock even when a burst signal successive of the same data is input. Therefore, there is an effect that the data reproduction error is reduced.

Description

Burst-mode clock and data reproducing apparatus using jitter reduction method {APPARATUS FOR BURST-MODE CLOCK AND DATA RECOVERY EMPLOYING JITTER REDUCTION METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst-mode clock and data reproducing apparatus using a jitter reduction method, and more particularly, to accumulate phase error of a reproducing clock generated when the same data is continuously input and A burst-mode clock and data reproducing apparatus which prevents errors of reproducing data caused.

The Burst-Mode Clock and Data Recovery (CDR), which consists of a gated oscillator (GO), forcibly synchronizes the phase of the playback clock with the phase of the input data when data transition occurs. The advantage is that you can sample the center of your data. However, if the input data rate is not the same as the frequency of the gate oscillator, when consecutive identical data is input, a phase error accumulates in a clock to be reproduced, and an error occurs during a data decision.

The frequency of the gate oscillator is determined by the feedback delay time of the gate oscillator. When this feedback delay time is equal to the half period of the input data, the input data rate and the frequency of the gate oscillator become the same, so that the same continuous data Even if is input, it can play the ideal clock. However, it is impossible to make the feedback delay time exactly match the half period of the input data, so it is inevitable to accumulate the phase error and increase the jitter of the clock when the same data is continuously input.

In addition, the maximum allowable number of identical data is determined according to the difference between the feedback delay time and the half period of the input data.If the number of consecutive identical data exceeds the maximum allowable number, the data determination error due to the accumulation of clock phase error Will occur. Therefore, a new additional circuit design is needed to prevent the accumulation of phase errors in the reproduction clock and increase the maximum allowable number of identical data.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned shortcomings, and the phase error accumulation of the reproduction clock generated when the same data is continuously input among the 155Mb / s burst data for a passive optical network (PON) and the error of the reproduction data thereby. It is an object of the present invention to provide a burst-mode clock and data reproducing apparatus using a jitter reduction method that prevents the use of a jitter reduction circuit to realize a low-error and high-performance burst-mode clock and data regenerator.

The present invention for achieving the above object is an edge detector for detecting the edge of the input data (edge detector); A gate oscillator for performing a NAND operation of the NAND operation of the edge detection signal provided from the edge detection unit as two inputs to regenerate a clock, and delaying the output of the NAND operation with the other signal; Jitter for preventing the accumulation of phase error of the reproduction clock generated when the input data is input as the same data and the resulting error of the reproduction data by adjusting the delay time of the gate oscillator in response to the reproduction clock provided from the gate oscillator. Jitter reduction circuit; And a data decision unit configured to receive the input data and the reproduction clock to reproduce data.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing an embodiment of a burst-mode clock and data reproducing apparatus using the jitter reduction method according to the present invention, which includes an edge detector 10, a gate oscillator 16, a jitter reduction unit 22, and data. It consists of a regeneration unit 24. The edge detector 10 includes a delay unit 12 and an exclusive NOR gate 14, and the gate oscillator 16 includes a NAND gate 18 and a programmable delay element. Chip: PDC) 20.

In the figure, the edge detector 10 detects an edge of input Non-Return-to-Zero (NRZ) data as shown in FIG. 2A and provides an edge detection signal as shown in FIG. 2A to the gate oscillator 16. At this time, the delay unit 12 in the edge detector 10 delays the input data by half of the input data period and provides it to the lower end of the exclusive NOR gate 14. The exclusive NOR gate 14 performs an Exclusive NOR operation on the input data and the delayed input data provided from the delay unit 12 to provide an upper portion of the NAND gate 18 in the gate oscillator 16.

The gate oscillator 16 performs a NAND operation using the edge detection signal provided from the edge detection unit 10 and another signal as two inputs, and reproduces the clock as shown in FIG. 2A, but uses the delayed output of the NAND operation with another signal. do. At this time, the NAND gate 18 in the gate oscillator 16 performs a NAND operation on a signal provided from the exclusive NOR gate 14 and a delayed feedback signal provided from the program delay element 20 to reproduce the clock. The program delay element 20 delays the output of the NAND gate 18 by a half period of the input data and provides it to the lower end of the NAND gate 18.

The jitter saver 22 adjusts the delay time of the program delay element 20 in the gate oscillator 16 in response to the regeneration clock provided from the gate oscillator 16 to reproduce the input data when the input data is input as the same data. Accumulation of phase error of the clock and resulting error of reproduction data is prevented.

The data reproducing unit 24 receives the input data and the reproducing clock provided from the gate oscillator 16 to reproduce the data. In this case, an external clock may be provided to the data reproducing unit 24 instead of the reproducing clock.

FIG. 2B is a waveform diagram illustrating a reproduction clock when the feedback delay time of the gate oscillator 16 illustrated in FIG. 1 is different from the half period of the input data. The output of the input data and the edge detector 10 are different from those of FIG. 2A. Although the same, the clock reproduced by the gate oscillator 16 is different from the case of FIG. 2A.

The above-described gate oscillator 16 forcibly synchronizes the phase of the reproduction clock with the phase of the input data when data transition occurs. Therefore, the gate oscillator 16 does not generate the phase error accumulation of the reproduction clock even if the feedback delay time of the program delay element 20 does not coincide with the half period of the input data when the transition of the input data occurs continuously. On the other hand, if the feedback delay time of the program delay element 20 is equal to the half period of the data when no transition of the input data occurs and the same continuous data is input, the phase error does not occur in the clock, but a slight difference between the two values occurs. Errors also cause the accumulation of phase errors in the clock, resulting in errors in data reproduction. Therefore, a new jitter reduction method is needed to prevent the phase error accumulation and data reproduction of the clock.

FIG. 3A is a block diagram illustrating an embodiment of the jitter reduction unit 22 shown in FIG. 1, including a quarter divider 26, a half divider 28, and an up / down counter. 30, and a dip switch 32.

In the figure, the quarter divider 26 in the jitter saver 22 divides the reproduction clock provided from the gate oscillator 16 by a quarter to provide a clock signal stage and a half divider of the up-down counter 30. Provided by 28.

The half divider 28 divides the quarter divided reproduction clock provided from the quarter divider 26 by half and provides it to the S1 input of the up-down counter 30.

The up-down counter 30 receives each output provided from the quarter divider 26 and the half divider 28 as a clock signal stage and an S1 input, and counts up and down to respectively program delay elements 20 in the gate oscillator 16. ) Is provided as data for delay control.

FIG. 3B is a diagram showing an operation table of the up-down counter 30 shown in FIG. 3A, in which S1 periodically has a logical high value and a logical low value, while S2 always has a logic low value. The up-down counter (30) is used because it does not connect to any signal (or to a logic low value), and therefore has a logic low value (use a device with a logic low value if S2 is not connected without any signal connection). ) Has only two of the four operations: 'preset' and 'count down'. Here, the 'preset' operation returns the output value of the up-down counter 30 to the initial input value of the predetermined up-down counter 30, and the 'count down' operation lowers the output value of the current up-down counter 30 by one step. . Since the program delay element 20 has an accuracy of 20 ps, the feedback delay time cannot be made to exactly match T / 2. Therefore, after adjusting the input of the up-down counter of the jitter reduction circuit so that the delay time of the program delay element is directly larger than T / 2, the program delay element (using the 'preset' and 'count down' operations of the up-down counter) The delay time of 20) is periodically changed between the large value and the small value with T / 2 in between. For example, if the half period value of the input data is T _d and the delay time that can be implemented by the program delay element is T _d -ΔT or T _d -ΔT + 20 ps, the delay time of the program delay element 20 is T _d -ΔT + 20 ps Through the combination of the dip switch 32 to the up-down counter 30 (ie, the combination of the 6-bit dip switch is connected to the data input of the up-down counter to determine the initial value of the program delay element 20 in the preset state). .) After inputting an initial value used as a reference signal by providing input data, the delay time of the program delay element 20 is set to T _d -ΔT by using the 'preset' and 'count down' operations of the up-down counter 30. It periodically changes to two values of T _d -ΔT + 20 ps. In conclusion, it is possible to prevent the accumulation of phase error, which occurs when consecutive identical data is input.

FIG. 4A is a circuit diagram of an embodiment of the data reproducing unit 24 shown in FIG. 1, wherein the first and second delay units 34 and 36, the program delay element 38, and the first, second, and first units are shown. 3D flip-flops 40, 42, 44, first and second exclusive OR gates 46, 48, and up-down counters 50. The data reproducing unit 24, unlike the conventional "early-late method" of changing the frequency of the voltage controlled oscillator (VCO) using the error information of the phase detector (phase detector), the data sampling information and the up-down counter To change the clock path delay time using.

In the figure, the first delay section 34 delays the input data by half of its input data period and provides it to the D stage of the second delay section 36 and the second D flip-flop 42. The second delay unit 36 delays the delayed input data provided from the first delay unit 34 by half of the input data period and provides the delayed input data to the D stage of the third D flip-flop 44.

The program delay element 38 delays the regeneration clock (or external clock) provided from the gate oscillator 16 in correspondence with the output of the up-down counter 50 so as to first, second, and third D flip-flops 40 and 42. , 44) to each clock signal stage.

The first D flip-flop 40 receives the input data to the D stage and the output of the program delay element 38 to the clock signal stage to perform the D flip-flop operation to output the reproduction data to the Q stage and the / Q stage. Provides the output of to the top input of the first exclusive OR gate 46. The second D flip-flop 42 receives the output of the first delay unit 34 to the D stage and the output of the program delay element 38 to the clock signal stage to perform the D flip flop operation to output the Q stage. Is provided as the bottom input of the first exclusive ora gate 46 and the output of the / Q stage is provided as the top input of the second exclusive ora gate 48. The third D flip-flop 44 receives the output of the second delay unit 36 to the D stage and the output of the program delay element 38 to the clock signal stage to perform the D flip flop operation to output the Q stage. Is provided as the bottom input of the second exclusive or gate 48.

The first exclusive OR gate 46 performs an exclusive OR operation on the signal provided from the / Q terminal of the first D flip flop 40 and the signal provided from the Q terminal of the second D flip flop 42. To the S2 input of the up-down counter 50. The second exclusive OR gate 48 performs an exclusive OR operation on the signal provided from the / Q terminal of the second D flip flop 42 and the signal provided from the Q terminal of the third D flip flop 44. To the S1 input of the up-down counter 50.

The up-down counter 50 receives the respective outputs of the first and second exclusive ora gates 46 and 48 as S2 inputs and S1 inputs, and counts up and down the outputs to the program delay element 38.

FIG. 4B is a diagram showing the principle of operation of the data reproducing unit 24 shown in FIG. Using three sampling values, up-down counter 50 changes the clock's path delay so that the clock can always sample the center of the data. If the clock phase is earlier than the data phase, S1 is logic high and S2 is logic low, and the up-down counter 50 counts up, increasing the clock path delay time and increasing the clock data. Sample the center of On the other hand, if the clock phase is later than the data phase, S1 is logic low and S2 is logic high, so the up and down counters 'count down' to reduce the clock path delay time, allowing the clock to sample the center of the data. Make. In addition, when there is no data transition, the phases of the clock and the data cannot be compared, so S1 and S2 become logic high to perform a "hold" operation, thereby maintaining the clock path delay time unchanged. . Therefore, data can be reproduced not only by the clock reproduced by the clock regenerator but also by using an externally provided clock.

5A is a waveform diagram illustrating a clock that is reproduced when the jitter saver 22 is not used when burst data is input. When a burst signal is consecutively inputted after 1000 pieces of '0' data, the jitter saver ( The clock reproduced by the gate oscillator 16 when 22) is not used is shown. The reproduction clock has a lot of jitter due to the accumulation of phase error due to the input of the same data.

FIG. 5B is a waveform diagram illustrating a clock reproduced when the jitter reduction unit 22 is used when burst data is input. When the same burst signal is input, the waveform is reproduced by the gate oscillator 16 when the jitter reduction unit 22 is used. The clock is shown. When the jitter saver 22 is used, a large amount of jitter can be removed by preventing accumulation of phase errors when the same data is input.

As described above, the present invention reduces the jitter of the reproduction clock by preventing the phase error of the reproduction clock even when a burst signal in which the same data is consecutive is input by using the jitter reduction method. Therefore, there is an effect that the data reproduction error is reduced.

1 is a circuit diagram illustrating an embodiment of a burst-mode clock and data reproducing apparatus using the jitter reduction method according to the present invention;

FIG. 2A is a waveform diagram illustrating a reproduction clock when the feedback delay time of the gate oscillator illustrated in FIG. 1 is equal to half the period of data.

FIG. 2B is a waveform diagram illustrating a reproduction clock when a feedback delay time of the gate oscillator illustrated in FIG. 1 is different from a half period of data.

3A is a block diagram illustrating an embodiment of the jitter reduction unit illustrated in FIG. 1;

3B is a view showing an operation table of the up-down counter shown in FIG. 3A;

4A is a circuit diagram illustrating an embodiment of a data reproducing unit shown in FIG. 1;

4B is a view illustrating an operation principle of the data reproducing unit shown in FIG. 1;

5A is a waveform diagram illustrating a clock reproduced when a jitter reduction method is not used in burst data input;

5B is a waveform diagram showing a clock reproduced when a jitter reduction method is used for burst data input.

<Description of the symbols for the main parts of the drawings>

10 edge detector 12 delay unit

14: Exclusive Noah Gate

16: gate oscillator 18: NAND gate

20, 38: program delay element 22: jitter reduction unit

24: data reproducing section 26: 1/4 divider

28: 1/2 divider 30: up-down counter

32: dip switch 34, 36: first, second delay unit

40, 42, 44: 1st, 2nd, 3rd D flip flop

46, 48: 1st, 2nd exclusive ora gate

50: up-down counter

Claims (5)

An edge detector detecting an edge of the input data; A gate oscillator for performing a NAND operation of the NAND operation of the edge detection signal provided from the edge detection unit as two inputs to regenerate a clock, and delaying the output of the NAND operation with the other signal; Jitter for preventing the accumulation of phase error of the reproduction clock generated when the input data is input as the same data and the resulting error of the reproduction data by adjusting the delay time of the gate oscillator in response to the reproduction clock provided from the gate oscillator. Saving unit; And And a data reproducing unit receiving the input data and the reproducing clock and reproducing the data. The method of claim 1, wherein the edge detector, A delay unit for delaying the input data by half of the input data period; Burst-mode clock and data reproducing apparatus using the jitter reduction method, characterized in that it consists of an Exclusive Noah gate to provide the gate oscillator by performing an Exclusive NOR operation from the input data and the delayed input data provided from the delay unit . The method of claim 1, wherein the gate oscillator, A NAND gate NAND operation of the edge detection signal and the delayed feedback signal; A burst-mode clock and data reproducing apparatus using a jitter reduction method, characterized in that it comprises a program delay element for providing a signal delayed by the output of the NAND gate by a half period of the input data to the NAND gate. The method of claim 3, wherein the jitter reduction unit, A quarter divider for dividing quarter the output of the NAND gate gate; A half divider for half dividing a quarter divided reproduction clock provided from the quarter divider; And An up-down counter which receives each output provided from the quarter divider and the half divider as a clock signal stage and an S1 input, up-down counting them, and provides them to the program delay element to adjust the delay time of the program delay element. A burst mode clock and data reproducing apparatus using the jitter reduction method. The method of claim 1, wherein the data reproduction unit, A first delay unit delaying the input data by half of the input data period; A second delay unit for delaying delayed input data provided from the first delay unit by half of the input data period; A program delay element for delaying the reproduction clock provided from the gate oscillator; A first D flip-flop for receiving the input data to the D stage and the output of the program delay element to a clock signal stage to perform a D flip-flop operation to output reproduction data to the Q stage; A second D flip flop which receives an output of the first delay unit to a D stage and an output of the program delay element to a clock signal stage to perform a D flip flop operation; A third D flip flop receiving an output of the second delay unit through a D stage and an output of the program delay element through a clock signal stage to perform a D flip flop operation; A first exclusive ora gate for performing an exclusive ora operation on a signal provided from the / Q end of the first D flip flop and a signal provided from the Q end of the second D flip flop; A second exclusive ora gate for performing an exclusive ora operation on a signal provided from the / Q end of the second D flip flop and a signal provided from the Q end of the third D flip flop; And And an up-down counter that receives the outputs of the first and second exclusive ora gates as an S2 input and an S1 input, respectively, and counts them up and down to provide them to the program delay device to adjust the delay time of the program delay device. Burst-mode clock and data reproducing apparatus using a jitter reduction method.