KR100494321B1 - Polycrystalline Silicon Film Formation Method of Semiconductor Device - Google Patents
Polycrystalline Silicon Film Formation Method of Semiconductor Device Download PDFInfo
- Publication number
- KR100494321B1 KR100494321B1 KR1019970081118A KR19970081118A KR100494321B1 KR 100494321 B1 KR100494321 B1 KR 100494321B1 KR 1019970081118 A KR1019970081118 A KR 1019970081118A KR 19970081118 A KR19970081118 A KR 19970081118A KR 100494321 B1 KR100494321 B1 KR 100494321B1
- Authority
- KR
- South Korea
- Prior art keywords
- silicon film
- film
- polycrystalline silicon
- gas
- amorphous silicon
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 title claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 20
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
- 239000001307 helium Substances 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 37
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
Abstract
본 발명은 반도체 소자의 다결정 실리콘막 형성 방법에 관한 것이다.The present invention relates to a method of forming a polycrystalline silicon film of a semiconductor device.
종래의 그레인 사이즈를 크게하여 그레인 바운더리 밀도를 감소시키는 SPG 어닐 방법은 결정 성장 뿐만 아니라 새로운 핵 입자도 함께 생성되므로 그레인 바운더리 밀도를 감소시키는데 문제가 있으며, 그레인 사이즈를 균일하게 증가시키는데 문제가 있으므로 TFT의 구동 특성 향상에 큰 제약이 되고 있다.Conventional SPG annealing method that reduces grain boundary density by increasing grain size has problems to reduce grain boundary density because new nucleus particles are generated as well as crystal growth, and there is a problem to increase grain size uniformly. There is a big limitation in improving the driving characteristics.
본 발명에서는 산화막 표면에 고진공 시스템에서 실리콘 시드를 형성하고 그 상부에 비정질 실리콘막을 증착하므로써 실리콘막이 실리콘 시드를 중심으로 실리콘 시드가 갖는 결정 방향과 같은 방향으로 증착되어 그레인 바운더리 밀도가 감소된 채널을 형성하고 후속 어닐링 공정을 실시하여 채널내의 전자들이 자유로이 이동할 수 있는 계면간의 공간이 최소화된 다결정 실리콘막이 형성되어 소자의 구동 특성을 향상시킬 수 있다.In the present invention, by forming a silicon seed on the surface of the oxide film in a high vacuum system and depositing an amorphous silicon film thereon, the silicon film is deposited in the same direction as the crystal direction of the silicon seed around the silicon seed to form a channel having a reduced grain boundary density. Subsequently, a subsequent annealing process may be performed to form a polycrystalline silicon film having minimal space between interfaces through which electrons in the channel can freely move, thereby improving driving characteristics of the device.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 계면간의 공간을 최소화하여 소자의 구동 특성을 향상시킬 수 있는 반도체 소자의 다결정 실리콘막 형성 방법에 관한 것이다.BACKGROUND OF THE
일반적으로 SRAM 소자의 박막 트랜지스터(Thin Film Transistor: 이하 TFT라 함) 소자의 채널, DRAM 소자의 게이트 전극, 전하저장(charge storage) 전극, 비휘발성 메모리 소자의 플로팅 게이트 전극으로는 CVD 방법으로 증착이 용이한 다결정 실리콘막이 사용되고 있다. 특히 SRAM 소자에 이용되고 있는 TFT 채널은 소자 구동시 전하들의 이동 통로 역할을 하므로 TFT의 특성을 판단하는 기본 요소인 채널 턴온시의 전류와 채널 턴오프시의 전류비, 즉 on/off 전류비가 클수록 좋다. 따라서, 이와 같은 채널은 다결정 실리콘막을 형성하여 가능한 한 그레인 바운더리 밀도(grain boundary density)를 줄이기 위해 그레인 사이즈를 크게 하여야 한다.In general, deposition of a channel of a thin film transistor (TFT) device of an SRAM device, a gate electrode of a DRAM device, a charge storage electrode, and a floating gate electrode of a nonvolatile memory device is performed by CVD. An easy polycrystalline silicon film is used. In particular, since the TFT channel used in the SRAM device acts as a movement path of charges when driving the device, the larger the ratio of current at channel turn-on and current at channel turn-off, that is, on / off current ratio, is a basic factor for determining TFT characteristics. good. Therefore, such a channel must have a large grain size in order to form a polycrystalline silicon film to reduce grain boundary density as much as possible.
종래에는 이러한 그레인 사이즈를 크게 하기 위해 다양한 기술들이 적용되어 왔으나, 가장 대표적인 방법을 설명하면 다음과 같다.Conventionally, various techniques have been applied to increase such grain size, but the most representative method will be described as follows.
SRAM 소자에서 다결정 실리콘막을 형성하는 방법은 소정의 공정을 거친 후 산화막이 형성된 실리콘 기판을 1Torr 이하의 압력과 550℃ 이하의 온도가 유지되는 반응로내에 로딩시킨다. 반응로내에 SiH4 또는 Si2H6 가스를 주입시켜 비정질 실리콘막을 형성시킨 후 650℃ 이상의 온도에서 4시간 이상 어닐링하므로써 비정질 실리콘막을 다결정 실리콘막으로 변형시킨다. 이러한 과정에서 그레인 사이즈를 크게하여 그레인 바운더리 밀도를 감소시키는 SPG 어닐 방법을 통해 TFT의 구동을 향상시킨다. 그 원리를 설명하면 다음과 같다. 보통 650℃ 이상의 온도에서 어닐링하는 동안 증착된 비정질 실리콘막내에 있는 다결정 실리콘 클러스터(cluster)로부터 핵이 형성된다. 막내의 그레인들은 생성된 핵을 중심으로 횡방향으로 증가하여 이웃하는 그레인과 맞닿을 때까지 성장한다. 따라서, 다결정 실리콘막의 그레인 사이즈는 막내의 핵의 농도에 의해 결정되는데, 650℃ 이상의 온도는 핵 입자가 생성될만한 에너지를 내포하고 있어 결정 성장 뿐만 아니라 새로운 핵 입자도 함께 생성되므로 그레인 바운더리 밀도를 감소시키는데 문제가 있다. 또한, 650℃ 이상의 온도에서 4시간 이상 어닐링하여 비정질 실리콘막을 다결정 실리콘막으로 형성하는 방법은 그레인 사이즈를 균일하게 증가시키는데 문제가 있으므로 TFT의 구동 특성 향상에 큰 제약이 되고 있다.In a method of forming a polycrystalline silicon film in an SRAM device, after a predetermined process, a silicon substrate on which an oxide film is formed is loaded into a reactor in which a pressure of 1 Torr or less and a temperature of 550 ° C. or less are maintained. SiH 4 or Si 2 H 6 gas is injected into the reactor to form an amorphous silicon film, and then the amorphous silicon film is transformed into a polycrystalline silicon film by annealing at a temperature of 650 ° C. or higher for 4 hours or more. In this process, the driving of the TFT is improved through the SPG annealing method in which the grain size is increased to reduce the grain boundary density. The principle is explained as follows. Nuclei are formed from polycrystalline silicon clusters in the amorphous silicon film deposited during annealing, usually at temperatures above 650 ° C. The grains within the membrane grow transversely around the nucleus, growing until they come into contact with neighboring grains. Therefore, the grain size of the polycrystalline silicon film is determined by the concentration of the nucleus in the film. The temperature of 650 ° C or higher contains energy enough to generate nuclear particles, so that not only crystal growth but also new nuclear particles are generated, which reduces grain boundary density. there is a problem. In addition, the method of forming an amorphous silicon film as a polycrystalline silicon film by annealing at a temperature of 650 DEG C or more for 4 hours or more has a problem of increasing the grain size uniformly, which is a great limitation in improving the driving characteristics of the TFT.
따라서, 본 발명은 계면간의 공간을 최소화하여 소자의 구동 특성을 향상시킬 수 있는 반도체 소자의 다결정 실리콘막 형성 방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method of forming a polycrystalline silicon film of a semiconductor device capable of minimizing the space between interfaces to improve driving characteristics of the device.
상술한 목적을 달성하기 위한 본 발명은 반도체 소자를 제조하기 위한 여러 요소가 형성된 반도체 기판 상부에 산화막을 형성한 후 상기 산화막 상부에 실리콘 시드를 형성하는 단계와, 상기 실리콘 시드를 포함한 전체 구조 상부에 실리콘 시드를 중심으로 실리콘 시드가 갖는 결정 방향과 같은 방향으로 비정질 실리콘막을 증착하여 그레인 바운더리 밀도가 감소된 채널을 형성하는 단계와, 어닐링 공정을 실시하여 상기 그레인 바운더리 밀도가 감소된 채널이 다결정 실리콘막으로 되는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is to form an oxide film on the semiconductor substrate formed with a number of elements for manufacturing a semiconductor device, and then forming a silicon seed on the oxide film, the entire structure including the silicon seed Depositing an amorphous silicon film around the silicon seed in the same direction as the crystal direction of the silicon seed to form a channel having a reduced grain boundary density, and performing an annealing process to form a channel having a reduced grain boundary density. Characterized in that it comprises a step that becomes.
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 다결정 실리콘막 형성 방법을 설명하기 위한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of a device for explaining a method of forming a polycrystalline silicon film of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 소자를 제조하기 위한 여러 요소가 형성된 반도체 기판(1) 상부에 산화막(2)을 형성한다. 산화막(2) 상부에 10-7 이하의 압력을 갖는 고진공 시스템(high vaccum system)을 이용하여 밀도(density)가 매우 낮은 실리콘 시드(3)을 형성한다.Referring to FIG. 1A, an
실리콘 시드(3)는 소스 가스로 SiH4 또는 Si2H6 가스등 실리콘을 함유하고 있는 가스를 10∼30SCCM으로 주입하고, 소스 가스 주입시 헬륨(He), 아르곤(Ar), 질소(N2) 등 화학 작용을 일으키지 않는 가스(inert gas)를 주입하여 10-5∼10-1 Torr의 압력과 550∼620℃의 온도에서 형성한다.The
도 1(b)는 실리콘 시드(3)가 형성된 전체 구조 상부에 CVD 방법으로 비정질 실리콘막(4)을 형성한 단면도이다.FIG. 1B is a cross-sectional view of the
비정질 실리콘막(4)을 증착하면 실리콘막이 실리콘 시드(3)를 중심으로 실리콘 시드(3)가 갖는 결정 방향과 같은 방향으로 증착되어 그레인 바운더리 밀도가 감소된 채널을 형성한다.When the
비정질 실리콘막(4)은 실리콘막이 비정질 상태를 잘 유지할 수 있는 0.5∼1Torr의 압력과 400∼550℃의 온도에서 SiH4 또는 Si2H6 가스를 50∼400SCCM 정도 주입하여 형성하며, 언도프트 및 도프트 비정질 실리콘막으로 형성한다.The
비정질 실리콘막(4)으로 도프트 비정질 실리콘막이 형성될 경우 도핑 소스로 PH3와 같은 인(P)을 함유하는 가스를 사용한다.When the doped amorphous silicon film is formed from the
도 1(c)는 어닐링 공정을 실시하여 전자들의 이동이 자유로운 다결정 실리콘막(5)이 형성된 단면도이다.FIG. 1C is a cross-sectional view of the
어닐링 공정은 챔버내를 600∼800℃의 온도와 0.5∼1Torr의 압력으로 유지하며, 질소 가스를 주입하여 1∼3시간 실시한다.In the annealing process, the chamber is maintained at a temperature of 600 to 800 ° C. and a pressure of 0.5 to 1 Torr, and nitrogen gas is injected for 1 to 3 hours.
상술한 바와 같이 본 발명에 의하면 산화막 표면에 고진공 시스템에서 실리콘 시드를 형성하고 그 상부에 비정질 실리콘막을 증착하므로써 실리콘막이 실리콘 시드를 중심으로 실리콘 시드가 갖는 결정 방향과 같은 방향으로 증착되어 그레인 바운더리 밀도가 감소된 채널을 형성하고 후속 어닐링 공정을 실시하여 채널내의 전자들이 자유로이 이동할 수 있는 계면간의 공간이 최소화된 다결정 실리콘막이 형성되어 소자의 구동 특성을 향상시킬 수 있다.As described above, according to the present invention, by forming a silicon seed on the surface of the oxide film in a high vacuum system and depositing an amorphous silicon film on the silicon film, the silicon film is deposited in the same direction as the crystal direction of the silicon seed with respect to the silicon seed so that grain boundary density is increased. By forming a reduced channel and performing a subsequent annealing process, a polycrystalline silicon film having a minimum space between interfaces through which electrons in the channel can freely move can be formed to improve driving characteristics of the device.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 다결정 실리콘막 형성 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of a device for explaining a method of forming a polycrystalline silicon film of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1 : 반도체 기판 2 : 산화막1
3 : 실리콘 시드 4 : 비정질 실리콘막3: silicon seed 4: amorphous silicon film
5 : 다결정 실리콘막5: polycrystalline silicon film
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970081118A KR100494321B1 (en) | 1997-12-31 | 1997-12-31 | Polycrystalline Silicon Film Formation Method of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970081118A KR100494321B1 (en) | 1997-12-31 | 1997-12-31 | Polycrystalline Silicon Film Formation Method of Semiconductor Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990060872A KR19990060872A (en) | 1999-07-26 |
| KR100494321B1 true KR100494321B1 (en) | 2005-08-31 |
Family
ID=37304341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970081118A KR100494321B1 (en) | 1997-12-31 | 1997-12-31 | Polycrystalline Silicon Film Formation Method of Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100494321B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101085626B1 (en) * | 2009-01-21 | 2011-11-22 | 주식회사 하이닉스반도체 | Method of formoing floating gate |
| KR20140085407A (en) * | 2010-04-27 | 2014-07-07 | 도쿄엘렉트론가부시키가이샤 | Amorphous silicon film formation method and amorphous silicon film formation apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01248511A (en) * | 1988-03-30 | 1989-10-04 | Nissan Motor Co Ltd | Formation of polycrystal film |
| JPH0360017A (en) * | 1989-07-27 | 1991-03-15 | Sanyo Electric Co Ltd | Manufacture of polycrystalline silicon film |
| JPH0370123A (en) * | 1989-08-10 | 1991-03-26 | Canon Inc | Formation of crystalline semiconductor film |
| KR100270620B1 (en) * | 1992-10-19 | 2000-12-01 | 윤종용 | Manufacturing method of poly crystal silicon layer |
-
1997
- 1997-12-31 KR KR1019970081118A patent/KR100494321B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01248511A (en) * | 1988-03-30 | 1989-10-04 | Nissan Motor Co Ltd | Formation of polycrystal film |
| JPH0360017A (en) * | 1989-07-27 | 1991-03-15 | Sanyo Electric Co Ltd | Manufacture of polycrystalline silicon film |
| JPH0370123A (en) * | 1989-08-10 | 1991-03-26 | Canon Inc | Formation of crystalline semiconductor film |
| KR100270620B1 (en) * | 1992-10-19 | 2000-12-01 | 윤종용 | Manufacturing method of poly crystal silicon layer |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101085626B1 (en) * | 2009-01-21 | 2011-11-22 | 주식회사 하이닉스반도체 | Method of formoing floating gate |
| US8324050B2 (en) | 2009-01-21 | 2012-12-04 | Hynix Semiconductor Inc. | Method of manufacturing flash memory device |
| KR20140085407A (en) * | 2010-04-27 | 2014-07-07 | 도쿄엘렉트론가부시키가이샤 | Amorphous silicon film formation method and amorphous silicon film formation apparatus |
| US9006021B2 (en) | 2010-04-27 | 2015-04-14 | Tokyo Electron Limited | Amorphous silicon film formation method and amorphous silicon film formation apparatus |
| KR101529171B1 (en) * | 2010-04-27 | 2015-06-16 | 도쿄엘렉트론가부시키가이샤 | Amorphous silicon film formation method and amorphous silicon film formation apparatus |
| KR101534637B1 (en) * | 2010-04-27 | 2015-07-09 | 도쿄엘렉트론가부시키가이샤 | Amorphous silicon film formation method and amorphous silicon film formation apparatus |
| KR101534634B1 (en) * | 2010-04-27 | 2015-07-09 | 도쿄엘렉트론가부시키가이샤 | Amorphous silicon film formation method and amorphous silicon film formation apparatus |
| KR101534638B1 (en) * | 2010-04-27 | 2015-07-24 | 도쿄엘렉트론가부시키가이샤 | Amorphous silicon film formation method and amorphous silicon film formation apparatus |
| US9123782B2 (en) | 2010-04-27 | 2015-09-01 | Tokyo Electron Limited | Amorphous silicon film formation method and amorphous silicon film formation apparatus |
| KR101615968B1 (en) | 2010-04-27 | 2016-04-28 | 도쿄엘렉트론가부시키가이샤 | Amorphous silicon film formation method and amorphous silicon film formation apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990060872A (en) | 1999-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| RU2199168C2 (en) | Method for producing integrated-circuit capacitor having improved characteristics of electrode and insulating layers (alternatives) and capacitors produced by this method | |
| JP3727449B2 (en) | Method for producing semiconductor nanocrystal | |
| US6391749B1 (en) | Selective epitaxial growth method in semiconductor device | |
| EP0608503B1 (en) | A semiconductor device and its manufacturing method | |
| KR100437296B1 (en) | Thin film transistor and its manufacturing method | |
| KR20050031455A (en) | Method of forming nanocrystals | |
| KR100299784B1 (en) | A method for forming a textured polysilicon layer, a substrate processing apparatus used to implement this method, and a semiconductor memory device | |
| CN1148799C (en) | Method for manufacturing capacitor using hemisphere grain silicon | |
| US5627086A (en) | Method of forming thin-film single crystal for semiconductor | |
| KR100769521B1 (en) | Poly silicon film producting method | |
| US7432141B2 (en) | Large-grain p-doped polysilicon films for use in thin film transistors | |
| KR100494321B1 (en) | Polycrystalline Silicon Film Formation Method of Semiconductor Device | |
| KR101012103B1 (en) | Method for depositing of ultra fine grain poly silicon thin film | |
| KR100255155B1 (en) | Semiconductor element multi-crystal silicon layer manufacturing method | |
| KR100255662B1 (en) | Method for manufacturing semiconductor device having polysilicon layer of hemisphere grain | |
| KR101110079B1 (en) | Method for depositing of ultra fine grain poly silicon thin film | |
| US5429961A (en) | Method for manufacturing a thin film transistor | |
| KR101012102B1 (en) | Method for depositing of ultra fine grain poly silicon thin film | |
| KR960013516B1 (en) | Thin film transistor & method of manufacturing thereof | |
| KR100208447B1 (en) | Forming method of channel polysilicon film in thin film transistor | |
| JPH09129626A (en) | Formation of thin film | |
| KR100338818B1 (en) | Method of forming capacitor of storage node in semiconductor device | |
| KR100316064B1 (en) | Method for manufacturing bottom electrod of capacitor in semiconductor device | |
| KR100472855B1 (en) | Polycrystalline silicon thin film manufacturing method of semiconductor device | |
| KR19990059057A (en) | Polysilicon Layer Formation Method Of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110429 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |