KR100492721B1 - Method and apparatus for designing intelligent system on a chip - Google Patents

Abstract

The present invention relates to a method and apparatus for designing an intelligent system on chip (SOC). When a specification of a chip to be designed is input by a designer, the present invention receives an analog IP and a digital IP to be applied to the design and compares it with the specification required by the designer. Unsatisfied IPs are modified and supplemented to derive new specifications. Apply the derived specifications to create the circuit, combine it with the circuit of the matching part, and verify. The number of input / output pins and power pins is calculated using the verified results, and the layout is extracted in consideration of the verified circuit and the calculated number of input / output pins and power pins. The extracted layout is produced as a mask. Therefore, even if you do not have enough prior knowledge of IP, SoC can be designed quickly and easily.

Description

Intelligent system-on-chip design method and apparatus {Method and apparatus for designing intelligent system on a chip}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the design of semiconductor integrated circuits, and more particularly, to an intelligent system-on-chip design method and apparatus for quickly and easily designing a system on a chip.

As semiconductor device manufacturing technology is developed and the size of integrated circuits is increased, system-on-chip (hereinafter, referred to as SoC) has recently been used. SoC is designed by using IP (Intellectual Property) as an essential material. SoC is designed as a mixture of analog and digital blocks because IP is largely divided into analog IP and digital IP.

1 is a flowchart illustrating a design process of a general system on chip (SoC).

The analog block and the digital block are separated according to the specification of the chip to be designed (step 1), and the circuits of the separated analog block and the digital block are verified respectively (steps 2 and 3). An integrated layout of the verified analog block and the digital block circuit is derived (step 4), and the derived integrated layout is verified (step 5). Finally, the integrated layout is produced as a mask (step 6).

Conventionally, according to the specifications of the chip to be designed, separate circuits of the analog block and the digital block are verified and the integrated layout is derived. After verifying the integrated layout, the final layout is produced as a mask.

The analog block has a higher dependency on the manufacturing process (Fab), while the digital block has a lower dependency on the manufacturing process (Fab), which is advantageous over the analog block in terms of design freedom. However, because masks used in SoC fabrication are made through layout, it is necessary to derive a suitable layout for the fabrication process (Fab), whether analog blocks or digital blocks.

The designer of the chip must acquire and verify design variables that characterize the device. This is possible only if you know the technical details of analog and digital blocks that you want to apply to the design, that is, analog IP and digital IP. However, if you have all the prior knowledge of these IPs, it will not be difficult to design, but those who do not have to spend a lot of time to acquire the knowledge, so it is relatively time-consuming to design. SoCs need a way to effectively reduce design time, especially as development time is determined by how short the design time is.

Therefore, the present invention is an intelligent system that can easily design a chip even if you do not have sufficient prior knowledge of IP, and can solve the above problems by automatically calculating the number of input and output pins and power pins used in the chip. Its purpose is to provide an on-chip design method and apparatus.

Intelligent system-on-chip design method according to the present invention for achieving the above object is the step of receiving the analog IP and digital IP to be applied to the specification and design of the chip to be designed, the specification of the chip to be designed and the analog IP and Comparing the specifications of the digital IP, and if the analog IP and digital IP specifications are satisfied with the specifications of the chip to be designed, the circuit of the matching part is outputted, and if not satisfied, the new IP is corrected and supplemented. Deriving a specification, generating a circuit by applying the derived specification, combining the circuit with the matching part, and verifying, calculating a number of input / output pins and power pins using the verified result; Extracting a layout by receiving the verified circuits and the number of input / output pins and power pins; and manufacturing a mask from the layout. It is characterized by including.

In addition, the intelligent system-on-chip design apparatus according to the present invention for achieving the above object is a specification input unit for receiving the specifications of the chip to be designed, an IP input unit for receiving analog IP and digital IP to be applied to the design, the chip to be designed By comparing the specifications of the analog IP and the digital IP and the specifications of the analog IP and digital IP meets the specifications of the chip to be designed, the circuit of the matching part is outputted, and if not satisfied, the unsatisfactory IP is corrected. And a circuit for applying a specification derived from the specification adaptation unit to generate a new specification by supplementing the circuit, generating a circuit, combining the circuit with the matching part, and verifying the result. The design unit for calculating the number, the layout from the verified circuit and the number of input and output pins and power pins are input And a mask fabrication unit configured to receive a layout from the layout extraction unit and produce a mask.

The specification adaptation unit may include a specification separation unit that separates the specifications input through the specification input unit into the specifications for the analog block and the digital block, an analog IP specification input unit for receiving the specification of the analog IP from the IP input unit, and the specification of the analog IP. Analog specification comparison unit for comparing the specifications for the analog block, Analog matching circuit separation unit for separating and outputting the circuit of the matched part in the transmission when the specifications of the analog IP and the specification for the analog block match, Analog mismatch specification establishment unit which derives new specification for mismatched part if specification of analog IP and specification of analog block do not match, digital IP specification input unit which receives digital IP specification from said IP input unit, said digital IP specifications and for the digital block Digital specification comparison unit for comparing the specifications, digital matching circuit separation unit for separating and outputting the circuit of the matching part in the transmission when the specifications of the digital IP and the specifications for the digital block match, the specifications of the digital IP and the If the specifications for the digital block does not match, it characterized in that it comprises a digital mismatch specification establishment for deriving a new specification for the mismatch.

The design unit inputs an analog matching circuit input unit which receives the analog circuit of the matching part from the specification adaptation unit, and a mismatched analog circuit which receives the specification derived from the specification adaptation unit and applies the derived specification to generate an analog circuit. A generating unit, an analog circuit unit for coupling a circuit output from the analog matching circuit input unit and a circuit output from the mismatching analog circuit generating unit, a digital matching circuit input unit receiving a digital circuit of the matching part from the specification conforming unit, A discrepancy digital circuit generation unit which receives the derived specification from a specification adaptation unit and applies the derived specification to generate a digital circuit; a circuit output from the digital coincidence circuit input unit and a circuit output from the mismatch digital circuit generation unit; texture A digital circuit unit for verifying, an analog verify unit for verifying an analog circuit output from the analog circuit unit, a digital verify unit for verifying a digital circuit output from the digital circuit unit, and a circuit output from the analog verify unit and the digital verify unit An analog-digital integrated verification unit, an input / output pin calculation unit for calculating the number of input / output pins using the verification result output from the analog-digital integrated verification unit, and the power using the verification result output from the analog-digital integrated verification unit Power pin calculation unit for calculating the number of pins, characterized in that it comprises a power pin calculation algorithm storage unit for storing the algorithm for calculating the number of power pins.

The layout extracting unit receives an analog circuit verified from the design unit and layouts the analog layout unit, a digital layout unit receiving and laying out the digital circuit verified from the design unit, a layout output from the analog layout unit and the digital layout unit and the And an integrated layout unit configured to receive the number of input / output pins and power pins calculated from the design unit, and extract the integrated layout in consideration of the input and output pins.

Also, a specification Fab library unit providing a specification and manufacturing process (Fab) library to the specification adaptation unit, design unit, and layout extraction unit, and a specification comparison result output unit outputting information on specifications from the specification adaptation unit and design unit to the outside. It further comprises.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. It doesn't happen.

2 is a block diagram illustrating an apparatus for designing a system on chip (SoC) according to the present invention.

When the designer determines the specification of the chip to be designed and inputs it to the specification input unit 10, the IP input unit 11 receives an IP to be applied to the design. At this time, analog IP and digital IP are input as design file.

The specification adaptation unit 12 compares the specifications of the chip to be designed with the specifications of analog IP and digital IP. When IPs satisfying the specifications required by the designer are input through the IP input unit 11, the circuit of the matching part is sent to the SoC design unit 13 for verification, and when IPs that do not satisfy the required specifications are input, they are not satisfied. New specifications are derived by modifying and supplementing IP. In most cases, since the IP that satisfies the specification is not directly obtained, the specification adaptation unit 12 modifies and supplements the obtained IP to derive a new specification.

The SoC design unit 13 generates a circuit by applying the specification derived from the specification adaptation unit 12, and then combines and verifies the circuit of the matching part, and calculates the number of input / output pins and power pins using the verification result. .

The layout extractor 14 receives the verified circuit from the SoC design unit 13 and the number of input / output pins and power pins to extract the layout, and the mask fabrication unit 15 provides the layout extracted from the layout extractor 14. Take a mask and make it.

FIG. 3 is a detailed block diagram of the specification adaptation unit 12 illustrated in FIG. 2, and the specification separation unit 102 converts the specifications input through the specification input unit 10 of FIG. 2 into the specifications for the analog block and the digital block. Separated and sent to the analog specification comparison unit 100 and the digital specification comparison unit 104.

The analog specification comparison unit 100 compares the specifications of the analog IP input from the analog IP specification input unit 101 connected to the IP input unit 11 of FIG. 2 with the specifications of the analog blocks separated by the specification separation unit 102. . At this time, if the specification of the input analog IP and the specification of the separated analog block match each other, the analog matching circuit separating unit 105 separates the circuit of the matching part in the transmission and sends it to the SoC design unit 13, If the specifications of the analog IP and the specifications for the separated analog block do not match with each other, the mismatch specification establishment unit 106 derives a new specification for the inconsistency. In other words, after confirming the part where the specification of the analog IP and the specification of the separated analog block do not match, modifying and supplementing the IP to derive a new specification. When comparing the specifications with each other, the analog specification comparison unit 100 refers to the specification Fab library unit 16 of FIG. At this time, the information about the specifications that do not match the specifications that match each other is output in a text form through the specification comparison result output unit 107, which is output to the outside through the comparison verification result output unit 17 of FIG.

On the other hand, the digital specification comparison unit 104 is a specification of the digital IP input from the digital IP specification input unit 103 connected to the IP input unit 11 of FIG. Compare. At this time, if the specification of the input digital IP and the specification of the separated digital block match each other, the digital matching circuit separating unit 108 separates the circuit of the matching part in the transmission and sends it to the SoC design unit 13, If the specifications of the digital IP and the specifications for the separated digital blocks do not coincide with each other, the digital mismatch specification establishment unit 109 derives a new specification for the inconsistency. In other words, after confirming the part where the specification of the digital IP and the specification of the separated digital block does not match, the new specification is derived by modifying and supplementing the IP. When comparing the specifications of each other, the digital specification comparison unit 104 refers to the specification Fab library unit 16 of FIG. At this time, the information about the specifications that do not match the specifications that match each other is output in a text form through the specification comparison result output unit 107, which is output to the outside through the comparison verification result output unit 17 of FIG.

FIG. 4 is a detailed block diagram of the SoC design unit 13 shown in FIG. 2, in which analog circuits of matching parts separated from the analog matching circuit separating unit 105 of FIG. 3 are input to the analog matching circuit input unit 200. . The new specification derived for the mismatched portion of the analog mismatch specification establishing unit 106 of FIG. 3 is input to the mismatch analog circuit generation unit 201. The mismatched analog circuit generator 201 generates an analog circuit by applying the derived specifications and inputs the analog circuit to the analog circuit unit 204. The analog circuit unit 204 combines the circuit input from the analog coincidence circuit input unit 200 and the circuit input from the mismatched analog circuit generation unit 201 so that the analog layout unit of the analog verification unit 206 and the layout extraction unit 14 is provided. Send to 300 each. The analog circuit portion 204 then references the used Fab library portion 16 of FIG. 2 to apply the library of the fabrication process Fab.

On the other hand, the digital circuit of the matching part separated from the digital matching circuit separating unit 108 of FIG. 3 is input to the digital matching circuit input unit 202. The new specification derived for the mismatched part in the digital mismatch specification establishing unit 109 of FIG. 3 is input to the mismatch digital circuit generation unit 203. The discrepancy digital circuit generator 203 generates a digital circuit by applying the derived specifications and inputs the digital circuit to the digital circuit unit 205. The digital circuit unit 205 combines the circuit input from the digital coincidence circuit input unit 202 and the circuit input from the mismatched digital circuit generator 203 to form the digital layout unit of the digital verifier 207 and the layout extractor 14. Send each to 301. The digital circuit section 205 then references the used Fab library section 16 of FIG. 2 to apply the library of the fabrication process Fab.

The analog verifying unit 206 and the digital verifying unit 207 verify the circuits output from the analog circuit unit 204 and the digital circuit unit 205, respectively, and then send them to the analog-digital integrated verification unit 208. The analog-digital integrated verification unit 208 performs the integrated verification and sends the verification result to the input / output pin calculation unit 209 and the power pin calculation unit 210.

The input / output pin calculation unit 209 calculates the number of input / output pins for all the chips and sends them to the integrated layout unit 302, and the power pin calculation unit 210 calculates the power pins with reference to the used Fab library unit 16. The result is then sent to the integrated layout unit 302. At this time, the algorithm for calculating the number of power pins is stored in advance in the power pin calculation algorithm storage unit 211, an algorithm included in the used Fab library unit 16 or a separate algorithm may be used.

FIG. 5 is a detailed block diagram of the layout extracting unit illustrated in FIG. 2, wherein the analog layout unit 300 is a result circuit input from the analog circuit unit 204 of FIG. 4, that is, the analog matching circuit input unit 200 of FIG. 4. Inconsistent with the input circuit Lay out a circuit combining the circuit input from the analog circuit generation unit 201, the digital layout unit 301 is a result circuit input from the digital circuit unit 205 of FIG. The circuit in which the circuit input from the circuit input unit 202 and the circuit input from the mismatched digital circuit generation unit 203 are combined is laid out.

The integrated layout unit 302 may include layouts output from the analog layout unit 300 and the digital layout unit 301, input / output pins calculated by the input / output pin calculation unit 209 and the power pin calculation unit 210 of FIG. 4. The number of power pins is input and the integrated layout is taken into consideration. An integrated layout in which input and output pins and power pins are properly arranged is fabricated with a mask 303.

6 is a flowchart illustrating a method for designing an intelligent system on chip according to the present invention, and illustrates a design process performed through the intelligent system on chip design apparatus according to the present invention.

The specification of the chip to be designed is input from the designer (step 400), and the IP to be applied to the design is input (step 401). At this time, IP is composed of analog IP and digital IP, and it is input in the form of design file.

The specifications of the chip to be designed are compared with the specifications of the analog IP and the digital IP (step 402). If the specifications of the analog IP and digital IP are satisfied with the specifications of the chip to be designed, the circuit of the matching part is output (step 403), and if not satisfied, a new specification is derived by correcting and supplementing the unsatisfied IP (step 403). 404).

A circuit is generated by applying the derived specifications (step 405), combined with the circuit of the matching part and verified (step 406), and the number of input / output pins and power pins is calculated using the verified result (step 407).

The layout is extracted by receiving the verified circuit, the number of the input / output pins and the power pins (step 408), and a mask is manufactured from the layout (step 409).

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various forms may be made by those skilled in the art within the scope of the present invention. Modifications are possible.

In the present invention, when the specification of the chip to be designed by the designer is input, the analog IP and the digital IP to be applied to the design are input and compared with the specification required by the designer, but the unsatisfactory IP is modified and supplemented to derive a new specification. Apply the derived specifications to create the circuit, combine it with the circuit of the matching part, and verify. The number of input / output pins and power pins is calculated using the verified results, and the layout is extracted in consideration of the verified circuit and the calculated number of input / output pins and power pins. The extracted layout is produced as a mask.

As described above, the present invention extracts the circuits of analog blocks and digital blocks by analyzing the IP even without having sufficient prior knowledge of the IP, while automatically calculating the number of input / output pins and power pins to derive an integrated layout. Therefore, the design of the SoC is quick and easy, and the development of the SoC can be successfully achieved.

1 is a flowchart illustrating a design process of a general system on chip (SoC).

2 is a block diagram for explaining a system on a chip (SoC) design apparatus according to the present invention.

3 is a detailed block diagram of a specification adaptation unit illustrated in FIG. 2.

4 is a detailed block diagram of a design unit shown in FIG. 2;

5 is a detailed block diagram of the layout extraction unit illustrated in FIG. 2.

6 is a flowchart illustrating a system on chip (SoC) design method according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: Specification input unit 11: IP input unit

12: Specification compliance section 13: SoC design section

14: layout extraction unit 15: mask production unit

16: Fab library section 17: Comparative verification result output section

100: analog specification comparison unit 101: analog IP specification input unit

102: specification separation unit 103: digital IP specification input unit

104: digital specification comparison unit 105: analog matching circuit separation unit

106: analog mismatch specification part 107: specification comparison result output unit

108: digital coincidence circuit separating unit 109: digital mismatch specification

200: analog match circuit input unit 201: mismatch analog circuit generation unit

202: digital coincidence circuit input unit 203: mismatch digital circuit generator

204: analog circuit portion 205: digital circuit portion

206: analog verification unit 207: digital verification unit

208: analog-digital integrated verification unit 209: input and output pin calculation

210: power pin calculation unit 211: power pin calculation algorithm storage unit

300: analog layout section 301: digital layout section

302: Integrated layout unit 303: Mask

Claims (9)

a) receiving analog IP and digital IP to be applied to the specification and design of the chip to be designed, b) comparing the specifications of the chip to be designed with the specifications of the analog IP and digital IP; c) outputting a circuit of a corresponding part when the specifications of the analog IP and the digital IP satisfy the specification of the chip to be designed, and if not satisfied, correcting and supplementing the unsatisfied IP to derive a new specification; d) generating a circuit by applying the derived specifications, combining and verifying the circuit with the matching part, and calculating the number of input / output pins and power pins using the verified results; e) extracting a layout by receiving the verified circuit and the number of input / output pins and power pins; f) fabricating a mask with the layout. The method of claim 1, wherein the analog IP and the digital IP are input in the form of a design file. Specification input unit for receiving the specification of the chip to be designed, IP input unit that receives analog IP and digital IP to apply to design, When the specifications of the chip to be designed and the specifications of the analog IP and the digital IP are compared and the specifications of the analog IP and the digital IP are satisfied, the circuit of the matching part is outputted. Specification adaptation department that revises and supplements IP Design unit for generating a circuit by applying the specifications derived from the specification adaptation unit, verify after combining with the circuit of the matching portion, and calculates the number of input and output pins and power pins using the verification result, A layout extracting unit extracting a layout by receiving the verified circuit and the number of input / output pins and power pins from the design unit; And a mask fabrication unit receiving the layout from the layout extraction unit and manufacturing a mask. The intelligent system on chip design apparatus according to claim 3, wherein the analog IP and the digital IP are input in the form of a design file. The apparatus of claim 3, wherein the specification adaptation unit comprises: a specification separation unit configured to separate the specifications input through the specification input unit into specifications for analog blocks and digital blocks; Analog IP specification input unit for receiving the specification of analog IP from the IP input unit, Analog specification comparison unit for comparing the specification of the analog IP and the specification for the analog block, Analog matching circuit separation unit for separating and outputting the circuit of the matching part in the transmission when the specification of the analog IP and the specification for the analog block, An analog mismatch specification establishment unit which derives a new specification for an inconsistent part if the specification of the analog IP and the specification of the analog block do not match; Digital IP specification input unit for receiving the specification of the digital IP from the IP input unit, Digital specification comparison unit for comparing the specification of the digital IP and the specification for the digital block, A digital coincidence circuit separating unit for separating and outputting a circuit of a matched portion in the transmission when the specification of the digital IP and the specification of the digital block match; And a digital inconsistency specification establishment unit that derives a new specification for a mismatched part if the specification of the digital IP does not match the specification for the digital block. The analog matching circuit input unit of claim 3, wherein the design unit receives an analog circuit of the matching portion from the specification adaptation unit. An inconsistent analog circuit generation unit which receives the derived specification from the specification adaptation unit and applies the derived specification to generate an analog circuit; An analog circuit unit for coupling a circuit output from the analog match circuit input unit and a circuit output from the mismatch analog circuit generation unit; A digital matching circuit input unit for receiving a digital circuit of the matching portion from the specification adapting unit, Inconsistent digital circuit generation unit for receiving the derived specifications from the specification adaptor and applying the derived specifications to generate a digital circuit, A digital circuit unit for coupling a circuit output from the digital match circuit input unit and a circuit output from the mismatch digital circuit generation unit; An analog verification unit for verifying an analog circuit output from the analog circuit unit; A digital verification unit which verifies a digital circuit output from the digital circuit unit, An analog-digital integrated verification unit for verifying a circuit output from the analog verification unit and the digital verification unit; An input / output pin calculation unit for calculating the number of input / output pins using the verification result output from the analog-digital integrated verification unit, And a power pin calculation unit for calculating the number of power pins using the verification result output from the analog-digital integrated verification unit. The apparatus of claim 6, further comprising a power pin calculation algorithm storage unit in which an algorithm for calculating the number of power pins is stored. The analog layout unit of claim 3, wherein the layout extractor is configured to receive and layout an analog circuit verified from the design unit; A digital layout unit configured to receive and layout the verified digital circuit from the design unit, Intelligent system on chip, characterized in that it comprises an integrated layout unit for receiving the layout output from the analog layout unit and the digital layout unit and the number of input and output pins and power pins calculated from the design unit, and extracts the integrated layout in consideration of these Design device. The apparatus of claim 3, wherein the specification Fab library unit provides a specification and fabrication process (Fab) library to the specification adaptation unit, the design unit, and the layout extraction unit. Intelligent system-on-chip design apparatus further comprises a specification comparison result output unit for outputting information on the specification from the specification adaptation unit and the design unit to the outside.