KR100491113B1 - Asymmetric digital subscriber line system using gps signal, and clock and dcs signal supply device of system thereof - Google Patents

Abstract

The present invention discloses a clock and DCS signal supply apparatus of an ADSL system using a GPS signal. The asymmetric digital subscriber line (ADSL) system using the disclosed GPS signal of the present invention extracts a clock from a GPS signal received through a GPS antenna and generates asymmetric digital subscriber line (ADSL) data using the extracted clock. It provides an Annex-C service for outputting the ADSL data.

Therefore, the clock signal (1pps) received from the GPS receiver is used to confirm the phase error with the DCS signal in advance, and reflects the clock signal generated in synchronization with the clock signal to the output frequency signal (400 Hz). By providing the system, the Annex-C service can be operated normally even when DCS signal is not provided.

Description

ASSYMMETRIC DIGITAL SUBSCRIBER LINE SYSTEM USING GPS SIGNAL, AND CLOCK AND DCS SIGNAL SUPPLY DEVICE OF SYSTEM THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asymmetric digital subscriber line (ADSL) system and a clock and digital clock supply (DCS) signal supply apparatus thereof, and in particular, a global positioning system (GPS). The present invention relates to an ADSL system using a GPS signal capable of providing an Annex-C service using a signal, and a clock and a DCS signal supply device of the system.

In general, the ADSL enables downlink (telephone to subscriber) transmission and slow uplink (subscriber to telephone) transmission of about 1.5 Mbps to 8 Mbps using a conventional telephone twisted pair cable. As a transmission technology, it was developed by Bellcore in the United States. This ADSL consists of a 1.5 Mbps downlink channel at a much higher frequency than the 4 KHz voice band, a 16 Kbps upstream channel between the band and the voice band, and frequency division that allows analog voice to pass through the lowest band. I choose the way.

This ADSL has a transmission distance long enough to allow a relay connection from the telephone or remote station to the subscriber by using a conventional telephone spiral pair cable, and the installation and supply of a service device is as simple as conventional telephone service (POTS). . In addition, by placing the video and control signal band on the upper frequency band of the existing telephone signal it is possible to transmit several signals simultaneously using the telephone line without overlapping the frequency band.

In the ADSL, a video server that stores compressed video signals such as movies, videos, and games is connected to an ASL Transceiver Unit (ATU-C), which is a transmission device of a mother station, together with an existing telephone switch. Inside the home, an ASL Transceiver Unit-Remote (ATU-R), which is a subscriber-side transmission device, is connected. The ATU-R is a video and audio signal decoder called a set-top box that connects directly to a personal computer (PC), ATM or LAN console with a conventional telephone, or to a TV or PC. Is connected to. Plain Ordinary Telephone Service (POTS) signals are then distributed to standard telephone wiring in the subscriber's home.

On the other hand, for Annex-C service that provides ADSL data using ISDN (Integrated Services Digital Network) line, 400Hz phase synchronization is used to prevent crosstalk between ISDN lines. Service is essential.

FIG. 1 is a schematic diagram of an ADSL system providing a conventional Annex-C service, and includes a first and a second ADSL system (1) for outputting ADSL data by respectively inputting a DCS signal having 400 Hz phase information. (2) is shown.

As shown in FIG. 1, the first and second ADSL systems 1 and 2, in which DCS signals with 400 Hz phase information are provided, are provided with an Annex-C service providing the ADSL data. It is possible. However, ADSL system (not shown) located where DCS signal with 400Hz phase information is not provided is not available for Annex-C service.

As such, in the conventional ADSL system, there was a place where a DCS signal having 400 Hz phase information was not provided depending on the location where the device was installed. Therefore, there is a problem in that the clock and the DCS signal supply device of the ADSL system cannot be installed because the DCS signal is not provided in this region.

The present invention has been made to solve the above problems, and an object of the present invention is to normally operate the Annex-C service that provides ADSL data even where a DCS signal with 400 Hz phase information is not received. To provide an ADSL system using a GPS signal and a clock and DCS signal supply of the system.

An asymmetric digital subscriber line (ADSL) system using a GPS signal of the present invention for achieving the above object,

The Annex-C service extracts a clock from a GPS signal received through a GPS antenna and generates asymmetric digital subscriber line (ADSL) data using the extracted clock, thereby outputting the ADSL data. It is characterized by providing.

Here, the ADSL system is installed in a place where a digital clock supply (DCS) signal is not received.

And, the clock is characterized in that it has 400Hz phase information.

Clock and DCS signal supply apparatus of the ADSL system using a GPS signal according to the present invention for achieving the above object,

A GPS receiver receiving a GPS signal via a GPS antenna;

A reference clock monitoring unit for receiving and monitoring a first reference clock from the GPS receiver;

A first synchronization clock generation unit receiving the first reference clock from the reference clock monitoring unit and generating a first synchronization clock synchronized with the first reference clock;

A timing generator generating second and third reference clocks for correcting a phase difference by using the first sync clock received from the first sync clock generator;

A second sync clock generator configured to receive the second reference clock from the timing generator and generate a second sync clock synchronized with the second reference clock;

A DCS clock generation unit configured to receive a second reference clock from the second synchronization clock generator and the third reference clock from the timing generator to generate a DCS signal; And

And an AMI signal matching unit which receives the DCS signal from the DCS clock generator and converts the DCS signal into an Alternate Mark Inversion (AMI) signal.

The first synchronous clock generator may include: a phase error detector configured to compare the phase difference between the first reference signal and the first comparison signal and output the digital data; A central processing unit (CPU) for lowpass filtering the signal received from the phase error detector by programming; A D / A converter converting the digital signal received from the CPU to an analog signal and outputting the analog signal; A voltage controlled oscillator for generating a self oscillation frequency according to the voltage of the analog signal received from the D / A converter; And a divider for generating the first synchronous clock and the first comparison signal by dividing the oscillation frequency received from the voltage controlled oscillator at a predetermined frequency.

The second synchronous clock generator may include: a phase error detector configured to compare a phase difference between the first synchronous clock and the second comparison signal and output a voltage; A low pass filter (LPF) for low pass filtering the signal received from the phase error detector; A voltage controlled oscillator for generating a self oscillation frequency according to a voltage of a signal received from the low pass filter (LPF); And a divider for generating the second synchronization clock and the second comparison signal by dividing the oscillation frequency received from the voltage controlled oscillator at a predetermined frequency.

In addition, the first reference clock is a 1pps signal, the first synchronous clock is a 400Hz signal, the first comparison signal is a 1Hz signal, the second reference clock is a 400Hz signal, the third reference clock is an 8KHz signal And a 400 Hz signal, the second synchronous clock is a 64 KHz signal, and the DCS signal is a 64 KHz + 8 KHz + 400 Hz signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic diagram of an ADSL system using a GPS signal according to the present invention.

In the ADSL system using the GPS signal, as shown in FIG. 2, an ADSL system is provided by inputting a DCS (Digital Clock Supply) signal having 400 Hz phase information and outputting ADSL data to provide an Annex-C service. 1 ADSL system 100 and the DCS signal having the 400Hz phase information is installed in a place where the reception is not received, by extracting the 400Hz clock from the GPS signal received through the GPS antenna to output ADSL data (Annex-C) A second ADSL system 200 that provides a service.

As shown in FIG. 2, the first ADSL system 100 provided with a DCS signal having 400 Hz phase information is capable of an Annex-C service providing the ADSL data. However, the Annex-C service is not possible in the second ADSL system 200 where the DCS signal having the 400 Hz phase information is not provided. Therefore, the present invention provides an Annex-C by installing the second ADSL system 200 for receiving a GPS signal having 400 Hz phase information through a GPS antenna where a DCS signal having 400 Hz phase information is not provided. -C) Implemented to provide service.

The second ADSL system 200 provides an Annex-C service by extracting a 400 Hz clock from the GPS signal received through the GPS antenna and outputting ADSL data.

3 is a block diagram of a clock and DCS signal supply apparatus of an ADSL system using a GPS signal according to the present invention.

Clock and DCS signal supply apparatus of the ADSL system using the GPS signal, as shown in Figure 1, GPS receiver 10, reference clock monitoring unit 20, phase error detector 31 and the central processing unit (CPU) A first synchronous clock generator 30 comprising a D / A converter 33, a voltage controlled oscillator 34, and a divider 35, a timing generator 40, a phase error detector 51, The second synchronous clock generator 50, the DCS clock generator 60, and the AMI signal matcher 70 including the low pass filter (LPF) 52, the voltage controlled oscillator 53, and the divider 54 are connected. It is configured to include.

Here, the GPS receiver 10 receives a GPS signal through a GPS antenna (not shown) and secures 1 ppm from the input GPS signal.

In addition, the reference clock monitoring unit 20 detects a reception state of the GPS signal and a failure of 1 pps synchronized with the GPS and automatically restores the failure when the failure is released. The reference clock monitoring unit 20 detects the first reference signal A from the GPS signal and outputs the first reference signal A to the phase error detector 31. Here, the first reference signal A is a 1pps signal.

The first sync clock generator 30 receives the first reference signal A from the reference clock monitor 20 to receive a first sync clock G synchronized with the first reference signal A. FIG. Occurs. Here, the first synchronous clock G is 400 Hz.

As shown in FIG. 1, the first synchronous clock generator 30 includes a phase error detector 31, a central processing unit (CPU) 32, a D / A converter 33, and a voltage controlled oscillator 34. And a divider 35.

Here, the phase error detector 31 compares the phase difference between the first reference signal A and the first comparison signal B and outputs the compared signal C as digital data.

The CPU 32 outputs a signal D obtained by low-pass filtering the signal C received from the phase error detector 31 by internal programming.

The D / A converter 33 converts the signal (digital signal) D received from the CPU 32 into an analog signal E and outputs the analog signal.

The voltage controlled oscillator 34 generates its own oscillation frequency F according to the voltage of the analog signal E received from the D / A converter 33. Here, the oscillation frequency (F) is 38.88MHz.

The divider 35 divides the oscillation frequency F received from the voltage controlled oscillator 34 at a predetermined frequency to generate the first synchronous clock G, and divides the first synchronous clock G. Thus, the first comparison signal B is generated. Here, the first synchronous clock G is 400 Hz and the first comparison signal B is 1 Hz.

Next, the timing generator 40 may correct the phase difference between the GPS 1pps signal and the 400Hz signal using the first sync clock 400Hz (G) received from the first sync clock generator 30. The second reference clock I and the third reference clock H are generated. Here, the second reference clock (I) is 400Hz, the third reference clock (H) is 8KHz, 400Hz.

Next, the second synchronous clock generator 50 receives the second reference clock I from the timing generator 40 and synchronizes the second synchronous clock with the second reference clock I. L) is generated and output to the DCS clock generator 60. Here, the second synchronous clock L is a 64KHz signal.

As shown in FIG. 1, the second synchronous clock generator 50 includes a phase error detector 51, a low pass filter (LPF) 52, a voltage controlled oscillator 53, and a divider 54. do.

Here, the phase error detector 51 compares the phase difference between the second reference signal I and the second comparison signal M and outputs the compared signal J as digital data.

The low pass filter (LPF) 52 outputs a signal K obtained by low pass filtering the signal J received from the phase error detector 51. In this case, the low pass filter (LPF) 52 serves to adjust the strength of the second synchronous clock generator 50.

The voltage controlled oscillator 53 divides the oscillation frequency oscillated according to the voltage of the analog signal K received from the low pass filter (LPF) 52, that is, the second synchronous clock (L). And outputs to the DCS clock generator 60. Here, the second synchronous clock L is a 64KHz signal.

The divider 54 divides the oscillation frequency L received from the voltage controlled oscillator 53 at a predetermined frequency to generate the second comparison signal M.

The second synchronous clock generator 50 generates an oscillation frequency, that is, the second synchronous clock L according to the input signal K of the voltage controlled oscillator 53. The divider 54 inputs the second synchronization clock L to output a second comparison signal M divided by 1 / N. The phase error detector 51 outputs the same signal as the input signal K of the voltage controlled oscillator 53 when the phase of the second reference signal I and the second comparison signal M coincide with each other. By outputting, the phase difference between the two signals is compensated.

Next, the DCS clock generator 60 receives the second reference clock H from the second synchronization clock L and the timing generator 40 from the second synchronization clock generator 50. To generate the DCS signal (N). Here, the second synchronous clock is a 64KHz signal, the third reference clock is an 8KHz signal and a 400Hz signal, and the DCS signal is a 64KHz + 8KHz + 400Hz signal.

Finally, the AMI signal matching unit 70 receives the DCS signal N from the DCS clock generator 60 and converts the DCS signal into an AMI (Alternate Mark Inversion) signal.

Therefore, the present invention generates a 400Hz signal synchronized with the 1pps signal using the 1pps signal obtained from the GPS receiver and provides the system to the system, and the ADSL system can be operated so that the Annex-C service can operate normally. By synchronizing to a 400Hz signal, the ADSL system can provide Annex-C services.

Preferred embodiments of the present invention as described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, modifications, additions, etc. within the spirit and scope of the present invention, such modifications and the like belong to the following claims You will have to look.

As described above, according to the ADSL system using the GPS signal according to the present invention, and the clock and DCS signal supply apparatus of the system, the phase error with the DCS signal is preliminarily used by using the clock signal (1pps) received from the GPS receiver. Check and measure this measurement error to the ADSL system by reflecting the clock signal generated in synchronization with the clock signal to the output frequency signal (400Hz), so that the Annex-C service is normally operated even if the DCS signal is not provided. It is effective to operate.

1 is a schematic diagram of an ADSL system providing a conventional Annex-C service

2 is a schematic diagram of an ADSL system using a GPS signal according to the present invention

3 is a block diagram of a clock and DCS signal supply apparatus of an ADSL system using a GPS signal according to the present invention

<Explanation of symbols for the main parts of the drawings>

10: GPS receiver 20: reference clock monitoring unit

30: first synchronous clock generator 31: phase error detector

32: CPU (CPU) 33: D / A converter

34: voltage controlled oscillator (VCXO) 35: divider

40: timing generator 50: second sync clock generator

51: phase error detector 52: low pass filter (LPF)

53: voltage controlled oscillator (VCXO) 54: divider

60: DCS clock generator 70: AMI signal matching unit

100: first asymmetric digital subscriber line (ADSL) system

200: second asymmetric digital subscriber line (ADSL) system

Claims (7)

delete delete delete A GPS receiver receiving a GPS signal via a GPS antenna; A reference clock monitoring unit for receiving and monitoring a first reference clock from the GPS receiver; A first synchronization clock generation unit receiving the first reference clock from the reference clock monitoring unit and generating a first synchronization clock synchronized with the first reference clock; A timing generator generating second and third reference clocks for correcting a phase difference by using the first sync clock received from the first sync clock generator; A second sync clock generator configured to receive the second reference clock from the timing generator and generate a second sync clock synchronized with the second reference clock; A DCS clock generation unit configured to receive a second reference clock from the second synchronization clock generator and the third reference clock from the timing generator to generate a DCS signal; And A clock and DCS signal of an asymmetric digital subscriber line system using a GPS signal, comprising: an AMI signal matching unit receiving the DCS signal from the DCS clock generator and converting the signal into an AMI (Alternate Mark Inversion) signal Feeding device. The method of claim 4, wherein the first sync clock generator comprises: A phase error detector for comparing the phase difference between the first reference signal and the first comparison signal and outputting the digital data; A central processing unit (CPU) for lowpass filtering the signal received from the phase error detector by programming; A D / A converter converting the digital signal received from the CPU to an analog signal and outputting the analog signal; A voltage controlled oscillator for generating a self oscillation frequency according to the voltage of the analog signal received from the D / A converter; And And a divider for generating the first synchronization clock and the first comparison signal by dividing the oscillation frequency received from the voltage controlled oscillator to a predetermined frequency. And DCS signal supply. The method of claim 4, wherein the second sync clock generating unit: A phase error detector for comparing the phase difference between the first synchronization clock and the second comparison signal and outputting the voltage as a voltage; A low pass filter (LPF) for low pass filtering the signal received from the phase error detector; A voltage controlled oscillator for generating a self oscillation frequency according to a voltage of a signal received from the low pass filter (LPF); And And a divider for generating the second synchronous clock and the second comparison signal by dividing the oscillation frequency received from the voltage controlled oscillator to a predetermined frequency. And DCS signal supply. The method according to any one of claims 4 to 6, The first reference clock is a 1pps signal, The first sync clock is a 400 Hz signal, The first comparison signal is a 1 Hz signal, The second reference clock is a 400 Hz signal, The third reference clock is an 8KHz signal and a 400Hz signal, The second sync clock is a 64KHz signal, The DCS signal is a 64KHz + 8KHz + 400Hz signal, characterized in that the clock and DCS signal supply apparatus of an asymmetric digital subscriber line system using a GPS signal.