KR100490666B1 - Memory device having a redundant memory block - Google Patents

Abstract

The present invention relates to a memory device having redundant memory blocks. The memory device includes a main memory block, a redundant memory block, a first decoder, a second decoder, and an address control circuit. The address control circuit is used to set an address corresponding to a defective byte among memory bytes. When the external address signal matches the set address by the address control circuit, the address is transferred to the redundant memory block so that a defective byte of memory cells can be replaced with an extra byte of memory cells. Therefore, the production yield increases.

Description

MEMORY DEVICE HAVING A REDUNDANT MEMORY BLOCK}

The present invention relates to a memory device, and more particularly to a memory device having a redundant memory block.

FIG. 1A is a circuit diagram illustrating a circuit configuration of a conventional memory device, and FIG. 1B is a diagram illustrating an address and data of the memory device shown in FIG. 1A.

The memory device 100 shown in FIGS. 1A-1B has a storage capacity of 1K × 8 bits. In this case, ten address lines A0 to A9 for addressing the entire main memory block MMB by the row decoder 11 and the column decoder 112. ) Is required. The address lines A0 to A4 are electrically connected to the row decoder 111, and the other address lines A5 to A9 are electrically connected to the column decoder 112.

Defects in some memory cells that occur during the manufacture of a memory device (eg, random access memory (RAM)) cause the entire memory device to behave abnormally, resulting in low manufacturing yields. As the storage capacity of the memory device increases, the memory device has a high density. Thus, the probability of defects on the memory device is further increased, resulting in a low production yield. In order to improve production yield, redundant memory blocks (RMBs) are designed in each memory device. Thus, even if some memory cells in the memory device are defective, it can be replaced with redundant memory cells in the redundant memory block, thereby maintaining an improved production yield.

2 is a block diagram illustrating a memory device having a conventional redundant memory block. Referring to FIG. 2, the memory device 210 additionally includes a redundant memory block (RMB) 214 in a main memory block (MMB) 213. The redundant memory block 214 is composed of memory cells of a plurality of rows. If one row of memory cells in the main memory block 213 fails, an extra row of memory cells in the redundant memory block 214 is used to replace the row of defective memory cells.

2, an address signal IA is input to access data stored in memory cells of a corresponding row in the memory device 210. At this time, if the memory cells of the corresponding row are normal, the address can be correctly designated according to the address signal IA input by the row decoder 211 and the column decoder 212. On the other hand, if the memory cells of the corresponding row are abnormal (defective), then the row decoder 211 is disabled after the address signal IA is compared by the address comparator 220. Next, the extra rows of memory cells in redundant memory block 214 are selected to replace defective memory cells. Therefore, since the memory device 210 has a redundant memory block 214 so that the main memory block 213 can function normally even if the main memory block 213 is partially defective, the production yield of the memory device is improved.

However, the redundant memory block unit 214 is estimated on a row basis. That is, even if only one memory cell is defective in the memory cells of the row of the main memory block 213, the entire memory cells of the defective row are replaced with the memory cells of the row selected from the redundant memory block 214. Therefore, a problem arises in how many redundant memory cells should be prepared when designing a memory device. For example, a row decoder of a 1K × 8-bit memory device is used to address 32 rows of memory cells. In the worst case, when each row of memory cells has one defective memory cell, 32 rows of redundant memory cells are needed to replace it. As a result, the areas of the main memory block 213 and the redundant memory block 214 should have a ratio of 1: 1. This is clearly inefficient.

It is therefore an object of the present invention to provide a memory device having redundant memory blocks that are evaluated in bytes.

According to a feature of the present invention for achieving the object of the present invention as described above, a memory device comprising a redundant memory block includes: a redundant memory block, a first decoder, a second decoder, a multiplexer, a block selection circuit, a plurality of addresses A setting circuit and a redundant address generating circuit.

The first decoder and the second decoder are electrically connected to the main memory block and the redundant memory block. The first decoder accepts a first address signal, and the first decoder accepts the first address signal and a block select signal. The first and second address signals include a first state or a second state. When the block select signal is in the first state, the second decoder selects the main memory block. Conversely, when the block select signal is in the second state, the second decoder selects the redundant memory block.

The multiplexer is controlled by the redundant select signal and receives the second address signal and the third address signal to output the first address signal. When the redundant select signal is deactivated, the multiplexer selects the second address signal as the first address signal. On the other hand, when the redundant select signal is activated, the multiplexer selects the third address signal as the first address signal.

The block selection circuit receives the redundant selection signal and outputs the block selection signal to the second decoder. When the redundant select signal is deactivated, the block select signal is brought to the first state. On the other hand, when the redundant select signal is activated, the block select signal enters the second state.

The address setting circuit is used to generate a plurality of redundant setting address signals, respectively. The redundant address generation circuit is electrically connected to the address setting circuit, the block selection circuit, and the multiplexer, and receives the external redundant setting address signal to output the third address signal and the redundant selection signal. When the second address signal matches one of the redundant set address signals, a corresponding third address signal is output and the redundant set signal is activated.

The memory device further includes a redundant setting circuit outputting a redundant enable / disable signal to enable / disable the redundant address generation circuit. When the redundant enable / disable signal is activated, the redundant address generation circuit is enabled.

The redundant address generating circuit includes a plurality of comparators, an address encoder, and an address selection control circuit.

Each comparator receives the redundant setting address signal and the second address signal from the corresponding address setting circuit and outputs a result signal. When the redundant setting address signal of the corresponding address setting circuit coincides with the second address signal, the result signal is activated. The address encoder receives the result signal of each of the comparators and outputs the third address signal to the multiplexer. The address selection control circuit also accepts the result signal from each of the comparators and outputs the redundant selection signal to the multiplexer. When one of the result signals output from the comparators is activated, the redundant select signal is activated.

The address selection control circuit accepts a redundant enable / disable signal output from the redundant setting circuit. Next, when the redundant enable / disable signal is activated, the address selection control circuit is activated.

The result signal of each comparator, the redundant enable / disable signal, and the redundant select signal are activated at a high potential. The address selection control circuit includes an OR gate and a NAND gate. The OR gate includes a plurality of input terminals for receiving result signals output from the comparators. The NAND gate includes two input terminals receiving the output signal of the OR gate and the redundant enable / disable signal, and output the redundant select signal.

The block select signal, the second multiplexer, controlled by the redundant select signal, includes two input terminals for receiving a first signal in a first state and a second signal in a second state. When the redundant select signal is deactivated, the second multiplexer outputs the first signal as the block select signal. On the other hand, when the redundant selection signal is activated, the second multiplexer outputs the second signal as the block selection signal.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 6.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details.

3 is a block diagram illustrating a circuit configuration of a memory device having a redundant memory block according to an exemplary embodiment of the present invention. As shown in FIG. 3, the memory device 300 includes a memory array 310 and an address control circuit 320. In general, the memory array 310 is used to store required data. The address control circuit 320 may access an internal address signal IA and a block selection signal to access corresponding data stored in the memory array 310 based on an external address signal MA. Used to generate a block selecting signal (SA).

In general, a main memory block (MMB) 313 included in the memory array 310 is mainly used for storing data required under normal conditions. Similar to the prior art, in order to protect the defective memory cells in the main memory block 313 from affecting the function of the entire memory device 300, the memory device 300 is a redundant memory block (RMB). Is designed to have 314. If some of the memory cells in main memory block 313 are defective, the corresponding spare memory cells in redundant memory block 314 are selected to replace the defective memory cells, such that the entire memory device 300 is normal. Maintain the operating state. Decoders 311 and 312 decode the address signal IA into a row decoded signal and a column decoded signal. The row decode signal and column decode signal are used to select a corresponding access address. In general, the decoder 311 is provided as a row decoder, and the decoder 312 is provided as a column decoder. Originally, row decoders and column decoders are defined in the actual circuit design. Moreover, main memory block 313 and redundant memory block 314 share the decoders 311 and 312 together. The decoder 311 receives the address signal IA from the address control circuit 320 and selects a row decode signal to select memory cells of a corresponding row from the main memory block 313 or the redundant memory block 314. Provided as main memory block or redundant memory block. The decoder 312 receives a block selection signal SA as well as an address signal IA from the address control circuit 320 to decode a column to select memory cells of a corresponding column from a main memory block or a redundant memory block. The signal is provided to the main memory block or the redundant memory block. The block select signal SA is also decoded by the decoder 312. Further, the address signal IA is transmitted on a plurality of address lines, and the decoders 311 and 312 are electrically connected to some of the address lines. For example, the 10-bit address signal IA is transmitted on ten address lines IA0 to IA9, and the decoders 311 and 312 are address lines IA0 to IA4 and address lines. Are electrically connected to the respective fields IA5 to IA9. The block select signal SA is used to select one of the main memory block 313 and the redundant memory block 314. For example, the block select signal SA is a 1-bit select signal. In this embodiment, the main memory block 313 is selected when the block select signal SA is at a logic '0' level, and the redundant memory block 314 is configured to set the block select signal SA to a logic '1'. Is selected when

In general, the corresponding access address in the main memory block is selected according to the address signal MA. However, if some memory cells in the corresponding access address are defective, the alternate access address in the redundant memory block is selected by converting the address signal MA through the address control circuit 320 and the decoders 311 and 312. do. Therefore, the entire memory device 300 functions normally even if the memory cells of the main memory block are defective.

In addition, the address control circuit 320 includes a multiplexer 340, a block selection circuit 350, an address setting circuit 361 to 36N, a redundant address generating circuit 330, and a redundant setting circuit 380. .

The multiplexer 340 includes two input terminals (A) and (B), and receives an address signal RA output from an external address signal MA and a redundant address generation circuit 330. The multiplexer 340 includes an output terminal Y for outputting an address signal IA. Furthermore, the multiplexer 340 is controlled by the redundant select signal RS. When the redundant select signal RS is deactivated (eg, at a logic '0' level), the multiplexer 340 selects an external address signal MA and outputs the external address signal MA as an address signal IA. On the contrary, when the redundant select signal RS is activated (eg, at a logic '1' level), the multiplexer 340 selects the address signal RA and outputs the address signal IA. .

The block selection circuit 350 receives the redundant selection signal RS output from the redundant address generation circuit 330 and selects a block for selecting one of the main memory block and the redundant memory block 314. The signal SA is provided to the decoder 312. When the redundant select signal RS is deactivated (eg, at a logic '0' level), the block select signal SA is set to select the main memory block 313 through the decoder 312. do. Conversely, when the redundant select signal RS is activated (eg, at a logic '1' level), the block select signal SA selects a redundant memory block 314 through the decoder 312. Is set to.

The address setting circuits 361 to 36N are used to generate various redundant setting address signals DA1 to DAN according to an address where defective memory cells in the main memory block 313 are located. The redundant address generation circuit 330 receives redundant setting address signals DA1 to DAN and an external address signal MA. When the address signal MA coincides with one of the redundant setting address signals DA1 to DAN, the redundant address generating circuit 330 supplies a corresponding activated address signal RA and a redundant setting signal RS. Output At this time, the multiplexer 340 selects the address signal RA and outputs the address signal IA, and the block selection signal SA is set to select the redundant memory block 314 (eg, For example, logic '1' level).

The redundant enable / disable signal REN output from the redundant setting circuit 380 is an address selection control circuit 334 to enable / disable the redundant address generation circuit 330. Is provided by the enable terminal EN. When the redundant enable / disable signal REN is activated (eg, at a logic '1' level), the redundant address generation circuit 330 is enabled. Conversely, when the redundant enable / disable signal REN is deactivated (eg, at a logic '0' level), the redundant address generation circuit 330 is disabled. After the memory device 300 is fully fabricated, if the main memory block 313 can function normally, extra memory cells in the redundant memory block 314 are unnecessary. At this time, the redundant address generator 330 is disabled by the redundant setting circuit 380.

Referring to FIG. 3, the redundant address generation circuit 330 additionally includes comparators 371 to 37N, an address coder 332, and an address selection control circuit 334.

The comparators 371 to 37N respectively receive the redundant set address signals DA1 to DAN output from the external address signal MA and the address setting circuits 361 to 36N, and the result signals ( CP1 to PN) are output. For example, if the redundant setting address signal DA1 output from the address setting circuit 361 matches the external address signal MA, the result signal CP1 output from the comparator 371 is activated. do. Other comparators perform the same operation as described above. The redundant configuration address signals DA1 to DAN vary, and only one output signal from one comparator is activated, and the output signals of the remaining comparators are deactivated.

The result signals CP1 to CPN from the comparators 371 to 37N are simultaneously transmitted to the address encoder 332 and the address selection control circuit 334. The address encoder 332 generates a corresponding address signal RA according to an activated signal among the result signals CP1 to CPN. The address selection control circuit 334 determines the state of the redundant selection signal RS according to the result signals CP1 to CPN and the redundant enable / disable signal REN. When one of the enable / disable signal REN and one of the result signals CP1 to CPN is activated, the redundant selection signal RS is activated. At this time, the multiplexer 340 selects the address signal RA output from the address encoder 332 and outputs it as an address signal IA, and the address signal IA is transmitted to the memory array 310. do.

FIG. 4 is a detailed circuit diagram illustrating the memory device shown in FIG. 3 in more detail. Referring to FIG. 4, the address selection control circuit 334 includes an OR gate 431 and an AND gate 432, and the redundant setting circuit 380 includes a pull-up resistor. resistor 481 and a fuse 482 that is broken off by a laser. The block select circuit 350 includes a multiplexer 451 whose two input terminals are electrically connected to a high potential and a ground potential, respectively.

The address selection control circuit 334 and the redundant setting circuit 380 cooperate to activate one of the result signals CP1 to CPN at a high logic level, and the redundant enable / When the disable signal REN is activated at the high logic level, the redundant select signal RS is activated at the high logic level.

The result signals CP1 to CPN output from the comparators 371 to 37N are all connected to input terminals of the OR gate 431. Therefore, when one of the result signals CP1 to CPN is activated at the high logic level, the output terminal of the OR gate 431 is set to the high logic level. At the same time, the fuse 482 in the redundant setting circuit 380 is shorted by the register 481 so that the enable / disable signal SEN is pulled up to a high logic level. When both input terminals of the AND gate 432 are at a high logic level, the output terminal of the AND gate 432 is set at a high logic level. At this time, the multiplexer 340 selects the address signal RA by the redundant selection signal RS and outputs it to the output terminal Y.

The multiplexer 451 constituting the block select circuit 350 outputs the input terminals A and B electrically connected to ground potential and high potential, and a block select signal SA to the decoder 312. It has an output terminal (Y). When the redundant select signal RS is deactivated to a low logic level, the multiplexer 451 selects the ground potential of the input terminal A as the block select signal SA. At this time, the decoder 312 designates an address of the main memory block 313. Conversely, when the redundant select signal RS is activated to a high logic level, the multiplexer 451 selects the high potential of the input terminal B as the block select signal SA. At this time, the decoder 312 specifies the address of the redundant memory block 314.

The address setting circuits 316 to 36N are used to generate a redundant setting address signal corresponding to defective memory cells in the main memory block 313.

5 is a circuit diagram illustrating an address setting circuit illustrated in FIGS. 3 and 4.

Referring to FIG. 5, each address setting circuit includes a plurality of pull-up resistors 521 to 52N and pairs of fuses 531 to 53N. The fuses 531 to 53N are shorted by a laser. Taking the pair of the resistor 512 and the fuse 531 as an example, if the fuse 531 is not shorted, the potential of the corresponding signal line RA1 is grounded by the fuse 531 to a ground potential (logical '0' level). Is pulled down). On the contrary, when the fuse 531 is shorted, the potential of the signal line RA1 is pulled up to a high potential (logical '1' level) by the resistor 521. Other pairs of resistors and fuses perform the same operation as described above. Therefore, the corresponding address signal RA is determined by setting the potentials of the signal lines RA1 to RAN according to whether the fuses 531 to 53N are shorted.

6A is a block diagram illustrating a memory array illustrated in FIGS. 3 and 4, and FIG. 6B is a diagram illustrating an address and data arrangement of the memory array illustrated in FIG. 6A.

Referring to FIG. 6A, the operation of the redundant memory block 314 will be described. The storage capacities of the main memory block 313 and the redundant memory block 314 are (1K × 8) bits and (32 × 8), respectively. Bit. Each address can store 8-bit data and requires 10 address lines IA0 to IA9 to transmit the address signal IA. Five address lines IA0 to IA4 are electrically connected to the decoder 311 to address 32 rows of memory cells, and the remaining five address lines IA5 to IA9 are 32 columns of memory cells. Is electrically connected to the decoder 312 to address these devices. Thus, an address in main memory block 313 may be selected via the decoders 311 and 312. The block select signal SA is transmitted to the decoder through an address line IA10 to select one of the main memory block 313 and the redundant memory block 314. When the address line IA10 is at a logic '0' level, the decoder 312 selects memory cells of one row in the main memory block 313. Conversely, when the address line IA10 is at a logic '1' level, the decoder 312 selects the redundant memory block 314 to select a corresponding storage address in conjunction with the decoder 311.

Referring to FIG. 6B, the external address signal MA is transmitted through the address lines A0 to A9, and the internal address signal IA in the memory array 310 is transmitted through the address lines IA0 to IA10. do. The external address lines A0 to A9 may designate addresses within a range of 000h to 3FFh. It is assumed that when the memory device 300 is fully manufactured and tested, some addresses malfunction in the main memory block 313 such as 002h and 130h. To solve this problem, the first and second address setting circuits of the address setting circuits 361 to 36N are set by the laser to generate redundant setting address signals corresponding to malfunctioning addresses 0002h and 130h, respectively. The redundant enable / disable signal REN is activated to select the redundant memory block 314. Except for the 002h and 130h addresses, the remaining addresses in the main memory block 313 may be designated for data access. If access to the data stored in the address 002h is requested, the result signal CP1 of the comparator 371 is activated and sent to the address encoder 332 to generate an address signal RA corresponding to the address 000h. And at the same time to the address selection control circuit 334. Next, the redundant enable / disable signal REN and the redundant select signal RS are activated so that the multiplexer 340 selects the address signal RA of the input terminal B, and the address signal IA is activated. It is output to the output terminal Y of the multiplexer 340. Furthermore, the block select signal SA output from the block select circuit 350 is activated to select the redundant memory block 314. As shown in Fig. 6B, the external address signal MA specifies the address 002h, and the address signal MA is converted into the address signal RA to provide the address signal IA corresponding to the address 000. The block selection signal SA is activated to select a replacement access address in the redundant memory block 314.

Similarly, the external address signal MA specifies an address 130h, the address signal MA is converted into an address signal RA providing an address signal IA corresponding to address 001, and the block selection signal. (SA) is activated such that the redundant memory block 314 is addressed.

Compared with the prior art, the memory device including the redundant memory block according to the present invention has the following advantages. The memory device may be performed in units of bytes so that defective memory cells in the main memory block may be replaced with spare memory cells of the redundant memory block in units of bytes. Therefore, not only the manufacturing yield of the memory device according to the present invention increases but also the redundant memory block can be efficiently used.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to encompass all such modifications and similar constructions.

According to the present invention as described above, the memory device is performed in units of bytes so that defective memory cells in the main memory block can be replaced with spare memory cells of the redundant memory block in units of bytes. Therefore, not only the manufacturing yield of the memory device according to the present invention increases but also the redundant memory block can be efficiently used.

1A is a block diagram showing a circuit configuration of a conventional memory;

1B shows an address and data arrangement of a conventional memory;

2 is a block diagram showing a circuit configuration of a memory device having redundant memory blocks according to the prior art;

3 is a block diagram showing a circuit configuration of a memory device having redundant memory blocks according to a preferred embodiment of the present invention;

4 is a detailed circuit diagram illustrating the memory device shown in FIG. 3 in more detail;

5 is a circuit diagram showing an address setting circuit shown in FIGS. 3 and 4;

FIG. 6A is a block diagram illustrating the memory array shown in FIGS. 3 and 4; And

FIG. 6B is a diagram illustrating the address and data arrangement of the memory array shown in FIG. 6A.

* Description of the symbols for the main parts of the drawings

100, 210, 300: memory device 111, 211: row decoder

112, 212: column decoder 113, 213: main memory block

214: redundant memory block 220: address comparator

310: memory array 311, 312: decoder

313: main memory block 314: redundant memory block

320: address control circuit 330: redundant address generating circuit

340, 451: multiplexer 350; Block selection circuit

361 to 36N: address setting circuit 371 to 37N: comparator

380: redundant setting circuit 334: address selection control circuit

431 OA Gate 432 NAND Gate

481, 521 to 52N: Resistor 482, 531 to 53N: Fuse

Claims (19)

In a memory device comprising redundant memory blocks: A main memory block; Redundant memory blocks; A first decoder electrically connected to the main memory block and the redundant memory block and receiving a first address signal; The main memory block and the redundant memory block electrically connected to the main memory block and the redundant memory block to receive a block selection signal including the first address signal and first and second states, and the main memory block when the block selection signal is in the first state. A second decoder for selecting and selecting the redundant memory block when the block selection signal is in the second state; A multiplexer, controlled by a redundant selection signal, for receiving a second address signal and a third address signal and outputting the first address signal; The second address signal is selected as the first address signal when the redundant select signal is deactivated, and the third address signal is selected as the first address signal when the redundant select signal is activated; Receive the redundant select signal and electrically output the block select signal to the first state when the redundant select signal is deactivated, and to output the block select signal to the second state when the redundant select signal is activated. A block selection circuit connected to each other; A plurality of address setting circuits for generating a plurality of redundant setting address signals, respectively; A redundant address generation circuit electrically connected to the address setting circuits, the block selection circuit and the multiplexer, the redundant address generation circuit receiving the second address signal and outputting the third address signal and the redundant selection signal; And the redundant select signal is activated when the third address signal is transmitted to the multiplexer and the second address signal matches one of the redundant set address signals. The method of claim 1, And a redundant setting circuit for outputting a redundant enable / disable signal to enable / disable the redundant address generation circuit. The method of claim 2, The redundant setting circuit is, With a fuse whose one end is electrically connected to ground potential and shorted by a laser, And a resistor having one end electrically connected to a high potential and the other end electrically connected to the other end of the fuse to output the redundant enable / disable signal. The method of claim 2, The redundant address generation circuit, A plurality of comparators for receiving a redundant setting address signal from the corresponding address setting circuit and the second address signal and outputting a result signal; The result signal is activated when the redundant set address signal coincides with the second address signal; An address encoder having a plurality of input terminals electrically connected to the output terminals of the comparators, the address encoder receiving the result signals output from the comparators and outputting the third address signal to the multiplexer; The address encoder generates the corresponding third address when one of the result signals is activated; An address selection control circuit having a plurality of input terminals electrically connected to the output terminals of the comparators, receiving an output signal from the comparators, and outputting the redundant selection signal, And the redundant select signal is activated when one of the result signals is activated. The method of claim 4, wherein The address selection control circuit is electrically connected with the redundant setting circuit to accept the redundant enable / disable signal, wherein the address selection control circuit is enabled when the redundant enable / disable signal is activated. And a redundant memory block. The method of claim 5, And a corresponding result signal output from each comparator is activated at a high potential. The method of claim 6, And a redundant enable / disable signal is activated at a high potential. The method of claim 7, wherein And the redundant select signal is activated at a high potential. The method of claim 8, And the address selection control circuit includes an OR gate receiving the result signals, an NAND gate receiving the output signal of the OR gate and the redundant enable / disable signal, and outputting the redundant select signal. A memory device comprising redundant memory blocks. The method of claim 1, The block select circuit is a multiplexer controlled by two input terminals for receiving a first signal in a first state and a second signal in a second state and the redundant select signal, wherein the block select circuit includes a redundant select signal. And selecting the first signal as the block selection signal when the first signal is deactivated and selecting the second signal as the block selection signal when the redundant selection signal is activated. The method of claim 1, Each of the address setting circuits, Each end is electrically connected to a ground potential, a plurality of fuses may be shorted by a laser, each end is electrically connected to a high potential, and the other end is electrically connected to the other end of the corresponding fuse; And a plurality of resistors providing a corresponding redundant set address signal. In a memory device comprising redundant memory blocks: A main memory block; Redundant memory blocks; A first decoder electrically connected to the main memory block and the redundant memory block and receiving a first address signal; Is electrically connected to the main memory block and the redundant memory block, and receives a block selection signal including the first address generation signal and first and second states, when the block selection signal is in the first state. A second decoder for selecting a main memory and selecting the redundant memory block when the block selection signal is in the second state; An address control circuit which generates a plurality of redundant set address signals, receives a second address signal, and outputs the first address signal and the block select signal; When the second address signal does not match any of the redundant set address signals, the second address signal is provided as the first address signal, the block select signal is brought into the first state, and the first When a second address signal coincides with one of the redundant set address signals, the second address signal is converted to be provided as a corresponding first address signal, and the block selection signal is set to the second state And a redundant memory block. The method of claim 12, The address control circuit, A plurality of address setting circuits for generating a plurality of redundant setting address signals, respectively; A plurality of comparators for respectively receiving a redundant setting address signal and a second address signal output from a corresponding address setting circuit and outputting a result signal; The result signal is activated when the redundant set address signal coincides with the second address signal; Having a plurality of input terminals electrically coupled with the output terminals of the comparators, receiving the result signals output from the comparators, and outputting a corresponding third address signal when one of the result signals is activated An address encoder; An address selection control circuit having a plurality of input terminals electrically connected to the output terminals of the comparators, receiving the result signals output from the comparators, and outputting the redundant selection signal; The redundant selection signal is activated when one of the result signals is activated; A multiplexer controlled by the redundant select signal, which receives the second address signal and the third address signal and outputs the first address signal as the first address signal; The second address signal is selected as the first address signal when the redundant select signal is deactivated, and the third address signal is selected as the first address signal when the redundant select signal is activated; A block selection circuit electrically connected to the second decoder and receiving the redundant setting signal and outputting the block selection signal to the second decoder; And the block select signal is in the first state when the redundant select signal is deactivated, and the block select signal is in the second state when the redundant select signal is activated. Device. The method of claim 13, And the address control circuit further comprises a redundant setting circuit for outputting a redundant enable / disable signal for enabling / disabling the address setting control circuit. The method of claim 14, And a corresponding result signal output from each comparator is activated at a high potential. The method of claim 15, And a redundant enable / disable signal is activated at a high potential. The method of claim 16, And the redundant select signal is activated at a high potential. The method of claim 17, And the address selection control circuit includes an OR gate receiving the result signals, an NAND gate receiving the output signal of the OR gate and the redundant enable / disable signal, and outputting the redundant select signal. 12. A memory device comprising a redundant memory block comprising a redundant memory block. The method of claim 13, The block select circuit is a multiplexer controlled by two input terminals for receiving a first signal in a first state and a second signal in a second state and the redundant select signal, wherein the block select circuit includes a redundant select signal. And selecting the first signal as the block selection signal when the first signal is deactivated and selecting the second signal as the block selection signal when the redundant selection signal is activated.