KR100487365B1 - viterbi decoding method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding method, particularly for a communication channel having a variable data rate in mobile communications, wherein the rate determined in the previous frame is loaded at the decoding rate for the current frame. Decoding the current frame at the loaded decoding rate, and comparing a cyclic redundancy code (CRC) check result and the number of bit errors of the current frame generated from the decoding result with a predetermined criterion; And reloading the decoding rate for the loaded current frame at a predetermined next rate when the result of the cyclic redundancy code (CRC) check of the current frame and the number of bit errors in the comparison result do not meet the criteria. Viterbi consisting of re-decoding the current frame at the reloaded rate Provide a decoding method.

Description

Viterbi decoding method

TECHNICAL FIELD The present invention relates to mobile communications, and in particular, to a Viterbi decoding method for a communication channel having a variable data rate.

In general, errors occur when transferring data. An Error Correction Code is used to perform this error.

The error correction code is a convolutional code. Convolutional coding using the convolutional code uses a certain length of memory to compare previous data with the current data, and then Coding technique that encodes through correlation.

Convolutional codes include Viterbi codes and Turbo codes. Viterbi codes are currently used in communication systems (eg, CDMA communication systems).

The following describes the configuration and operation of a conventional Viterbi decoder using Viterbi code.

1 is a block diagram showing the structure of a Viterbi decoder according to the prior art.

Referring to FIG. 1, the Viterbi decoder adds and compares an input buffer 1 with a branch metric value output from the input buffer 1 and a previous path metric value. add / compare / select block (2) for performing a compare and select procedure, and decision bit information output from the add / compare / select block (2), and trace-trace a predetermined length. a trace-back block 3 that outputs data after being backed up, and a series of operations of the input buffer 1, the addition / compare / selection block 2, and the traceback block 3 described above. The controller 4 for controlling the control, the output butter 5 for storing the data extracted from the traceback block 3, and the cyclic redundancy code (hereinafter abbreviated as CRC) for each data rate The CRC check block 6 to check, the hard decision value for each data rate and the decoded by the components 1, 2 and 3 described above. Re-encoding (re-encoding) the error probability per bit as compared to the value of the data; calculating (Bit Error Rate hereinafter abbreviated as BER hereinafter), and consists of a BER block 7 which outputs the number of bit errors thereof.

The operation of the Viterbi decoder according to the above configuration is as follows.

Once the input bits are made two symbols, the branch metric values obtained from these two symbols are stored in the input buffer 1. In addition, the input buffer 1 stores path metric values generated by previous input symbols.

The add / compare / select block 2 adds a branch metric value and a path metric value output from the input buffer 1, and compares two values that transition to the same state. . Thereafter, a portion having a smaller value is selected, and the state transition information (decision bit information) at that time is provided to the trace-back block 3.

The trace-back block 3 stores decision bit information received from the addition / comparison / selection block 2 and traces back a predetermined length to restore the encoded data. )do.

The data output from the backtracking block 3 is stored in the output buffer 5. For reference, in case of using four rates such as full rate, half rate, quarter rate and 1/8 rate for variable rate transmission, The decoded data according to each rate is stored in the output buffer 5. Here, the full rate is 36kbps, the half rate is 18kbps, the quarter rate is 9kbps and the 1/8 rate is 4.5kbps.

When data decoded according to each variable rate is stored in the output buffer 5, the CRC check block 6 checks each CRC for those rates. If the CRC of the rate matches in the CRC test result, "True" is output as the value of the signal (crc_ok) indicating the CRC test result, and "False" is output in the opposite case.

Also, when data decoded according to each variable rate is stored in the output buffer 5, the BER block 7 performs hard decision and re-encoding on those rates. The BER is then calculated by comparing the hard decision value for each rate with the re-encoding value of the decoded data, and outputs the number of bit errors accordingly.

The following is an example to describe in detail the operation according to each rate for the conventional Viterbi decoder.

Prior to this, data to be decoded by a microprocessor (not shown) is first written to the input buffer 1.

2 is a diagram illustrating an example for explaining a Viterbi decoding procedure according to the prior art.

Referring to FIG. 2, first, a decoding operation on a full rate is performed during A-time. In this case, first, data (decision bit information) necessary for the backtracking block 3 is created through the addition / comparison / selection block 2, and stored in the memory (not shown) of the backtracking block 3, and the backtracking is performed. Decoding is performed by the internal circuit of block 3. The decoded data produced through this operation is stored in the output buffer 5.

During the next B-time, the decoding operation for half rate is performed. In this case, the same procedure as the decoding operation for the full rate described above is performed, and the decoded data generated through the operation during the B-time is stored in the output buffer 5.

During the next C-time, the decoding operation for the quarter rate is performed, and during the next D-time, the decoding operation for the 1/8 rate is performed. These operations also go through the same procedure as the decoding operation for the full rate described above, and the decoded data produced during C-time and D-time, respectively, is also stored in the output buffer 5.

In FIG. 2, A-point 10 is a point at which decoded data is written to the output buffer 5 through a decoding operation for full rate, and B-point 11 is a half rate. Decoded data is output to output buffer 5 through each decoding operation at C-point 12 at quarter rate and D-13 at 1/8 rate. Each is written at a time.

After the series of operations described so far, the microprocessor (not shown) carries data of each rate determined after each decoding procedure with the CRC check information and the BER information provided from the CRC check block 6 and the BER block 7. Read from output buffer (5).

However, the conventional Viterbi decoder has the following disadvantages. It uses all the possible data rates of the vocoder, ie for communication channels with variable data rates, where the decoding is done every frame, of which only the result of the determined rate is used.

As a result, the conventional Viterbi decoder has a problem in that processing time for rate determination is required.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above points, and in particular, to reduce the processing time for rate determination, a Viterbi decoding method for changing the rate determination of the current frame step by step from the data rate determined in the previous frame is provided. To provide.

A feature of the Viterbi decoder according to the present invention for achieving the above object is a decoding block for decoding, a controller for controlling the decoding block, and a cyclic redundancy code (CRC) for the current frame decoded in the decoding block. A cyclic redundancy code (CRC) check block that performs a check and outputs the information, an error probability per bit block that outputs the number of bit errors for the current frame decoded by the decoding block, and the cyclic redundancy code And a rate controller for comparing the respective output values of the (CRC) check block and the error probability per bit (BER) block with a predetermined reference value and determining a decoding rate for the current frame according to the comparison result.

In this case, the rate controller informs the controller of the determined decoding rate so that the decoding block can be decoded to the determined decoding rate and then decoded for the current frame.

A feature of the Viterbi decoding method according to the present invention for achieving the above object is the step of loading the rate determined in the previous frame to the decoding rate for the current frame, and the current frame at the loaded decoding rate Performing a decoding process, comparing a CRC test result and a number of bit errors of the current frame generated from the decoding result with a predetermined criterion, and performing a cyclic redundancy of the current frame in the comparison result. Reloading the decoding rate for the loaded current frame at a predetermined next rate if a code (CRC) check result and the number of bit errors do not meet the criteria, and decoding the current frame at the reloaded rate. It is made to re-execute.

Preferably, the full rate is loaded at the decoding rate when the current frame is the first frame.

If the comparison result indicates that the CRC test result and the number of bit errors of the current frame are satisfied, decoding of the current frame is stopped.

Finally, the cyclic redundancy code of the current frame is obtained from a result of comparing a cyclic redundancy code (CRC) test result of the current frame generated from the re-executed decoding result and the number of bit errors with If the CRC) check result and the number of bit errors do not meet the criteria, the decoding is performed by continuously reloading the rate to a supportable rate for the frame.

Hereinafter, a preferred embodiment of the Viterbi decoding method according to the present invention will be described with reference to the accompanying drawings.

In the present invention, the rate determination of the current frame is changed step by step from the data rate determined in the previous frame. To this end, we propose a Viterbi decoding procedure that conforms to the rate determination algorithm of a variable rate vocoder and a Viterbi decoder for executing the same. This makes it possible to increase the probability of hitting the rate determination.

Prior to the description of the Viterbi decoder of the present invention, the characteristics of the voice call related to the present invention are briefly mentioned.

In the case of a voice call, it is generally within about 40% of the time that the voice is actually transmitted and received. Also, the data rate change of each successive frame transmitted from the speaker does not occur at all possible data rates, but changes step by step at the data rate of the previous frame (the change is relatively slow). The data rate of a frame transmitted from the listener is likely to be a quarter rate or 1/8 rate, and the likelihood of the data rate changing is greater than the possibility of a change in the data rate of a frame transmitted from the speaker. low. The present invention takes advantage of this feature of voice communication.

3 is a block diagram showing the structure of a Viterbi decoder according to the present invention.

Referring to FIG. 3, the Viterbi decoder of the present invention adds using an input buffer 100, a branch metric value output from the input buffer 100, and a previous path metric value. Add / compare / select block 110 for performing a compare and select procedure, and decision bit information output from the add / compare / select block 110, and backtrack a predetermined length. the trace-back block 120 for outputting data after the trace-back, the input buffer 100, the add / compare / selection block 110, and the traceback block 120. A controller 130 for controlling the decoding operation to be performed at a preset rate, an output butter 140 storing data extracted from the backtracking block 120, and a CRC check block for checking a CRC for each data rate. 150, a hard decision value for each data rate and the components 100, Comparing the re-encoding value of the data decoded by the 110, 120 to calculate the BER, and outputs the number of bit errors according to the BER block 160, and finally decoding at the rate determined in the previous frame The controller 130 controlling the blocks 100, 110 and 120 for decoding to start is provided to the control signal Rate_sel by the rate selection, and the CRC check output from the CRC check block 150 and the BER block 160 described above. It consists of a rate controller 170 having information and BER information to determine the rate of the frame currently decoding.

In the present invention, since the rate controller 170 is used to determine the rate of the frame currently being decoded, the decoding processing time compared to the conventional method of determining the rate of the frame after each decoding procedure with CRC check information and BER information. This is shortened.

The Viterbi decoder of the present invention according to the above configuration is as follows.

Once the input bit is made two symbols, the branch metric value obtained from the two created symbols is stored in the input buffer 100. In addition, the input buffer 100 stores path metric values generated by previous input symbols.

The add / compare / select block 110 adds a branch metric value and a path metric value output from the input buffer 100 and compares two values that transition to the same state. . Thereafter, a portion having a smaller value is selected and the state transition information (decision bit information) at that time is provided to the trace-back block 120.

The trace-back block 120 stores decision bit information received from the addition / comparison / selection block 110 and trace-backs a predetermined length to restore the coded data. )do.

The data output from the backtracking block 120 is stored in the output buffer 140, and the decoded data according to each rate is stored in the output buffer 140.

When data decoded according to each variable rate is stored in the output buffer 140, the CRC check block 150 checks each CRC for those rates. If the CRC of the rate matches in the CRC test result, "True" is output as the value of the signal (crc_ok) indicating the CRC test result, and "False" is output in the opposite case.

In addition, when data decoded according to each variable rate is stored in the output buffer 140, the BER block 160 performs hard decision and re-encoding on those rates. Then, BER is calculated by comparing a hard decision value for each rate and a re-encoding value of decoded data, and the number of bit errors corresponding thereto is output through a notification signal ber_num.

The next rate controller 170 provides a control signal Rate_sel by selecting a rate to the controller 130 that controls the blocks 100, 110, and 120 for decoding to start decoding at the rate determined in the previous frame. The controller 130 may also determine a signal Rate_sel that determines the rate of the frame currently being decoded by referring to the signals crc_ok and ber_num output from the CRC check block 150 and the BER block 160. Output to. In addition, if the current decoded rate meets a predetermined criterion, the rate controller 170 transmits a signal (Oper_stop) to the controller 130 to stop the further decoding procedure for the current frame.

The peculiarity of the present invention is that the controller 130 controls the decoding related blocks 100, 110, 120 so as to perform decoding first at the rate set by the rate select signal Rate_sel of the rate controller 170 when the current frame starts. This is a case where the stop signal Opera_stop of the rate controller 170 is not enabled.

However, if the stop signal Opera_stop of the rate controller 170 is enabled, the controller 130 controls the decoding related blocks 100, 110, and 120 so that the decoding of the next rate is no longer performed. The determined rate is stored.

The following is an example to explain in more detail the operation according to each rate for the Viterbi decoder of the present invention described above.

4 is a diagram illustrating an example for explaining a Viterbi decoding procedure according to the present invention.

Referring to FIG. 4, first, the intervals of A-time, B-time, C-time, and D-time are in turn full rate, half rate, quarter rate, and Decoding times for each 1/8 rate (1/8 rate), and decoding ends at the end point (D-point) 13 of the D-time.

First, in the case of the first frame having no information on the previous frame, it proceeds in the same manner as the conventional decoding procedure.

Next, the operation of the first case (Case-1-1) will be described.

First, when data of a previous frame is full rate, decoding of the current frame is performed at full rate. As a result, the generated CRC check information and BER information are transmitted to the rate controller 170. After receiving the information, the rate controller 170 enables a signal (Oper_stop) to stop decoding for the next rate when the CRC check result and the number of bit errors are within an appropriate value. The controller 130 controls the decoding related blocks 100, 110, and 120 to no longer perform decoding as the stop signal Op_stop is enabled.

As a result, the decoding is completed at the A-point 10, and then the decoding procedure for the B-time, C-time, and D-time is omitted.

The following describes the operation of the second case (Case-1-2).

This is for the case where the CRC check result and the number of bit errors by the decoding of the full rate are more than an appropriate value in the first case described above.

Thereafter, the rate controller 170 determines the rate of the current frame as half rate, and performs decoding on the current frame at half rate. After that, the CRC check information and the BER information generated from the half-rate decoding result are transferred to the rate controller 170. When the rate controller 170 receives these information, the CRC check result and the number of bit errors are within an appropriate value, Enable signal Op_stop to stop decoding for the next rate.

As a result, the decoding is completed at the B-point 11, and then the decoding procedure for the C-time and the D-time is omitted.

Next, operation of the third case (Case-2-1) will be described.

First, when the data of the previous frame is half rate, the decoding of the current frame is performed at half rate. As a result, the generated CRC check information and BER information are transmitted to the rate controller 170. After receiving the information, the rate controller 170 enables a signal (Oper_stop) to stop decoding for the next rate when the CRC check result and the number of bit errors are within an appropriate value. The controller 130 controls the decoding related blocks 100, 110, and 120 to no longer perform decoding as the stop signal Op_stop is enabled.

As a result, the decoding is completed at the E-point 14, and then the decoding procedure is omitted for a time from the E-point 14 to the D-point 13.

Next, operation of the fourth case (Case-2-2) will be described.

This is the case in the third case (Case-2-1) described above, when the CRC check result and the number of bit errors by the decoding of the half rate are more than an appropriate value.

Thereafter, the rate controller 170 determines a rate of the current frame as a quarter rate, and performs decoding on the current frame at a quarter rate. After that, the CRC check information and the BER information generated from the decoded result by the quaternate are transmitted to the rate controller 170. When the rate controller 170 receives these information, the CRC check result and the number of bit errors are within an appropriate value, Enable signal Op_stop to stop decoding for the next rate.

As a result, the decoding is completed at the F-point 15, and then the decoding procedure is omitted for a time from the F-point 15 to the D-point 13.

Next, operation of the fifth case (Case-2-3) will be described.

In this case also in the third case (Case-2-1), the CRC test result and the number of bit errors by decoding the half rate is more than an appropriate value.

Thereafter, the rate controller 170 determines a rate of the current frame as a quarter rate, and performs decoding on the current frame at a quarter rate. After that, the CRC check information and the BER information generated from the result of decoded by the quarter are transmitted to the rate controller 170. When the rate controller 170 receives the information, the CRC check result and the number of bit errors are again higher than appropriate values. The rate of the current frame is set to the full rate, and the decoding of the current frame is performed at the full rate. Thereafter, the signal Op_stop, which stops decoding at the B-point 11, is enabled.

As a result, the decoding is completed at the B-point 11, and then the decoding procedure for the C-time and the D-time is omitted.

Next, operation of the sixth case (Case-3-1) is explained.

First, when the data of the previous frame is a quarter rate, the decoding of the current frame is performed in the quarter rate. As a result, the generated CRC check information and BER information are transmitted to the rate controller 170. After receiving the information, the rate controller 170 enables a signal (Oper_stop) to stop decoding for the next rate when the CRC check result and the number of bit errors are within an appropriate value. The controller 130 controls the decoding related blocks 100, 110, and 120 to no longer perform decoding as the stop signal Op_stop is enabled.

As a result, the decoding is completed at the G-point 16, and then the decoding procedure is omitted for a time from the G-point 16 to the D-point 13.

The following describes the operation of the seventh case (Case-3-2).

This is the case in the sixth case (Case-3-1), the CRC check result and the number of bit errors by the decoding of the quarter rate is more than an appropriate value.

Thereafter, the rate controller 170 sets the rate of the current frame at 1/8 rate, and performs decoding on the current frame at 1/8 rate. After that, the CRC check information and the BER information generated from the decoding result of 1/8 rate are transmitted to the rate controller 170, and the rate controller 170 receiving these information has a CRC check result and the number of bit errors within an appropriate value. In this case, the signal Op_stop, which stops decoding for the next rate, is enabled.

As a result, the decoding is completed at the H-point 17, and then the decoding procedure is omitted for a time from the H-point 17 to the D-point 13.

Next, the operation of the eighth case (Case-3-3) is explained.

In this case, too, in the sixth case (Case-3-1), the CRC check result and the number of bit errors due to the decoding of the quarter rate are more than appropriate values.

Thereafter, the rate controller 170 sets the rate of the current frame at 1/8 rate, and performs decoding on the current frame at 1/8 rate. After that, the CRC check information and the BER information generated from the decoding result at 1/8 rate are transmitted to the rate controller 170, and the rate controller 170 receiving these information has a CRC check result and the number of bit errors again more than an appropriate value. In this case, the rate of the current frame is set to half rate, and the decoding of the current frame is performed at half rate. Thereafter, the signal Op_stop, which stops decoding at the F-point 15, is enabled.

As a result, the decoding is completed at the F-point 15, and then the decoding procedure is omitted for a time from the F-point 15 to the D-point 13.

A summary of all operation examples through FIG. 4 may be expressed as follows in FIG. 5.

5 is a flowchart illustrating an algorithm for the operation of the Viterbi decoder according to the present invention, and is a flowchart illustrating an operation example according to each case of FIG. 4.

At the first starting point, the rate at which decoding for this frame is to be started is loaded (S1). However, if this frame is the first frame, it starts at full rate. On the other hand, if it is not the first frame, decoding starts at the rate determined in the previous frame.

By doing so, the present invention can reduce the decoding time using the continuity of every frame.

Then, as is done in each case of FIG. 4 described above, the CRC check result and the number of bit errors generated in the result decoded at the rate for the previous frame are loaded by the rate controller 170 (S2).

After that, when the value of the signal crc_ok indicating the CRC test result is "True", the bit error number ber_num is again compared with a predetermined threshold value BER_LIMIT (S3 to S4). At this time, if the number of bit errors ber_num is smaller than the predetermined threshold BER_LIMIT, the controller 130 stores the current decoded rate and informs the controller 130 to decode at the stored rate first when the next frame starts. This is done by the rate controller 170.

However, if the value of the signal (crc_ok) indicating the CRC test result is not "True", the controller 130 is notified to decode at the next rate for this frame, and the threshold value determined by the number of bit errors (ber_num) ( BER_LIMIT), the controller 130 is instructed to perform decoding at the next rate for this frame. This is also done by the rate controller 170.

As described above, the Viterbi decoding method according to the present invention has the following effects.

In the present invention, since the rate determination of the current frame is changed step by step from the data rate determined in the previous frame, the processing time for the rate determination can be reduced. Therefore, the present invention can be more effectively applied to communication channels having variable data rates.

In more detail, unlike the conventional method in which four decodings are performed in one frame time, the present invention uses the characteristic that the data rate of the current frame has the same probability as the data rate of the previous frame. By starting with the decoding rate of, we eliminated the unnecessary decoding procedure for successive frames.

As a result, the power consumption of the circuit for Viterbi decoding can be significantly reduced.

1 is a block diagram showing the structure of a Viterbi decoder according to the prior art.

2 is a diagram illustrating an example for explaining a Viterbi decoding procedure according to the prior art.

3 is a block diagram showing the structure of a Viterbi decoder according to the present invention.

4 is a diagram illustrating an example for explaining a Viterbi decoding procedure according to the present invention.

5 is a flowchart illustrating an algorithm for operation of a Viterbi decoder according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: input buffer 110: addition / comparison / selection block

120: backtracking block 130: controller

140: output buffer 150: CRC check block

160: BER block 170: rate controller

Claims (6)

Loading the rate determined in the previous frame at the decoding rate for the current frame;  Performing decoding on the current frame at the loaded decoding rate; Comparing a cyclic redundancy code (CRC) check result and a number of bit errors of the current frame generated from the decoding result with a predetermined criterion; Reloading the decoding rate for the loaded current frame at a predetermined next rate when the result of the cyclic redundancy code (CRC) check of the current frame and the number of bit errors in the comparison result do not meet the criteria; And re-decoding the current frame at the reloaded rate. The Viterbi decoding method of claim 1, wherein when the current frame is the first frame, a full rate is loaded at the decoding rate. The Viterbi decoding method of claim 1, wherein the decoding of the current frame is stopped when the comparison result of the CRC test and the number of bit errors of the current frame are satisfied. 2. The method of claim 1, wherein after the decoding re-executing step, the cyclic redundancy code (CRC) check result of the current frame generated from the re-executed decoding result and the number of bit errors are compared with a predetermined criterion. And if the duplicated code (CRC) check result and the number of bit errors do not meet the criteria, the decoding is continued by reloading the rate to a rate that can be supported for the frame. delete delete