KR100486708B1 - Magnetic randon access memory and operating method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic random access memory, comprising: a gate having a substrate, a first impurity layer and a second impurity layer formed by doping an impurity on the substrate, and a gate conducting layer formed as a word line between the impurity layer on the substrate A MOSFET element comprising a; A memory element formed on the first impurity layer and including a magnetic material; A bit line connected with the first impurity layer through the memory element; A plate line connected to the second impurity layer; And an insulating layer formed between each of the components. The magnetic random access memory includes only three metal lines, so that data can be written and read using only word lines, bit lines, and plate lines. A simpler form of magnetic random access memory can be implemented.

Description

Magnetic random access memory and its operation method

The present invention relates to a magnetic random access memory, and more particularly, to a magnetic random access memory including only word lines, bit lines, and plate lines, the same size as a transistor, and a method of operating the same.

Magnetic Random Access Memory (MRAM), or MRAM, is a new solid-state magnetic memory that utilizes magnetoresistive effects based on spin-dependent conduction phenomena unique to nanomagnetic materials as one of nonvolatile memory devices. The magnetic random access memory utilizes a giant magnetoresistance phenomenon or a tunnel magnetoresitance phenomenon caused by spin, which is the degree of freedom of electrons, greatly affects the electron transfer phenomenon.

Giant magnetoresistance refers to a phenomenon in which a difference in resistance occurs when a spin arrangement between ferromagnetic materials formed with a nonmagnetic material interposed between ferromagnetic materials / nonmagnetic metal materials and ferromagnetic materials is opposite to the same case. The tunnel magnetoresistance refers to a phenomenon in which the current is easier to transmit than the case in which the arrangement of the spins in the two ferromagnetic layers is the same in the continuous arrangement of the ferromagnetic / insulator / ferromagnetic materials. In the case of MRAM using a large magnetoresistance phenomenon, the voltage difference cannot be increased because the difference in resistance along the magnetization direction is relatively small. In addition, there is a disadvantage in that the size of a MOSFET used in combination with a GMR film to form a cell has to be increased. Currently, researches for the practical use of an MRAM are being actively conducted by employing a TMR film.

1 is a cross-sectional view showing a magnetic random access memory device according to the prior art. Impurity layers 111 and 112 formed to be spaced apart from each other are formed on the substrate 100, and the gate oxide layer 113 and the gate conductive layer 114 are formed on the substrate 100 between the impurity layers 111 and 112. ) Is formed. In addition, first and second via holes 116a and 116b through which the impurity layers 111 and 112 are exposed are formed in the first interlayer insulating layer 117 on the substrate 100, respectively. 120b is filled with conductive plugs 120a and 120b. In addition, conductive layer patterns 121a and 121b may be formed on the first interlayer insulating layer 117 to cover the via holes 116a and 116b, and the conductive patterns 121a and 121b may be formed on the second interlayer insulating layer 118. Is covered in. The third via hole 122a through which the first conductive layer pattern 121a is exposed is formed in the second interlayer insulating layer 118, and the inside thereof is filled with the conductive plug 122. In addition, third and fourth conductive layer patterns 123a and 123b are formed on the second interlayer insulating layer 118 to cover the exposed entire surface of the conductive plug 122 and cover the third interlayer insulating layer 118. 119 is formed. A fourth via hole 124a exposing the fourth conductive layer pattern 123b is formed in the third interlayer insulating layer 119. A fourth via hole 124a is formed on the third interlayer insulating layer 119, and is expanded onto the fourth conductive layer pattern 123a while filling the fourth via hole 124a on the third interlayer insulating layer 119. The fifth conductive layer pattern 124 is formed. Here, a TMR element 127 having a continuous structure of a ferromagnetic film 127a / insulator film 127b / ferromagnetic film 127c is formed on the fifth conductive layer 124 pattern. In this case, an antiferromagnetic layer may be further included to fix the spin alignment of the uppermost or the lowest magnetic layer among the magnetic layers 127a and 127c. A bit line 126 is formed on the third interlayer insulating layer 119 to cover the fifth conductive layer pattern 124 and contact the magnetic layer of the TMR element 127.

In the conventional magnetic random access memory (MRAM), a write word line and a read word line are separately configured to require at least four metal lines. As a result, the complexity of the process is increased, resulting in a decrease in yield. Considering the structure that includes three metal lines by sharing the word lines of the transistors, in this case, it is necessary to alternately apply the positive voltage and the negative voltage to the word lines, which makes the peripheral circuit for the operation of the device complicated. There are disadvantages to losing.

In the present invention, in order to solve the problems of the prior art, it is composed of only the word line, bit line and plate line in the simplest form of 1T (transistor) -1C (capacitor), the manufacturing process is simple, the operation method is simple It is an object to provide a magnetic random access memory.

In the present invention, to achieve the above object,

A MOSFET element comprising a substrate, a gate including a first impurity layer and a second impurity layer formed by doping an impurity on the substrate, and a gate conductive layer formed between the impurity layer on the substrate and a word line;

A memory element formed on the first impurity layer and including a magnetic material;

A bit line connected with the first impurity layer through the memory element;

A plate line connected to the second impurity layer; And

It provides a magnetic random access memory comprising only three metal lines, including an insulating layer formed between each of the components.

In the present invention, the memory element is a GMR element or a TMR element.

In the present invention, the TMR element is a multilayer film having an insulating layer formed between the ferromagnetic layers, it is preferable to include an antiferromagnetic layer on the top or bottom of the multilayer film.

In the present invention, it is preferable to further include a conductive plug formed between the memory element and the first impurity layer.

In the present invention, it is preferable to further include a buffer layer formed between the conductive plug and the memory element and between the memory element and the bit line.

In the present invention, it is preferable to further include a gate insulating film formed between the gate conductive layer and the substrate.

In the present invention, it is preferable to further include a sense amplifier connected to the plate line.

In addition, the present invention includes a MOSFET element having a first impurity layer and a second impurity layer formed by doping an impurity on a substrate and a word line serving as a gate conducting layer formed between the impurity layer on the substrate; A memory element formed on the first impurity layer and including a magnetic material; A bit line connected with the first impurity layer through the memory element; A plate line connected to the second impurity layer; And an insulating layer formed between the components, the method of operating a magnetic random access memory comprising:

(A) For addressing, a voltage Vb is applied to the bit line to flow a current, and a voltage Vp is applied to the plate line to flow a current in one direction, and then a resistance is formed in the memory element. Recording to data; And

(B) applying a voltage Vr to the bit line for addressing, applying the word line voltage Vw to sense current flowing through the plate line and reading data according to a resistance value written in the memory element; It provides a method of operating a magnetic random access memory comprising a.

In the present invention, step (b) preferably detects a current through a sense amplifier connected to the plate line.

Hereinafter, the magnetic random access memory according to the present invention will be described in detail with reference to the drawings.

2 is a cross-sectional view showing a magnetic random access memory according to the present invention. An embodiment of the structure of the magnetic random access memory according to the present invention will be described with reference to FIG. The first impurity layer 212a and the second impurity layer 212b are formed by doping conductive substrates, for example, p-type impurities, to the substrate, and spaced apart from each other on the semiconductor substrate 211. Is formed. The first and second impurity layers 212a and 212b are doped with conductive impurities opposite to the doped impurities in the semiconductor substrate 211, and are n-type impurities. If n-type impurities are doped into the semiconductor substrate 211, p-type impurities may be doped into the first and second impurity layers 212a and 212b. Here, a gate including a gate insulating layer 213b and a gate conductive layer 213a is stacked on the semiconductor substrate 211 between the first and second impurity layers 212a and 212b. As described above, the magnetic random access memory according to the present invention includes a MOSFET. The gate conducting side 213a is used as a word line in the present invention. The interlayer insulating layer 220 is coated on side surfaces and upper surfaces of the gate insulating layer and the gate conductive layer.

The via hole 214 exposing the first impurity layer 212a is formed in the interlayer insulating layer 220, and the via hole 214 exposing the first impurity layer 212a is filled with a conductive plug 215. have. A memory element 217 is formed on the conductive plug 215 to store information according to the spin arrangement. Here, the memory device may have a GMR structure composed of a multi-layered film of ferromagnetic material / non-magnetic material / ferromagnetic material, preferably has a TMR structure of a multilayer film of ferromagnetic material 217a / insulator 217b / ferromagnetic material 217c It is preferable. The TMR structure according to the present invention is not significantly different from the general TMR structure, and is more advantageous than the GMR structure due to the large difference in current conductivity according to the spin array direction.

The bit line 219 made of a conductive material is formed on the TMR structure. Wherein a first buffer layer 216 is formed between the bit line 219 and the memory element 217 of the TMR structure and between the conductive plug 215 and the memory element 217 of the TMR structure to facilitate the formation of a multilayer thin film. It is preferable to further include). In this case, an interlayer insulating layer 220 is coated on side surfaces of the gate conductive layer 213a, the memory element 217, and the bit line 219. The plate line 221 is formed on the interlayer insulating layer 220 in a direction perpendicular to the formation direction of the bit line 219 and the gate conductive layer 217. That is, the bit line 219 and the plate line 221 are formed above the substrate 211 and extend in the vertical direction to form a matrix, and represent an array structure including a large number of magnetic random access memories. The plate line 221 is connected to the second impurity layer 212b formed on the substrate 211.

3 shows an equivalent circuit in the case where the magnetic random access memory according to the present invention is shown in an array structure. Here, four magnetic random access memory devices are shown. A gate conducting layer used as a word line Wn and a bit line Bn on the TMR structure layer pass through the array in a direction parallel to each other, and the plate line Pn is the word line Wn and the bit. Notice the passing of the array in a direction perpendicular to the line Bn.

A method of operating the magnetic random access memory according to the present invention as described above will be described in more detail with reference to the accompanying drawings.

The magnetic random access memory according to the present invention is characterized in that the "write" process is performed with bit lines and plate lines, and "read" is characterized by gate lines (or word lines), bit lines, and plate lines.

4A, 4B, and 4C illustrate writing "1" or "0" in the "write" process of the magnetic random access memory according to the present invention. In a magnetic random access memory array, a position of a desired element is first determined and a voltage is applied to bit lines and plate lines having corresponding addresses of the designated elements. As described above, only the bit line 219 and the plate line 221 are used in the “write” process in the random access memory according to the present invention. As shown in FIG. 4A, the direction change of the current flowing through the bit line and the plate line is changed. So that "1" and "0" are recorded. In the present invention, the bit line 219 serves as a reference, and the voltage Vb is applied to only one side of the bit line 219 so that the current i flows in one direction, and the opposite transistor is grounded. The plate line 221 applies a voltage Vb after applying the voltage of the bit line 219 to flow a current i in one direction. The resistance R ₁ of the entire TMR element 217 is formed according to the spin direction of the ferromagnetic layers 217a and 217c with the insulating layer 217b of the 217 interposed therebetween, and is designated as "1". At this time, when the sense amplifier (S / A) is located at the end of the line, the T _WRN is grounded or turned off.

In the case of writing "0", the direction of the current flowing by applying a voltage is reversed from the case of writing "1". That is, a current of -i flows using the bit line 219 as an addressing reference. Next, a current -i flows through the plate line 221 to form a resistor R ₀ in the TMR element 217 and designates it as "0".

Next, the "read" process of the magnetic random access memory according to the present invention will be described in more detail. 5A, 5B and 5C are diagrams for explaining a "read" process of the magnetic random access memory according to the present invention. In the case of a “read” process as shown in FIG. 5A, a voltage is applied to the bit line 219 and the word line 213a to measure a current flowing through the plate line 221 to obtain a data value stored in the TMR element 217. It is characterized by reading. As shown in Figs. 5B and 5C, first, a voltage V _r is applied to a bit line 219, which becomes an addressing reference, and then a voltage Vw is applied to a word line 213a to turn on the MOSFET and to both ends of the TMR element. The voltage difference is read out through the sense amplifier S / A connected to the plate line 221. This depends on the resistance of the TMR element in the "write" process. At this time, as shown in FIG. 5B, in the memory array, each of the transistors in the peripheral state is turned off to operate only the sensor amplifier connected to the plate line 221.

Although many details are specifically disclosed in the above-mentioned detailed description, this should not be construed as limiting the scope of the invention, but should be construed as an example of a preferred embodiment.

According to the present invention, a conventional 1T-1C cell structure requires four metal lines, or in the case of a 1T-1C cell consisting of two or three metal lines, a complicated operating circuit is required. Since only three metal lines such as lines are needed, the manufacturing process is simple, and the contact voltage applied to the word line can be fixed to only positive or negative, which simplifies the operation circuit relatively.

1 is a cross-sectional view showing the structure of a conventional magnetic random access memory device.

2 is a cross-sectional view showing the structure of a magnetic random access memory device according to the present invention.

3 is an equivalent circuit diagram of an array of magnetic random access memory elements according to the present invention.

4A to 4C are structural and circuit diagrams for describing a " write " process of a magnetic random access memory device according to the present invention.

5A to 5C are structural and circuit diagrams illustrating a "read" process of a magnetic random access memory device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100 ... substrate 111 ... first impurity layer

112 second impurity layer 113 gate oxide

114 ... gate conducting layer 116a ... first via hole

116b ... the second via hole 117 ... the first interlayer insulating film

118 ... Second interlayer insulating film 119 ... Third interlayer insulating film

120a ... first conductive plug 120b ... second conductive plug

121a ... first conductive layer pattern 121b ... second conductive layer pattern

122 ... Third conductive plug 123a ... Third conductive layer pattern

123b ... the fourth conductive layer pattern 124 ... the fifth conductive layer pattern

124a ... fourth via hole 125 ... fourth interlayer insulating film

126 ... bit line 127 ... TMR element

211 ... substrate 212a ... first impurity layer

212b ... Second impurity layer 213a ... Gate conducting layer

213b ... gate insulation layer 214 ... via hole

215 ... conductive plug 216 ... first buffer layer

217 ... TMR element 218 ... second buffer layer

219 bit line 220 interlayer insulation film

221 ... plate line

Claims (9)

A MOSFET element comprising a substrate, a gate including a first impurity layer and a second impurity layer formed by doping an impurity on the substrate, and a gate conductive layer formed between the impurity layer on the substrate and a word line; A memory element formed on the first impurity layer and including a magnetic material; A bit line connected with the first impurity layer through the memory element; A plate line connected to the second impurity layer; And And an insulating layer formed between each of the components. 3. The method of claim 1, And the memory element is a GMR element or a TMR element. The method of claim 2, The TMR element is a multilayer film having an insulating layer formed between ferromagnetic layers, and includes an antiferromagnetic layer on top or bottom of the multilayer film. The method of claim 1, And a conductive plug formed between said memory element and said first impurity layer. The method of claim 4, wherein And a buffer layer formed between the conductive plug and the memory element and between the memory element and the bit line. The method of claim 1, And a gate insulating film formed between the gate conductive layer and the substrate. The method of claim 6, And a sense amplifier coupled to the plate line. A MOSFET element having a first impurity layer and a second impurity layer formed by doping an impurity in a substrate and a word line serving as a gate conducting layer, which is a word line formed between the impurity layer on the substrate; A memory element formed on the first impurity layer and including a magnetic material; A bit line connected with the first impurity layer through the memory element; A plate line connected to the second impurity layer; And In the method of operating a magnetic random access memory having only three metal lines, including; insulating layer formed between each of the components, (A) For addressing, a voltage Vb is applied to the bit line to flow a current, and a voltage Vp is applied to the plate line to flow a current in one direction, and then a resistance is formed in the memory element. Recording to data; And (B) applying a voltage Vr to the bit line for addressing, applying the word line voltage Vw to sense current flowing through the plate line and reading data according to a resistance value written in the memory element; And a method of operating a magnetic random access memory. The method of claim 8, The step (b) is characterized in that for detecting the current through the sense amplifier connected to the plate line.