KR100477526B1 - Semiconductor testing device of pogo pin - Google Patents

Abstract

The present invention relates to a pogo pin of a semiconductor test apparatus in which the pogo pin has a constant strength and can serve as an interface, and the interface pad of the test board is electrically connected to the probe by circular pogo pins vertically penetrating the block. In the pogo pin of the semiconductor test device for the characteristic test, the upper contact pin, the lower contact pin, and the upper and lower contact pins respectively contacting the test board and the probe so that the upper and lower contact pins do not go down any further when the upper and lower operations A spring, a spring for tensioning the upper and lower contact pins to be in strong contact with the test board, a metal conductor plate formed on the groove and contacting when the upper contact pin descends, and the upper and lower contact pins moving upward and downward A case for fixing the metal conductor plate and the upper contact Pin is connected to the light emitting body, wherein the metal conductive plate, indicating that the contact when the contact with the metal conductive plate and being configured to power for operating the balgwangcheeul.

Description

Pogo pin of semiconductor test device {SEMICONDUCTOR TESTING DEVICE OF POGO PIN}

The present invention relates to a pogo pin of a semiconductor test device, and more particularly to a pogo pin of a semiconductor test device capable of having a certain strength and acting as an interface.

In general, each chip on the wafer where the wafer-level manufacturing process is completed is subjected to electrical property inspection by a test facility in an electrical die sorting (EDS) process before performing the packaging process. In addition, packages that have completed the packaging process are subjected to electrical characterization by a test facility. This is to determine whether each chip or package of the wafer has been manufactured in accordance with a specific standard as a semiconductor device.

In recent years, as the integration of semiconductor devices has progressed, a probe called a pogo pin has been widely used. The block to which the pogo pin is applied electrically connects a tester (Device Under Testing) and a dirt board (or a test).

In other words, the pogo pin is a device that can be effectively separated from each other and the pad form requiring electrical connection.

Hereinafter, a pogo pin of a conventional semiconductor test apparatus will be described with reference to the accompanying drawings.

1 is a configuration diagram showing a case where the pogo pin is applied to the interface between the conventional board, Figure 2 is a configuration diagram showing a conventional pogo pin.

As shown in FIG. 1, circular pogo pins 20 penetrate vertically to the block 10. At this time, the pogo pins 20 are each inserted and fixed to the pogo pin case of the circular through shape, the pogo pin 20 is inserted into the pogo pin cases one by one correspondingly installed. The interface pad 40 of the test board 30 is electrically connected to the probe 50 by the pogo pins 20.

Here, as shown in FIG. 2, the pogo pin 20 has an upper contact pin 21, a lower contact pin 22, and the upper and lower contact pins 21, 22 contacting the upper or lower test board. A spring 24 for tensioning the groove 23 and the upper and lower contact pins 21 and 22 so as to be in strong contact with the test board so as not to move down any further during operation, and the upper and lower contact pins 21 ( It is composed of a case 25 for fixing so that 22) can move up and down.

The pogo pin operation of the conventional semiconductor test apparatus configured as described above is as follows.

When the upper contact pin 21 is pressed by the interface pad 40 of the test board 30 is supported by the spring 24 and down to make contact. In this case, the lower contact pin 22 is in contact with the probe 50.

That is, although not shown in the drawing, the contact height adjustment is performed by a bracket and a blocking optical sensor.

However, the pogo pin of the conventional semiconductor test apparatus as described above has the following problems.

When setting up the test board and the probe, the interface pad of the test board and the pogo pins in the pogo pin block must be precisely aligned. Difficult to know

An object of the present invention is to provide a pogo pin of the semiconductor test apparatus that can be contacted to the interface pad with a certain strength to all pogo pins to solve the above problems.

In order to achieve the above object, the interface pad of the test board is electrically connected to the probe by the circular pogo pins vertically penetrating the block in the pogo pin of the semiconductor test device for the property test, the present invention is An upper contact pin and a lower contact pin contacting the test board and the probe, respectively; a spring installed between upper and lower contact pins to apply tension to the upper and lower contact pins so as to strongly contact the test board; A case surrounding the upper and lower contact pins; A groove formed in the case so that the upper and lower contact pins do not go down any more when the upper and lower contact pins operate; A metal conductor plate formed on an upper portion of the groove and contacted when the upper contact pin descends; A light emitter connected to the metal conductor plate to indicate that the upper contact pin is in contact when the upper contact pin is in contact with the metal conductor plate; and a power source connected to the metal conductor plate and the light emitter to operate the light emitter, respectively. In addition, the case is preferably an insulator.

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Hereinafter, a pogo pin of the semiconductor test apparatus of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a pogo pin of a semiconductor test apparatus according to an embodiment of the present invention.

As shown in FIG. 3, the pogo pin 100 includes an upper contact pin 110 in contact with a test board, a lower contact pin 120 in contact with a probe, and upper and lower contact pins 110 and 120. A groove 130 to prevent further down when operating, a spring 140 for tensioning the upper and lower contact pins 110 and 120 to be in strong contact with the test board and the probe, and the groove 130 A metal conductor plate 150 formed at an upper side thereof and contacted when the upper contact pin 110 descends, and fixed to allow the upper and lower contact pins 110 and 120 to move up and down, and the metal conductor plate The case 160 fixing the 150 and the upper contact pin 110 are connected to the metal conductor plate 150 and the light emitter 170 indicating that the contact is made when the upper contact pin 110 is in contact with the metal conductor plate 150. The power source 180 is configured to operate the light emitter 170.

The pogo pin of the semiconductor test apparatus of the present invention configured as described above is brought down to contact the metal conductor plate 150 when the upper contact pin 110 is pressed on the interface pad of the test board. Power is continuously applied to the metal conductor plate 150 from the source 180 source, and a closed loop is formed at the moment when the upper contact pin 110 contacts, and the light emitter 170 is lit.

On the other hand, the pogo pin configured as described above is vertically penetrated up, down, left, and right of the block 200 as shown in Figure 4 so that the interface pad of the test board is electrically connected to the probe by the pogo pins (100). That is, when the pogo pin 100 configured as described in the present invention is inserted into the top, bottom, left and right of the block 200, and the rest of the pogo pins are inserted into the conventional pads and pressed in the interface pad of the test board, the light emits at the same time. Adjust until

As described above, according to the pogo pin of the semiconductor test apparatus of the present invention, the pogo pin contact invisible is also increased, and the pogo pins in the block unit can be contacted with a predetermined amount of contact pressure.

Therefore, the time required for setup can be shortened.

1 is a configuration diagram illustrating a case where a pogo pin is applied to interface between boards according to the related art.

2 is a configuration diagram showing a conventional pogo pin

3 is a block diagram illustrating a pogo pin of a semiconductor test apparatus according to an embodiment of the present invention.

4 is a plan view of a pogo pin block according to an embodiment of the present invention

<Explanation of symbols for the main parts of the drawings>

100: pogo pin 110: upper contact pin

120: lower contact pin 130: groove

140: spring 150: metal conductor plate

160 case 170 light emitter

180: power 200: block

Claims (2)

In the pogo pin of the semiconductor test apparatus for the interface test of the test board is electrically connected to the probe by the circular pogo pins vertically penetrating the block to undergo a characteristic test, Upper and lower contact pins contacting the test board and the probe, respectively; A spring installed between the upper and lower contact pins to apply tension to the upper and lower contact pins so as to strongly contact the test board; A case surrounding the upper and lower contact pins; A groove formed in the case so that the upper and lower contact pins do not go down any more when the upper and lower contact pins operate; A metal conductor plate formed on the groove and contacted when the upper contact pin descends; A light emitter connected to the metal conductor plate to indicate that the upper contact pin is in contact when the upper contact pin is in contact with the metal conductor plate; and A pogo pin of the semiconductor test apparatus, characterized in that it is composed of a power source for operating the light emitting body connected to the metal conductor plate and the light emitting body, respectively. The method of claim 1, Pogo pin of the semiconductor test device, characterized in that the case is an insulator.