KR100474525B1 - RF receiver - Google Patents

Abstract

According to the present invention, an RF receiver includes a limiter including a plurality of amplifiers arranged at a stage next to a channel selection filter and capable of varying gains, and a RSSI (Received Signal Strength Indicator) extracting a magnitude of an input signal of the limiter. In addition, the gain of the plurality of amplifiers is varied in real time by using the multi-bit signal output from the RSSI, and the gain is changed in inverse proportion to the magnitude of the input signal so that the distortion of the signal does not occur while maintaining a constant output signal size. The use of a smoothing filter reduces unnecessary current consumption and layout area.

Description

RF receiver

The present invention relates to an RF receiver, and more particularly, configured to vary the gain of an amplifier constituting the limiter, thereby changing the gain in inverse proportion to the magnitude of the input signal to maintain a constant output signal size. However, since the signal distortion does not occur, the RF receiver can reduce unnecessary current consumption and layout area by using a smoothing filter.

In general, a limiter implemented as an auto gain controller (AGC) or a multi-stage amplifier having one gain in front of a demodulator in a LOW-IF structure among RF transceiver structures. Use a circuit.

However, the automatic gain controller AGC is often difficult to implement and requires a lot of current and layout area, so it uses a lot of limiter structures that are easy to implement.

The limiter is amplified with a constant gain, regardless of the magnitude of the input signal, and clamps the analog signal for more than a certain amount of input. It is always used to send a certain amount of signal to the demodulator.

However, such a limiter structure is severely distorted, and an additional smoothing filter must be connected after the limiter. Thus, it consumes additional current and layout area.

1 is a block diagram illustrating a general RF receiver. Here, a low-IF structure will be described as an example.

The receiver uses a structure in which a limiter 2 is connected to a stage after a channel select filter 1.

The limiter 2 is implemented with the same amplifier stage in order to obtain one gain, and amplifies by the sum of gains in each amplifier regardless of the magnitude of the input signal so that the input analog signal is clamped at all times. An output signal of magnitude is output to the demodulator 3.

In addition, since the output signal clipped by the limiter 2 is amplified by a constant amplification value regardless of the magnitude of the input signal, the signal is severely clamped to a constant value. Thus, a smoothing filter 4 is connected to the output of the limiter 2 to compensate for this signal distortion.

In addition, a limiter signal (5) circuit for detecting the magnitude of the input signal is implemented in the limiter stage 2. The amplitude of the input signal extracted from each amplifier stage is extracted and the RSSI value is set to the value. .

FIG. 2 is a block diagram illustrating a detailed block of the limiter and RSSI circuit shown in FIG. 1.

The limiter 2 includes a plurality of amplifiers 6a to 6e connected in series with a constant gain, and the RSSI circuit 5 includes rectifiers 7a to 7f extracting the output magnitude of each amplifier 6a to 6e. And an RSSI encoder 8.

The input signal is an analog signal, but the output signal outputs the clamped signal, which causes severe signal distortion. Accordingly, since a smoothing filter 4 must be additionally implemented to compensate for such signal distortion, additional current consumption and layout area are required.

In addition, to extract the RSSI value, the amplitude of the input signal is estimated by comparing the signal amplified in each amplifier stage 6a to 6e of the limiter with a reference value, and the gain of each amplifier stage 6a to 6e is not constant. In this case, many errors occur and additional current consumption and layout area are required because the same rectifiers 7a to 7f must be implemented for each amplifier stage 6a to 6e.

An object of the present invention for solving the above problems, by connecting a circuit for extracting the RSSI value from the limiter input terminal, using a smoothing filter while generating a constant size output by automatically controlling the gain of the limiter using the RSSI value This reduces the current consumption and layout area.

A receiver of the present invention for achieving the above object comprises: a limiter disposed next to a channel select filter and including a plurality of amplifiers capable of varying gain; And a RSSI (Received Signal Strength Indicator) for extracting a magnitude of an input signal of the limiter and outputting a multi-bit signal that can vary each gain of the plurality of amplifiers to the limit.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating an RF receiver according to the present invention. Here, the Low-IF structure will be described as an example.

The receiver uses a structure in which the limiter 20 is connected to the stage after the channel selection filter 10. Here, the RSSI circuit 30 is connected to the front of the limiter 20.

The signal amplified to a certain size by the limiter 20 is applied to the demodulator 40.

In addition, the RSSI circuit 30 uses only one rectifier 31 and includes a comparator 32 and an encoder 33.

4 is a block diagram illustrating a detailed block of the limiter 20 and the RSSI circuit 30 of FIG. 3.

The limiter 20 includes variable gain amplifiers 21 to 24 whose gain is adjusted by the 4-bit RSSI signal RSSI <0: 3>, and the RSSI circuit 30 extracts the magnitude of the input value. RSSI signals RSSI <0: 3> are obtained by using the rectifier 31, the comparator 32 for comparing the magnitude of the input value extracted by the rectifier 31 with the reference values, and the results output from the comparator 32. And an RSSI encoder 33 for outputting.

Here, the signal RSSI <0: 3> output from the RSSI encoder 33 is applied to the resistor array of the variable gain amplifiers 21 to 24 without any other conversion to vary the gain of the amplifier. Therefore, it is possible to minimize the distortion of the signal by converting the gain in real time to the change in the magnitude of the RF input signal.

FIG. 5 is a circuit diagram illustrating a detailed circuit of the variable gain amplifier 21 of FIG. 4. Here, a structure in which the degeneration resistor of the differential amplifier is implemented as a resistor array will be described as an example.

The variable gain amplifier 21 includes a load resistor RL, an NMOS transistor NM forming an input terminal, a constant current source I, and a resistor array 25. Here, the common terminal of the load resistor RL and the drain of the NMOS transistor NM forms an output terminal.

At this time, the gain AV of the variable gain amplifier 21 can be obtained as shown in [Equation 1].

[Equation 1]

Here, the degeneration resistance value RS is a resistance value of the resistor array 25.

FIG. 6 is a circuit diagram illustrating a detailed circuit of the resistor array illustrated in FIG. 5.

The resistor array 25 is controlled by the resistors RS0 to RS4 connected in series between the two terminals A and B and the signals RSSI <0: 3> output from the RSSI circuit 30 to control the terminals of the resistors RS0 to RS4, respectively. It includes transmission gates TG1 to TG4 that selectively connect.

Therefore, the resistance value changes according to the states of the signals RSSI <0: 3> output from the RSSI circuit 30.

That is, referring to Equation 1, the total resistance value RS of the resistor array 25 is changed in inverse proportion to the gain of the variable gain amplifier 21 so as to be inversely proportional to the magnitude of the RF input signal. By changing the gain, you can always maintain a constant limiter output size.

FIG. 7 is a circuit diagram illustrating a detailed circuit of the RSSI circuit illustrated in FIG. 4.

The RSSI circuit 30 includes a rectifier 31 for extracting the magnitude of the input value, a comparator 32 for comparing the magnitude of the input value extracted by the rectifier 31 with reference values, and an output from the comparator 32. RSSI encoder 33 for outputting RSSI signals RSSI <0: 3> using the results.

The rectifier 31 includes NMOS transistors NM1 and NM2 forming parallel input terminals, a capacitor C holding a potential of the output terminal OUT, and a constant current source I connected to the output terminal OUT.

The comparator 32 includes comparators 34a, 34b, 34c, 34d, 34e, 34f, ... that compare the value output from the rectifier 31 with a plurality of reference values VREF1-VREF16.

The rectifier 31 detects the magnitude of the limiter input signal, compares this value with the sixteen reference voltages VREF1 to VREF16 and outputs a 4-bit signal RSSI <0: 3> through the encoder 33.

The signals RSSI <0: 3> output from the encoder 33 are applied to the amplifiers 21 to 24 of the limiter 20 to convert the gains of the amplifiers 21 to 24 into gains inversely proportional to the input signal.

8 is a block diagram illustrating another embodiment of an RF receiver according to the present invention. Here, an example of using an analog-digital converter (ADC) 60 in the structure including the digital demodulator 50 will be described.

When the RF receiver uses the ADC 60 in a structure including the digital demodulator 50, the limiter 20 uses the variable gain amplifiers 21 to 24 shown in FIG. 4 for the input size of the constant ADC 60. ) Is arranged next to the channel selection filter 10, and the RSSI circuit 30 extracts the magnitude of the input signal of the limiter 20.

Accordingly, the state of the resistor array 25 and the 4-bit signal RSSI <0: 3> suitable for the resolution of the input signal change required by the ADC 60 are used.

As described above, the RF receiver according to the present invention is configured to vary the gain of the amplifier constituting the limiter, and the gain is inversely proportional to the magnitude of the input signal to maintain a constant output signal size while maintaining the size of the signal. Since distortion does not occur, the smoothing filter is not required, thereby reducing unnecessary current consumption and layout area.

In addition, the RSSI circuit for detecting the magnitude of the input signal has the effect of placing only one rectifier at the limiter input stage to minimize the circuit configuration and detect the RSSI value insensitive to the gain change of the amplifier constituting the limiter.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a block diagram illustrating a typical RF receiver.

2 is a block diagram showing a detailed block of the limiter and RSSI circuit of FIG.

3 is a block diagram illustrating an RF receiver in accordance with the present invention.

4 is a block diagram showing a detailed block of the limiter and RSSI circuit of FIG.

FIG. 5 is a circuit diagram illustrating a detailed circuit of the variable gain amplifier of FIG. 4. FIG.

6 is a circuit diagram showing a detailed circuit of the resistor array of FIG.

7 is a circuit diagram illustrating a detailed circuit of the RSSI circuit of FIG. 4.

8 is a block diagram illustrating another embodiment of an RF receiver in accordance with the present invention.

Claims (4)

A limiter disposed next to the channel select filter and including a plurality of amplifiers capable of varying gain; And And an RSSI (Received Signal Strength Indicator) for extracting the magnitude of an input signal of the limiter and outputting a multi-bit signal capable of varying gains of the plurality of amplifiers to the limit. The method of claim 1, Wherein each amplifier is implemented as a differential amplifier comprising a resistor array whose degeneration resistor value is adjusted by a multi-bit signal output from the RSSI. The method of claim 2, The resistor array, Multiple resistors connected in series; And And a plurality of switch means each controlled by a multi-bit signal output from the RSSI and connected to respective terminals of the respective resistors. The method of claim 1, The RSSI, A rectifier for extracting a magnitude of an input signal of the limiter; A plurality of comparing means for comparing the value extracted from the rectifier with a plurality of reference values, respectively; And And an encoder for outputting the multi-bit signal using the result values output from the plurality of comparison means.