KR100473148B1 - Interface apparatus and method for burst mode packet transfer - Google Patents

Abstract

The present invention relates to a matching device and method for supporting packet delivery in burst mode, which is used in SPI-3 (System Packet Interface Level 3), an interface standard between a physical layer and a link layer. .

According to the present invention, a packet data transmitted from a transmitting device in a non-burst mode, a control signal including a packet start point signal, a packet end point signal, and an effective cycle indication signal are received and stored, and output to the receiving device in burst mode. A first-in, first-out buffer; While the valid cycle display signal input from the transmitting element is activated, the write enable signal of the data first-in-first-out buffer is activated to store the packet data and the control signal in the data first-in-first-out buffer, and the data first-in-first-out buffer If the storage condition of the read condition satisfies the read condition, the enable signal is activated to output the packet data and the control signal stored in the data first-in first-out buffer to the receiving device. And a FIFO control signal generator for deactivating the read enable signal when all control signals are output to the receiving device. Here, when a new trailing packet is completely input to the data first-in, first-out buffer while one packet is output and satisfies the read condition for the trailing packet, the FIFO control signal generator activates the read enable signal even if all preceding packets are output. This state is maintained so that subsequent packets are output continuously after the preceding packet.

Description

Interface apparatus and method for burst mode packet transfer

The present invention relates to a matching device and a method of a network system, and more specifically, it is used in a system packet interface level 3 (SPI-3), which is an interface standard between a physical layer and a link layer. A matching device and method for supporting packet delivery in burst mode. The present invention also provides a computer-readable recording medium having recorded thereon a program for causing a computer to execute a matching method for delivering a packet in burst mode as described above.

System Packet Interface Level 3 (SPI-3) is a standard that the Optical Internet Forum (OIF) has standardized for interfacing between physical layer and link layer elements. The parent of this SPI-3 is POS-PHY Level 3, which was first proposed by the SATURN development group and is the basis for SPI-3, as well as the frame-based ATM interface level 3 based ATM Interface Level 3).

The 2001 System Packet Interface Level 3 (SPI-3), `` Op-48 Interface for Physical and Link Layer Devices, '' published by The Optical Internetworking Forum in 2001, contains seven pages of OIF-SPI3-01.0. The SPI-3 interface reference point is defined.

1 is a diagram illustrating a reference point defined in SPI-3. It includes a communication line 11, a physical layer 13, and a link layer 15. The communication line 11 corresponds to an optical fiber, a twisted pair electrical cable, a coaxial cable, or the like. The physical layer 13 is a physical layer for packet over SONET (POS), the PMD element 12 is a layer independent from the physical medium, and the physical layer-link layer matching means 14 is linked with the physical layer 13. Define the electrical interface between layers 15. This SPI-3 specifies the physical layer-link layer matching method.

2 is a signal configuration diagram of SPI-3. SPI-3 supports an interface for performing a matching function between the physical layer element 21 and the link layer element 22. The SPI-3 uplink signal (Rx, Receive) 23, which supports the physical layer element 21 to transmit packets to the link layer element 22, and the link layer element 22 send the packet to the physical layer element 21. It consists of an SPI-3 downlink signal (Tx, Transmit) 24 that supports transmission. The SPI-3 uplink signal 23 is a received packet data RDAT (Rx Data) and a control signal Rx Control (RVAL, ROP, RSOP), which is a handshaking signal between the link layer element 22 and the physical layer element 21. REOP, etc.), and a feedback signal Rx Feedback (RENB). The SPI-3 downlink signal 24 is a packet data (TDAT; Tx Data) to be transmitted and a control signal (Tx Control; TENB, TSOP) which is a handshaking signal between the physical layer element 21 and the link layer element 22. , TEOP, etc.), and a feedback signal Tx Feedback (TPA).

The SPI-3 uplink signal 23 defined in SPI-3 is summarized in Table 1, and the SPI-3 downlink signal 24 is summarized in Table 2.

signal direction Explanation TFCLK Clock Source-> Link Clock Source-> Physical Operation Clock TERR Link-> Physics Error indication signal of currently transmitted packet TENB Link-> Physics Data transfer possible TDAT Link-> Physics Data bus TPRTY Link-> Physics Data Bus Parity Signal TMOD Link-> Physics Modulo Signals in Data Bus Words TSC Link-> Physics Indicates that data on the data bus is an in-band address TSOP Link-> Physics Indication signal of starting point of packet boundary TEOP Link-> Physics End Point Indicator of Packet Boundary TADR [] Link-> Physics Address bus of each port of physical layer device DTPA [] Physics-> Link Direct indication signal of each port of physical layer device STPA [] Physics-> Link Enable / Disable of Port Specified by In-band Address PTPA [] Physics-> Link Whether or not to listen on the port specified by TADR

signal direction Explanation RFCLK Clock Source-> Link Clock Source-> Physical Operation Clock RVAL Physics-> Link Indication of valid / invalid of received data RENB Link-> Physics Whether data can be received RDAT [31: 0] Physics-> Link Data bus RPRTY Physics-> Link Data Bus Parity Signal RMOD [1: 0] Physics-> Link Modulo Signals in Data Bus Words RSOP Physics-> Link Indication signal of starting point of packet boundary REOP Physics-> Link End Point Indicator of Packet Boundary RERR Physics-> Link Error indication signal of currently transmitted packet RSX Physics-> Link Indicates that data on the data bus is an in-band address

SPI-3 described above is a standard defined for exchanging packets of variable length between POS physical layer devices and link layer devices. Similarly, there is a standard defined for fixed-length cell delivery in Asynchronous Transfer Mode (ATM), which is Utopia Level 3 (Universal Test & Operations Physical Interface for ATM level 3). This Utopia Level 3 supports the OC-48 class of physical layers and is defined in the ATM Forum for the delivery of fixed-length cells between physical and ATM layers.

3 is a signal configuration diagram of utopia level 3. Utopia level 3 performs a matching function between the physical layer element 31 and the ATM layer element 32, and the utopia uplink signal for supporting the physical layer element 31 to transmit the ATM cell to the ATM layer element 32. Rx, Receive) 33 and a Utopia downlink signal (Tx, Transmit) 34 that supports the ATM layer element 32 to transmit ATM cells to the physical layer element 31. The utopia uplink signal 33 is a received ATM cell data (Rx Data) and a control signal (Rx Control; RxAddr, RxClav, RxEnb, RxSOC) which is a handshaking signal between the physical layer element 31 and the ATM layer element 32. And the like). The utopia downlink signal 34 is an ATM cell data (Tx Data) to be transmitted and a control signal (Tx Control; TxAddr, TxClav, TxEnb, which is a handshaking signal between the physical layer element 31 and the ATM layer element 32). TxSOC, etc.).

Both SPI-3 and Utopia Level 3 described above define the interface between the physical layer and the link layer. While SPI-3 does not require burst mode packet delivery, Utopia Level 3 requires Burst Mode Cell Transfer, a continuous data transfer method, compared to SPI-3.

4 is a timing diagram of each signal when a physical layer device delivers a cell in burst mode to an ATM layer device according to the Utopia Level 3 interface standard. The physical layer device transmits an ATM cell to the ATM layer device using a utopia received signal, which includes an operation clock (RxClk) 31, an ATM cell data (Rx Data) 34, and a cell of the physical layer device. An RxClav signal 32 indicating whether there is a cell to be transmitted in the buffer, an RxEnb signal 33 indicating whether the ATM layer element can receive data, and an RxSOC signal 35 indicating a cell boundary start point are included.

In the Utopia level 3, when a physical layer device delivers an ATM cell to an ATM layer device, it first notifies the ATM layer device that the physical layer device is ready to deliver one or more complete ATM cells, and the ATM layer device receives the ATM cell. The physical layer device should be informed that it is ready to do so. Referring to the timing diagram of FIG. 4, the physical layer element transmits an RxClav signal 32 to the ATM layer element in an active state to indicate that there is an ATM cell to transmit. The ATM layer element then sends an RxEnb signal 44 in an active state to inform the physical layer element whether the ATM cell can be received. While one ATM cell is transferred from the physical layer element to the ATM layer element, the physical layer element keeps the RxClav signal high to notify the ATM layer element if there is a cell to send immediately after.

Referring to FIG. 4, the physical layer device sets the RxClav signal 32 to an active high state from the seventh rising edge of the RxClk operation clock 31 to notify the ATM layer device that there is a subsequent cell, and the ATM layer device RxEnb. The physical layer device is notified that the signal 33 can be brought into an active low state to receive a cell. Therefore, the last data of the cell is transmitted at the 10th clock of the RxClk operation clock 31, and then the header of the next transmission cell is transmitted at the 11th clock. At this time, the RxSOC signal 35 becomes the active high state to indicate that the start point of the cell. As shown in FIG. 4, Utopia Level 3 supports a burst mode for continuously transmitting cells.

Since SPI-3 and Utopia Level 3 are not intended to be compatible with each other and as described above, Burst Mode, which is not required by SPI-3, is required in Utopia Level 3, so compatibility between the two is not possible.

However, sometimes it is required to follow the SPI-3 standard additionally in burst mode, i.e., to deliver packet data continuously. For example, physical layer devices and link layer devices currently on the market may be mixed with Utopia level 3 and SPI-3 in order to accommodate various services on the same chip. In addition to following the SPI-3 standard, there may be additional requirements for burst mode delivery of packets. When implementing the burst mode transfer request of such a packet, if the physical layer device only complies with the SPI-3 standard and only the link layer device requires the packet forwarding in burst mode, the packet cannot be transferred between the two devices. Similarly, if the link layer device follows only the SPI-3 standard and only the physical layer device requires packet forwarding in burst mode, no packet forwarding can occur between these two devices.

Thus, when one device does not support burst mode and the other device requires packet delivery in burst mode, a matching method is required to match packet delivery in burst mode between two devices.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems of the prior art is to burst between a device that does not support burst mode packet delivery while following the SPI-3 standard and a device that requires burst mode packet delivery while following the SPI-3 standard. It is an object of the present invention to provide a matching device and a method for interfacing a packet forwarding mode.

The matching device for burst mode packet delivery according to the present invention for achieving the above object, converts the packet input from the transmitting element that does not support the packet delivery in burst mode to burst mode to transfer the packet in burst mode In the matching device for outputting to the receiving element,

Data first-in, first-out that receives and stores the packet data transferred from the transmitting device in a non-burst mode, and a control signal including a packet start point signal, a packet end point signal, and an effective cycle indication signal, and outputs the burst data to the receiving device in burst mode. A buffer;

While the valid cycle display signal input from the transmitting element is activated, the write enable signal of the data first-in-first-out buffer is activated to store the packet data and the control signal in the data first-in-first-out buffer, and the data first-in-first-out buffer If the storage condition of the read condition satisfies the read condition, the enable signal is activated to output the packet data and the control signal stored in the data first-in first-out buffer to the receiving device. A FIFO control signal generator for deactivating the lead enable signal when all control signals are output to the receiving device;

Detecting the end point of the packet output from the data first-in first-out buffer to the receiving device before N (N is an arbitrary natural number) cycle, and outputs the activated EOP notice signal to the FIFO control signal generation unit, the FIFO control signal It characterized in that the generation unit has an EOP notice means for accurately identifying the end point of the packet output from the data first-in, first-out buffer to the receiving element.

In addition, the matching method for burst mode packet delivery according to the present invention, to a receiving device that converts the packet input from the transmitting device that does not support the packet delivery to the burst mode to the burst mode to request the packet delivery to the burst mode In the matching method to output,

When the control element including the packet data in the non-burst mode, the packet start point signal, the packet end point signal, and the valid cycle display signal is input from the transmitting element, the packet is input to the data first-in-first-out buffer while the valid cycle display signal is activated. A data storage step of storing data and control signals;

Stores the packet endpoint signal of the packets continuously input from the transmitting element, the packet endpoint of the remaining valid cycle except for the N valid cycles after the N (N is an arbitrary natural number) valid cycle of the first input packet An EOP storage step of storing a signal in an EOP first-in, first-out buffer;

If the storage condition of the data first-in-first-out buffer satisfies the read condition, the read enable signal of the data first-in-first-out buffer and the EOP first-in-first-out buffer is activated to transmit packet data and control signals stored in the data first-in-first-out buffer to the receiving device. Outputting a data output step;

An EOP preliminary step of recognizing in advance that an EOP of the packet is output from the data first-in, first-out buffer after N cycles when the packet end signal output from the EOP first-in, first-out buffer is activated;

And a data output stop step of deactivating a read enable signal of the data first-in-first-out buffer when all packet data and control signals for one packet are output from the data first-in-first-out buffer.

According to the present invention, there is also provided a computer-readable recording medium having recorded thereon a program for executing a matching method for burst mode packet delivery as described above in a computer.

Hereinafter, a "matching device and method for burst mode packet transfer between a physical layer and a link layer" according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The matching method according to the present invention may be variously applied to programmable devices such as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). In order to more easily describe the present invention, some of the timing diagrams in the accompanying drawings are shown in a method-centric manner without considering the flow of time that would appear in actual implementation.

According to the present invention, there are two situations in which the physical layer device does not support burst mode transfer, but the link layer device requires burst mode transfer, and the physical layer device requires burst mode transfer, but the link layer device does not support burst mode transfer. If not supported, all can be applied. However, in the present embodiment, the above-described case, that is, the physical layer device does not support burst mode transfer, but the link layer device requires burst mode transfer as an example. That is, in the present embodiment, a matching device receives a packet not transmitted in the burst mode from the physical layer device, converts it into the burst mode, and transmits the packet to the link layer device as an example.

5 is a block diagram of a basic reference model including a matching device proposed in the present invention. A matching device according to the present invention is inserted between the physical layer element and the link layer element.

6 is a timing diagram of an input signal of a matching device according to an embodiment of the present invention, and FIG. 7 is a timing diagram of an output signal of a matching device according to an embodiment of the present invention. The physical layer device outputs a signal as shown in FIG. 6 to transmit packet data to the link layer device, which is input to the matching device. The signal input from the physical layer device to the matching device includes an RVAL signal indicating valid / invalidity of received data, transmission packet data (RxData), an RSOP signal indicating a start point of a packet boundary, and an end point of a packet boundary. A REOP signal is included, wherein the link layer device outputs a RENB signal indicating whether data can be received from the matching device.

The transmission packet data input to the matching device is a signal that does not support the burst mode, and the matching device converts the input packet data into the burst mode and outputs it to the link layer element. The signal output to the link layer device by the matching device includes an RVAL signal indicating whether the received data is valid or invalid, transmission packet data (RxData), an RSOP signal indicating the start of the packet boundary, and an end point of the packet boundary. REOP signal is included. The matching device provides a RENB signal to the physical layer device indicating whether data received from the link layer device can be received.

6 and 7, the start point of the packet boundary in FIG. 6 is the first rising edge of the operation clock RFCLK, and the end point is the 14th rising edge of the operation clock RFCLK. Because SPI-3 does not require burst mode transfer, there may be cycles where data is not valid, such as the fifth, ninth, and tenth clocks. When the invalid data is input, as shown in FIG. 6, the RVAL signal transitions to a low state, so that the matching device detects invalid data, excludes invalid cycles in the middle of the packet, and then invalid cycles from the first data to the last data in the packet. To the link-layer device in burst mode.

A matching device for performing the above functions is shown in FIG. Referring to FIG. 8, the matching device according to the present invention includes a physical layer matching unit 811, a control-data first-in first-out buffer (hereinafter referred to as a first FIFO) 812, a signal reproducing unit 813, and a buffer. A buffer 814, a link layer matching unit 815, a FIFO control signal generator 816, an end of packet (FIOP) -FIFO (hereinafter referred to as a second FIFO) 817, and an EOP detector 818 ) Is included. Since the matching device according to the present invention matches between the physical layer device that does not support the burst mode and the link layer device that requires the burst mode, the drawing further shows that it is in an upward (Rx) direction.

The physical layer matching unit 811 performs an electrical matching function with the physical layer device, receives an operation clock RFCLK from a clock source, and transmits a valid / invalid signal RVAL of data from the physical layer device. The packet data RxData, the start point signal RSOP of the packet boundary, the end point signal REOP of the packet boundary, the parity signal RPRTY for the data bus, and the word unit modulo signal RMOD of the data bus Receive input. Then, a RENB signal indicating whether or not reception from the link layer element is received is output to the physical layer element.

The first FIFO 812 stores control signals and packet data of valid cycles input through the physical layer matching unit 811 under the control of the FIFO control signal generator 816. The FIFO control signal generator 816 outputs a RVAL signal indicating whether the input data is valid or invalid as the write enable signal FIFO_1_WR_EN to the first FIFO 812, and outputs the RVAL signal when the write enable signal is active high. The 1FIFO 812 stores control signals and packet data input through the physical layer matching unit 811.

The FIFO control signal generator 816 outputs the read enable signal FIFO_1_RD_EN to the first FIFO 812 in an active state when a predetermined condition is reached. The first FIFO 812 then outputs the stored control signal and packet data to the signal reproducing unit 813 in burst mode. The signal reproducing unit 813 receives a control signal and packet data from the first FIFO 812, converts the signal into a signal for transmission to the link layer device, and outputs the converted signal. The buffer buffer 814 temporarily stores the packet data to be output to the link layer device and a control signal when a RENB signal indicating that packet data cannot be received from the link layer device is input. Data and control signals are transmitted to the link layer device.

The EOP-FIFO (second FIFO) stores the EOP signal input from the physical layer matching unit 811. The EOP detector 818 detects the REOP of the packet stored in the first FIFO 812 and output in the burst mode, a few cycles before the REOP of the packet, and outputs it to the FIFO control signal generator 816. Then, the FIFO control signal generator 816 deactivates the read enable signal provided to the first FIFO 812 so that the first FIFO 812 can no longer output data to the signal reproducing unit 813.

9 is an operation timing diagram of a FIFO control signal generator according to an embodiment of the present invention, FIG. 10 is an operation timing diagram of a signal reproducing unit according to an embodiment of the present invention, and FIG. 11 is an embodiment of the present invention. Fig. 1 shows the operation timing of the buffer buffer. Hereinafter, the present invention will be described in more detail with reference to the configuration diagram of FIG. 8 and the operation timing diagrams of FIGS. 9 to 11.

First, an operation timing diagram of the FIFO control signal generator shown in FIG. 9 will be described. The RFCLK signal is an operation clock, and the RENB signal is a signal output from the link layer element to the physical layer element, and outputs an active low RENB signal to the matching device in a state in which the link layer element can be received. The matching device may know whether the link layer device can be received by looking at the state of the RENB signal.

The RVAL signal is a signal output from the physical layer device to the link layer device, and indicates whether data of a corresponding cycle is valid. Since the physical layer device does not support burst mode, an invalid cycle may exist during the transmission of a packet. The physical layer device matches an active high state if the cycle is valid and an inactive (low level) RVAL signal if the cycle is valid. To the device. The FIFO control signal generator 816 of the matching device outputs this RVAL signal to the first FIFO 812 as a write enable signal FIFO_1_WR_EN. Since the first FIFO 812 stores the packet data and the control signal input through the physical layer matching unit 811 when the FIFO_1_WR_EN signal is in an active high state, the first FIFO 812 does not store the data when the FIFO_1_WR_EN signal is active. Only packet data and control signals of valid cycles are stored.

The RDAT_a signal is packet data input through the physical layer matching unit 811. This embodiment exemplifies a state in which two packets P1 to P7 and Q1 to Q5 are continuously input. There is an invalid cycle while one packet is being entered.

The RSOP_a signal is a packet start point signal input through the physical layer matching unit 811 and is input in an active high state in the first cycle in which each packet is input. The REOP_a signal is a packet endpoint signal input through the physical layer matching unit 811 and is input in an active high state at the end of each packet.

The FIFO_2_DEPTH signal is depth information of the effective number of cycles stored in the second FIFO 817, which is depth information (FIFO_1_DEPTH) of the effective cycle number stored in the first FIFO 812, which will be described later, and effective to be erased. The DEL_CNT signal indicating the number of cycles, the DEL signal indicating the effective cycle to be erased, and the FIFO_2_WR_EN signal for recording the effective number of cycles in the second FIFO 817 are used. The FIFO control signal generator uses the signals described above. A function of informing the first FIFO by finding the REOP of the packet in advance before an end point of one packet (packet read from the first FIFO) in the burst mode output from the first FIFO 812 to the signal reproducing unit 813. do. The reason for knowing in advance the REOP of the packet output to the signal reproducing section and the method of finding out in advance will be described later.

The FIFO_1_DEPTH signal is depth information of the number of valid cycles stored in the first FIFO 812. This increases by one when a valid cycle is written one cycle and decreases by one when a valid cycle is read one cycle. If a valid cycle is written one cycle and at the same time another cycle is read, the value does not change and does not change even when an invalid cycle is input.

The DEL_CNT signal operates when new packet data is input in the state where there is no packet data in the first FIFO 812. The DEL_CNT signal indicates how many valid cycles are deleted from the valid cycles recorded in the second FIFO 817. As shown in FIG. 9, if the DEL_CNT signal is 1, this means that one valid cycle is deleted from the number of valid cycles recorded in the second FIFO 817. If the DEL_CNT signal is 2, two valid cycles are deleted from the number of valid cycles recorded in the second FIFO 817.

The write enable signal FIFO_1_WR_EN of the first FIFO 812 is a signal output from the FIFO control signal generator 816 to the first FIFO 812. The first FIFO 812 may receive a physical signal when the FIFO_1_WR_EN signal in an active high state is received. The packet data and the control signal input through the layer matching unit 811 are stored. As described above, when the packet data and the control signal are stored in the first FIFO 812, the FIFO_1_DEPTH increases by one.

The DEL signal is a signal indicating a valid cycle to be deleted among the valid cycles recorded in the second FIFO 817. As shown in FIG. 9, when the DEL_CNT signal is 1, the DEL signal becomes active low for one cycle after the first valid cycle of the first packet has passed. If the DEL_CNT signal is 2, the DEL signal will be active low for two cycles after the second valid cycle of the first packet. In general terms, if the DEL_CNT signal is N, the DEL signal becomes active low for N cycles after the Nth valid cycle of the first packet, in which case, the read from the first FIFO 812 is performed. The REOP of a packet to be known can be known in advance N cycles.

The FIFO_2_WR_EN signal is obtained by performing a logical AND operation on the FIFO_1_WR_EN signal and the DEL signal, and is provided to the second FIFO 817. If the FIFO_2_WR_EN signal is in the active high state, the second FIFO 817 stores the end point signal REOP of the packet among control signals input from the physical layer matching unit. Since N valid cycles are not stored in the second FIFO 817 after the Nth valid cycle, FIFO_1_DEPTH and FIFO_2_DEPTH differ from N after the Nth valid cycle. In the embodiment of Fig. 9, since N is 1, the storage DEPTH of the two FIFOs differs by one.

The EOP_CNT signal counts the endpoint signal (REOP) signal of the packet input from the physical layer matching unit, and this means the number of packets continuously transmitted so far.

The FIFO_1_RD_EN signal is a lead enable signal provided to the first FIFO 812. The FIFO control signal generator 816 transitions the lead enable signal of the first FIFO 812 to an active high state when a certain condition is satisfied. When the FIFO_1_RD_EN signal becomes active high, the 1FIFO 812 outputs the packet data and the control signal stored in the first FIFO 812 to the signal reproducing unit 813. The FIFO_1_RD_EN signal is the same as the lead enable signal FIFO_2_RD_EN of the second FIFO 817. The second FIFO 817 outputs the REOP signal of the packet stored when the FIFO_2_RD_EN signal is active high to the REOP detector 818. do. Since one valid cycle is excluded when the REOP signal is input to the second FIFO 817, the REOP signal of the packet output from the second FIFO 817 is one cycle ahead of the REOP signal output from the first FIFO 812. The REOP signal output from the second FIFO 817 becomes the REOP notice signal of the packet read from the first FIFO 812.

The RDAT_b signal is packet data output from the first FIFO 812 to the signal reproducing unit 813. The RDAT_b signal is output in burst mode because there is no invalid cycle in the middle of the packet.

The EOP_OUT_INFO signal is a REOP notice signal input from the EOP detector 818, which informs the REOP of packet data currently output by the first FIFO 812 to the signal reproducing unit 813 before N cycles. In the embodiment of Fig. 9, since N is 1, the REOP of the packet is predicted in advance before one cycle of the packet being read.

The matching device of the present invention stores the packet data and the control signal inputted from the physical layer device in the effective cycle in the first FIFO 812, and the packet data stored in the first FIFO 812 if a certain read condition is satisfied. The control signal is transmitted to the link layer device. When all packets are delivered, the operation of reading the packet data and the control signal from the first FIFO 812 is terminated, and the packets are sent to the link layer device in burst mode. To pass.

For this purpose, it is very important to define the read condition and the read end condition. Read conditions are: first, when one or more packets are completely stored in the first FIFO (when an active REOP signal is stored in the first FIFO); and second, when one or more complete packets are not stored in the first FIFO, but a threshold is achieved. This is the case where packet data of the above cycle is stored in the first FIFO. At this time, the threshold is the maximum value of the total number of invalid cycles that can occur between the start point and the end point of a packet. For example, in the case of the first packet, the total is 1 because the 5th cycle is an invalid cycle, and the total is 1 because the cycles of the 13th, 14, 15, 17, and 18 cycles are invalid for the second packet. Is 5, in which case the maximum of the sum will be 5. Thus, the threshold can be set to a value greater than or equal to this maximum value. In practice, the maximum value of the sum of these invalid cycles is always present, which is actually a very small value compared to the maximum packet size. Therefore, reading the packet under the second condition can reduce the amount of storage space required while ensuring continuous delivery of the packet.

9 illustrates an example in which a first read condition is satisfied. That is, since the REOP signal indicates the end point of the packet, when one or more packets are completely stored in the first FIFO 812, corresponding packet data and control signals are read to the signal reproducing unit 813.

On the other hand, the read termination condition is when one packet is completely read in the first FIFO 812. That is, if the read condition is satisfied, the FIFO control signal generation unit 816 outputs the first FIFO read enable signal in an active high state, and when the read end condition is reached, that is, one packet is read, the first FIFO read enable is enabled. The signal must be deactivated so that no further packet data and control signals can be read. Of course, if one or more complete packets are stored in the first FIFO 812 while one packet is read, and the read condition is satisfied, the FIFO control signal generation unit 816 maintains the first FIFO read enable signal in an active state. Allow packets to be read continuously.

In general, when implementing a FIFO control signal generator with a programmable device such as a real FPGA or CPLD, the counter is incremented when the cycle in which the REOP is active is stored in the first FIFO 812, and the counter is decreased when the cycle in which the REOP is active is output. It will detect how many packets are stored in the first FIFO 812 at each moment.

Therefore, when the REOP of the packet read from the first FIFO 812 is output and the first FIFO read enable signal is transitioned to the inactive state, the counter is decremented when the REOP is output from the first FIFO 812. In this case, since the first FIFO enable signal is transitioned to an inactive state, it takes many clock cycles to deactivate the first FIFO read enable signal after the REOP is output, which causes data and control of the next packet continuously input. There is a situation that leads to a signal.

Therefore, when any one packet is read in the first FIFO 812, it is necessary to know in advance that the REOP of the packet is output before the REOP of the packet is output from the first FIFO 812. To this end, the present invention includes an EOP-FIFO (second FIFO) 817 and an EOP detector 818. The present invention can obtain the REOP notice signal (EOP_OUT_INFO) before N cycles before the REOP of the packet is output. In this embodiment, when N is 1, that is, the REOP notice signal is output one cycle before the REOP of the packet is output. An example will be described.

The second FIFO 817 receives and stores a REOP signal when the FIFO_2_WR_EN signal is in an active high state. The FIFO_2_WR_EN signal is a signal obtained by multiplying the FIFO_1_WR_EN signal by the DEL signal. That is, the second FIFO 817 stores REOP signals of consecutively input packets, but stores REOP signals of remaining valid cycles except for one valid cycle after the first valid cycle of the first input packet. Here, the packet is continuously input means that a new trailing packet is input before all packets stored in the first FIFO are read and the first FIFO is empty.

The REOP signal stored in the second FIFO 817 is one cycle less than the REOP signal stored in the first FIFO 812. Physical representations of these are FIFO_1_DEPTH and FIFO_2_DEPTH, which differ by one in the number of valid cycles stored in the two FIFOs. Here, in order for the REOP notice signal to be N cycles ahead of the REOP signal, it is necessary to exclude N valid cycles after the Nth valid cycle of the first packet.If the exclude operation is performed before the Nth valid cycle is stored in the two FIFOs, the preceding packet is excluded. The REOP information of a packet continuously input to the data of the result indicates that the REOP notice signal is output before N cycles.

When the read condition is satisfied, the FIFO control signal generator 816 outputs a read enable signal to the first FIFO 812 and the second FIFO 817 in an active state. Then, the first FIFO 812 outputs the stored packet data and the control signal (including the EOP signal) to the signal reproducing unit 813, and the second FIFO 817 transmits the stored REOP signal to the EOP detector 818. Output In FIG. 9, seven valid cycles are stored in the first FIFO 812 and six valid cycles are stored in the second FIFO 817, and two FIFOs 812 and 817 are simultaneously read and stored in the second FIFO 817. The REOP signal is activated one cycle earlier than the REOP signal stored in the first FIFO 812.

When the REOP signal output from the second FIFO 817 becomes active high, the EOP detector 818 outputs a REOP notice signal EOP_OUT_INFO to the FIFO control signal generator 816. That is, the REOP notice signal is output one cycle before the REOP signal of the first FIFO 812, and the FIFO control signal generator 816, when the REOP notice signal is activated, after one cycle the first FIFO 812 and the second FIFO ( The lead enable signal of 817 is shifted to an inactive state. In the last cycle, since the last packet data and the REOP signal are read from the first FIFO, and the first valid cycle of consecutive packets is output from the second FIFO, the REOP notice signal is also a REOP signal even when the consecutive packets are read in burst mode. It is activated one cycle earlier.

The signal reproducing unit 813 receives the packet data and the control signal from the first FIFO 812 and converts the packet data and the control signal into a control signal for output to the link layer element. That is, referring to FIG. 10, the signal reproducing unit 813 includes the packet data FIFO_OUT_DATA, the packet start point signal FIFO_OUT_RSOP, and the packet when the read enable signal RD_EN of the first FIFO is active high. The endpoint signal FIFO_OUT_REOP and the valid cycle indication signal FIFO_OUT_RVAL are input as shown in FIG. When the read enable signal RD_EN of the first FIFO transitions from the active high state to the low level of the inactive state, the first FIFO 812 stops the output and maintains the last output state. That is, the FIFO_OUT_REOP signal and the FIFO_OUT_RVAL signal output from the first FIFO remain high even when no data is output. This does not meet the SPI-3 requirement that only one valid clock cycle is output in the active high state. Accordingly, the signal reproducing unit 813 reproduces the REOP signal having a length of 1 cycle with reference to the read enable signal RD_EN of the first FIFO and the end point signal FIFO_OUT_REOP of the packet. The RVAL signal also transitions to the low state when all the packet data is output and the REOP signal transitions from the active high state to the low level of the inactive state. In this case, the reason for referring to both the RD_EN signal and the FIFO_OUT_REOP signal is that the RD_EN signal is continuously output at the packet boundary when two packets are continuously output.

While packet data output from the physical layer element is transmitted to the link layer element via the matching device, when no further packet can be received due to the internal condition of the link layer element, the link layer element moves the RENB signal from the low state to the high state. Transitions prevent further packets from being received. The RENB signal is transmitted to the FIFO control signal generator 816 and the physical layer matching unit 811. The physical layer matching unit 811 transfers the RENB signal to the physical layer device, and the FIFO control signal generator 816. ) Drives the buffer buffer 814 to temporarily store the packet data and the control signal output from the signal reproducing unit 813.

Referring to FIG. 11, when the lead enable signal RD_EN input from the FIFO control signal generator 816 transitions to an active high state, the buffer buffer 814 receives packet data input from the signal reproducing unit 813 ( The RDAT_c, the start point signal RSOP_c of the packet, the end point signal REOP_c of the packet, and the valid cycle indication signal RVAL_c are transmitted to the link layer matching unit 815.

Then, when the RENB signal input from the link layer element transitions from the low state to the high state, the FIFO control signal generator 816 recognizes that the link layer element can no longer receive packet data, and buffer buffer 814. The read enable signal RD_EN outputs to < RTI ID = 0.0 > Then, the buffer buffer 814 stops outputting the packet data and the control signal. Then, when the RENB signal input from the link layer device transitions to the low state again, the FIFO control signal generator 816 transitions the read enable signal RD_EN back to the high state, where the buffer buffer is configured to control the packet data and the control signal. Continue to print This buffer buffer has a size of 256 bytes as recommended by SPI-3.

Until now, the configuration and operation of a matching device for matching uplink signals between a physical layer device not supporting burst mode and a link layer device requiring burst mode have been described. As described above, the present invention can also be applied to a device for matching down signals between a link layer element not supporting a burst mode and a physical layer element requiring a burst mode. In this case, TENB is removed instead of the RVAL of the upstream signal. It is possible to use it as a write enable signal of 1FIFO and use TPA as a reception signal of the buffer buffer instead of RENB of the upstream signal. Apparatus and method for matching downlink signals using the present invention can be easily implemented by anyone skilled in the art to which the present invention pertains, and a detailed description thereof will be omitted.

While the invention has been described above based on the preferred embodiments thereof, these embodiments are intended to illustrate rather than limit the invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments can be made without departing from the spirit of the invention. Therefore, the protection scope of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.

As described above, the present invention enables packet delivery in burst mode while using less storage space between a device that conforms to the SPI-3 standard and does not support burst mode and a device that conforms to the SPI-3 standard and requires burst mode. It can work.

1 is a configuration diagram showing a reference point defined in the SPI-3 standard,

2 is a signal configuration diagram of the SPI-3 standard;

3 is a signal configuration diagram of the Utopia Level 3 standard,

4 is a timing diagram of each signal when a physical layer device delivers a cell in burst mode to an ATM layer device according to the Utopia Level 3 interface standard;

5 is a basic reference model configuration diagram including a matching device proposed in the present invention,

6 is a timing diagram of an input signal of a matching device according to an embodiment of the present invention;

7 is a timing diagram of an output signal of a matching device according to an embodiment of the present invention;

8 is an internal configuration diagram of a matching device according to an embodiment of the present invention;

9 is an operation timing diagram of an input / output signal of a FIFO control signal generator according to an embodiment of the present invention;

10 is an operation timing diagram of a signal reproducing unit input / output signal according to an embodiment of the present invention;

11 is an operation timing diagram of a buffer buffer input / output signal according to an embodiment of the present invention.

※ Explanation of code about main part of drawing ※

811: physical layer matching unit 812: control-data FIFO (first FIFO)

813: signal reproducing unit 814: buffer buffer

815: link layer matching unit 816: FIFO control signal generation unit

817: EOP-FIFO (second FIFO) 818: EOP detector

Claims (13)

A matching device for converting a packet input from a transmitting device that does not support packet delivery in burst mode into a burst mode and outputting the packet to a receiving device requiring packet delivery in burst mode. Data first-in, first-out that receives and stores the packet data transferred from the transmitting device in a non-burst mode, and a control signal including a packet start point signal, a packet end point signal, and an effective cycle indication signal, and outputs the burst data to the receiving device in burst mode. A buffer; While the valid cycle display signal input from the transmitting element is activated, the write enable signal of the data first-in-first-out buffer is activated to store the packet data and the control signal in the data first-in-first-out buffer, and the data first-in-first-out buffer If the storage condition of the read condition satisfies the read condition, the enable signal is activated to output the packet data and the control signal stored in the data first-in first-out buffer to the receiving device. A FIFO control signal generator for deactivating the lead enable signal when all control signals are output to the receiving device; Detecting the end point of the packet output from the data first-in first-out buffer to the receiving device before N (N is an arbitrary natural number) cycle, and outputs the activated EOP notice signal to the FIFO control signal generation unit, the FIFO control signal And an EOP predicting means for generating a generator to accurately recognize an end point of a packet output from the data first-in-first-out buffer to the receiving element. The method of claim 1, wherein the EOP notification means, Under the control of the FIFO control signal generation unit, the packet end signal of the packets continuously inputted from the transmitting element is stored, and N valid after N (N is an arbitrary natural number) valid cycle of the first input packet. An EOP first-in, first-out buffer that stores the packet end signal of the remaining valid cycle except for cycles and outputs the stored packet end point signal to the rear end while packet data and a control signal are output from the data first-in first-out buffer to the receiving device; When the packet end point signal output from the EOP first-in, first-out buffer is activated, activates the EOP notice signal output to the FIFO control signal generation unit, and then EOP detection for notifying that the EOP of the packet is output from the data first-in, first-out buffer after N cycles. Matching device for burst mode packet delivery, characterized in that it comprises a unit. The matching device of claim 1, wherein the read condition is a state in which an activation cycle of at least one packet endpoint signal is stored in the data first-in, first-out buffer. The method of claim 1, wherein the read condition is a state in which packet data of a cycle greater than or equal to a threshold is stored in the data first-in, first-out buffer, and the threshold is a maximum value of a total of invalid cycles that may occur between a start point and an end point of an arbitrary packet. Matching device for burst mode packet transmission, characterized in that. The method of claim 1, wherein the FIFO control signal generation unit, While the packet data and the control signal for the packet are output from the data first-in-first-out buffer to the receiving element, when a new trailing packet is stored in the data first-in-first-out buffer and the read condition for the subsequent packet is satisfied, the preceding packet is satisfied. Even if both the packet data and the control signal is output to the receiving element, the burst enable packet transmission, characterized in that to maintain the activation state without deactivating the read enable signal to output the packet data and the control signal of the subsequent packet Matching device. The apparatus of claim 1, further comprising a signal reproducing unit configured to receive the packet data and the control signal output from the data first-in, first-out buffer, convert the packet data into signals matched with the receiving device, and output the converted signal to the receiving device. Matching device for mode packet delivery. According to claim 1, When the reception signal is received from the receiving element under the control of the FIFO control signal generation unit to temporarily store the packet data and the control signal input from the data first-in, first-out buffer, the reception possible signal from the receiving element And a buffer buffer for outputting packet data and control signals inputted from the data first-in, first-out buffer to the receiving device under control of the FIFO control signal generator. . A matching method for converting a packet input from a transmitting device that does not support packet delivery in burst mode into a burst mode and outputting the packet to a receiving device requesting packet delivery in burst mode. When the control element including the packet data in the non-burst mode, the packet start point signal, the packet end point signal, and the valid cycle display signal is input from the transmitting element, the packet is input to the data first-in-first-out buffer while the valid cycle display signal is activated. A data storage step of storing data and control signals; Stores the packet endpoint signal of the packets continuously input from the transmitting element, the packet endpoint of the remaining valid cycle except for the N valid cycles after the N (N is an arbitrary natural number) valid cycle of the first input packet An EOP storage step of storing a signal in an EOP first-in, first-out buffer; If the storage condition of the data first-in-first-out buffer satisfies the read condition, the read enable signal of the data first-in-first-out buffer and the EOP first-in-first-out buffer is activated to transmit packet data and control signals stored in the data first-in-first-out buffer to the receiving device. Outputting a data output step; An EOP preliminary step of recognizing in advance that an EOP of the packet is output from the data first-in, first-out buffer after N cycles when the packet end signal output from the EOP first-in, first-out buffer is activated; And a data output stop step of deactivating a read enable signal of the data first-in-first-out buffer when all packet data and control signals for one packet are output from the data first-in-first-out buffer. Matching method for packet delivery. 10. The matching method of claim 8, wherein the read condition in the data output step includes storing activation cycles of at least one packet end signal in the first-in, first-out buffer. 9. The method of claim 8, wherein the read condition in the data output step is a state in which packet data of a cycle equal to or greater than a threshold is stored in the data first-in, first-out buffer, and the threshold is an invalid cycle that may occur between a start point and an end point of an arbitrary packet. Matching method for burst mode packet delivery, characterized in that the maximum value of the sum total. The method of claim 8, wherein the data output stop step, While all packet data and control signals for one packet are output from the data first-in-first-out buffer to the receiving element, when a new trailing packet is stored in the data first-in-first-out buffer and the read condition for the subsequent packet is satisfied. A matching method for burst mode packet delivery, characterized in that the activation state is maintained without deactivating the read enable signal even when both the packet data and the control signal of the preceding packet are output to the receiving element. 9. The burst mode of claim 8, further comprising a signal reproducing step of converting the packet data and the control signal output from the data first-in, first-out buffer into signals matched to the receiving device and outputting the same to the receiving device. Matching method for packet delivery. On your computer, When the control element including the packet data of the non-burst mode, the packet start point signal, the packet end point signal, and the valid cycle display signal is input from the transmitting element, the packet data is input to the data first-in-first-out buffer while the valid cycle display signal is activated. A data storage step of storing a control signal; Stores the packet endpoint signal of the packets continuously input from the transmitting element, the packet endpoint of the remaining valid cycle except for the N valid cycles after the N (N is an arbitrary natural number) valid cycle of the first input packet An EOP storage step of storing a signal in an EOP first-in, first-out buffer; If the storage condition of the data first-in-first-out buffer satisfies the read condition, the read enable signal of the data first-in-first-out buffer and the EOP first-in-first-out buffer is activated to transmit packet data and control signals stored in the data first-in-first-out buffer to the receiving device. Outputting a data output step; An EOP preliminary step of recognizing in advance that an EOP of the packet is output from the data first-in, first-out buffer after N cycles when the packet end signal output from the EOP first-in, first-out buffer is activated; When all packet data and a control signal for one packet are output from the data first-in-first-out buffer to the receiving device, a burst mode packet transfer including a data output stop step of deactivating a read enable signal of the data first-in-first-out buffer. A computer readable recording medium having recorded thereon a program for executing the matching method.