KR100469346B1 - Liquid crystal display panel and method for fabricating the same - Google Patents

Abstract

The present invention is to provide a liquid crystal display panel and a method of manufacturing the liquid crystal display panel that can improve the bonding force when bonding the two substrates using the sealing material, the liquid crystal display panel of the present invention comprises a first substrate and a second substrate, A gate metal and a data metal formed on a first substrate, a transparent conductive film formed to cover the respective gate metal and data metal at the edge of the first substrate, the first substrate and the second corresponding to the transparent conductive film Since the sealing material is formed between the substrates, the bonding force between the transparent conductive film and the sealing material can be increased, thereby facilitating the bonding between the first substrate and the second substrate.

Description

Liquid crystal display panel and method for fabricating the same

The present invention relates to a display device, and more particularly, to a liquid crystal display panel and a method of manufacturing the same.

Due to the rapid development of the information and communication field, the importance of the display industry for displaying desired information is increasing day by day. To date, the CRT (cathod ray tube) among information display devices can display various colors and the brightness of the screen is excellent. It has enjoyed steady popularity so far. However, because of the desire for large, portable and high resolution displays, the development of flat panel displays is urgently needed instead of the CRT. These flat panel displays have a wide range of applications from computer monitors to displays used in aircraft and spacecraft.

Currently produced or developed flat panel displays include liquid crystal display (LCD), electro luminescent display (ELD), field emission display (FED), plasma display panel (PDP), etc. In order to achieve an ideal flat panel display, light weight, high brightness, high efficiency, high resolution, high speed response characteristics, low driving voltage, low power consumption, low cost, and color display characteristics are required.

In general, the CRT displays by controlling the trace of the electron beam by emitting a fluorescent material on the surface of the CRT analogously based on the display timing and data signal applied from the outside, whereas the liquid crystal display (LCD) displays each display position Display by adjusting the transmittance of light by controlling the electric field applied to the LCD.

Such a liquid crystal display device is composed of two glass substrates and a liquid crystal layer enclosed therebetween, and uses a TFT (Thin Film Transistor) as a switching element for switching a signal voltage to the liquid crystal layer.

That is, as shown in FIG. 1, the liquid crystal display device includes a liquid crystal between a first substrate 1 on which a thin film transistor as a switching element is formed, and a second substrate 2 on which a color filter is formed. It is a non-light emitting element which injects (3) and acquires an image effect by using the electro-optical characteristic of the said liquid crystal.

The TFT array 4, the protective film 13, the pixel electrode 4a and the alignment film 8 are formed on the first substrate 1, and the light blocking film 5 and the color filter layer 6 are formed on the second substrate 2. The common electrode 7 and the alignment film 8 are formed.

The first substrate 1 and the second substrate 2 are bonded by a sealing material 9 such as an epoxy resin, and the driving circuit 11 on the PCB 10 is connected via a tape carrier package (TCP) 12. The driving circuit 11 is connected to the first substrate 1 and generates and outputs various control signals and signal voltages for displaying an image.

Here, the sealing material 9 serves to protect the liquid crystal between the two substrates as well as to bond and fix the two glass substrates.

For example, the liquid crystal absorbs moisture when it is left in the air, so the specific resistance is lowered, thereby causing a defect due to a control signal, which may result in deterioration of device characteristics due to the inflow of impurities such as moisture.

Therefore, in order to prevent such a phenomenon, materials such as epoxy resin, phenol resin, acrylic resin, heat and photocurable resin, etc. are used as sealing materials, all of which ensure high reliability. For this reason, strong adhesive strength, high crystallization rate, good printability, and the like are required, and in order to control more precise cell gaps, it is required to have a uniform spreading degree during pressurization, heating, and curing of the substrate.

However, in the case of a liquid crystal panel having a large area depending on the size of the liquid crystal display, the characteristics of the sealing material will be dominant. However, in a small liquid crystal display such as a portable PDA or PCS, when the size of the liquid crystal panel is small, strong adhesion is achieved. In addition to the necessity of a sealing material having, studies have been made on the surface materials of the two substrates of the liquid crystal panel and the structure of the two substrates adhered to the sealing material.

Accordingly, there is a need for development of a liquid crystal panel having a structure having a superior bonding force with the sealing material and a liquid crystal panel having a large surface area in contact with the sealing material.

Hereinafter, a liquid crystal display panel according to the related art will be described with reference to the accompanying drawings.

2 is a plan view of a liquid crystal display panel according to the prior art, in which a first substrate 21 and a second substrate 21a are disposed to face each other, and a liquid crystal layer (not shown) is formed therebetween. The first substrate 21 and the second substrate 21a are largely defined as an active region A and a pad region P. A plurality of thin film transistors and a plurality of thin film transistors are formed on the first substrate 21 of the active region A. Pixel electrodes are formed, and a plurality of gate pads 23 and data pads 25 are formed on the first substrate 21 of the pad region P. FIG.

A sealing material for bonding the first substrate 21 and the second substrate 21a to the pad region P outside the active region A, and more specifically, the pad link portion PL, 27) is formed.

FIG. 3 is a detailed view of part “a” of FIG. 2, in which a plurality of gate lines G1, G2,..., Gn and data lines D1, D2 are formed in the active region A on the first substrate 21. Dn are intersected to define a plurality of pixel regions, and pixel electrodes 31 are disposed in the pixel regions, and the gate lines G1, G2, ..., Gn and the data lines are arranged. Thin film transistors (not shown) are disposed at intersections of (D1, D2, ..., Dn).

The gate pads GP1, GP2, ..., GPn and the data pads DP1, DP2, ..., DPn are electrically connected to the driving IC through TCP and ACF, and the gate pads GP1, GP2,. The driving signals and the data signals applied to the GPn and the data pads DP1, DP2, ..., DPn are gated in the active area A through the gate pad link PL_g and the data pad link PL_d. The wirings GP1, GP2, ..., GPn and the data wirings DP1, DP2, ..., DPn are respectively linked.

In practice, the gate pads GP1, GP2, ..., GPn and the data pads DP1, DP2, ..., DPn are electrically connected to the TCP and Anisotropic Conductive Film (ACF) by the transparent conductive film 33. The thin film transistor is driven by receiving a driving signal and a data signal from an external driving IC.

Further, on the gate pad link PL_g and the data pad link PL_d, a seal is formed between the first substrate 21 and the second substrate to protect the liquid crystal (3 in FIG. 1) formed in the active region A. FIG. It adheres with the ash 27.

The conventional liquid crystal display panel will be described in more detail as follows.

FIG. 4A is a cross-sectional view taken along the line II ′ of FIG. 3, and is illustrated around the gate pad.

As shown in FIG. 4A, a gate wiring (not shown), a gate pad (not shown), and a gate pad link PL_g are formed on the first substrate 41, and the gate pad link PL_g may be formed. A gate insulating film 43 is formed on the upper side, a protective film 45 is formed on the gate insulating film 43, and a sealing and bonding with the second substrate 41a are formed on the protective film 45. Seal 47 is formed to be able to.

Although not shown, the thin film transistor and the pixel electrode are formed in a line along the gate line on the first substrate 41 on which the gate pad link PL_g is formed. That is, a gate electrode, a gate insulating film 43 formed on the gate electrode, a semiconductor layer and an ohmic contact layer formed on the gate insulating film 43, and a source and drain electrode at the intersection of the gate wiring and the data wiring. A thin film transistor is formed. A passivation layer 45 is formed on the entire surface of the first substrate 41 including the thin film transistor, and a pixel electrode connected to the drain electrode is formed through the passivation layer 45.

The gate wiring, the gate pad, and the gate pad link PL_g may be made of an opaque metal such as aluminum (Al), chromium (Cr), molybdenum (Mo), copper (Cu), and an aluminum alloy or a double layer thereof. In addition, the gate insulating layer is formed of silicon oxide (Si0 ₂ ), silicon nitride (SiNx), and the like, and the passivation layer 45 minimizes an electrical interference effect generated between the thin film transistor and the data line and the pixel electrode. It is made of highly insulating materials such as BCB (Benzocyclobutene).

For reference, FIG. 4B is a cross-sectional view taken along the line II-II 'of FIG. 3, where "PL_d" indicates a data side pad link.

4B is similar to the cross section of FIG. 4A except that the data pad DP1 and the data line D1 are formed on the gate insulating layer 43, and thus descriptions thereof will be omitted.

In the conventional liquid crystal display panel, a gate signal and a data signal are applied from an external driver IC through the gate pads GP1, GP2, ..., GPn and the data pads DP1, DP2, ..., DPn. The signals are transferred to the gate lines G1, G2, ..., Gn and the data lines D1, D2, ..., Dn of the active area A, respectively, and are imaged by the on / off operation of the thin film transistor. Is displayed.

However, the conventional liquid crystal display panel as described above has the following problems.

First, a sealing material for bonding the first substrate and the second substrate to the pad link portion outside the active region is formed, and an area contacted by the sealing material corresponds to the protective film of the first substrate and the light blocking film of the second substrate. There is a problem in that the adhesive strength is lowered because it is limited only to the plane.

In addition, when the BCB having excellent insulating property is used as the passivation layer in the liquid crystal display panel according to the prior art, there is a problem in that the bonding force between the gate insulating layer, the data pad link, and the sealing material that contacts the passivation layer is decreased.

Therefore, the adhesion of the first substrate and the second substrate leads to a poor bonding, which eventually acts as a factor of lowering the reliability of the product.

The present invention has been made to solve the above-mentioned problems of the prior art, and in order to increase the adhesion of the sealing material for bonding the two substrates, the protective film and the gate insulating film between each gate and the data pad link is removed, and the remaining two It is an object of the present invention to provide a liquid crystal display panel and a method of manufacturing the same, which can solve a problem of poor adhesion between two substrates by forming a metal layer to cover a protective film and a gate insulating film on an upper side of a pad link, thereby improving reliability of a product. .

1 is a configuration diagram of a general liquid crystal display device.

2 is a plan view of a liquid crystal display panel according to the prior art.

3 is a partial detail view of FIG. 2;

4A is a cross-sectional view taken along the line II ′ of FIG. 3.

4B is a cross-sectional view taken along line II-II ′ of FIG. 3.

5 is a plan view of a liquid crystal display panel according to the present invention;

6 is a cross-sectional view taken along line III-III ′ of FIG. 5.

7 is a cross-sectional view taken along line IV-IV ′ of FIG. 5 according to the first embodiment of the present invention.

8 is a cross-sectional view taken along line IV-IV ′ of FIG. 5 according to a second embodiment of the present invention.

9A to 9D are cross-sectional views taken along the line III-III 'of FIG. 5;

Explanation of symbols for main parts of the drawings

61, 61a: first and second substrates 63: transparent conductive film

67 sealing material 71 pixel electrode

71a: transparent conductive film 81: gate insulating film

83: protective film 85: light shielding layer

The liquid crystal display panel of the present invention for achieving the above object, each pad for electrically connecting the first substrate and the second substrate, the gate wiring and gate pad formed on the first substrate and the data wiring and the data pad And a link member, a transparent conductive film formed to cover the pad link, and a sealing material formed between the transparent conductive film and the first and second substrates.

In addition, another aspect of the present invention is a process of forming a plurality of gate wirings and gate pads on a first substrate, forming a data wiring and a data pad via a gate insulating film on the gate wiring and the gate pad, Forming a passivation layer on the gate insulating layer, the data line and the data pad, and forming a transparent conductive material to contact each pad link connecting the gate line and the gate pad and the data line and the data pad on which the passivation layer is formed. It is a liquid crystal display panel manufacturing method characterized by including the process of doing.

In the method of manufacturing a liquid crystal display panel of the present invention, a process of forming a plurality of gate wirings and gate pads on a first substrate, a process of forming a data wiring and a data pad through a gate insulating film on the gate wirings and the gate pad, and the gate insulating film And forming a passivation layer on the data line and the data pad, and connecting each pad link so that a transparent conductive material is covered on the gate line and gate pad where the passivation layer is formed, and a connection portion corresponding to the data line and the data pad. And forming a step of joining the second substrate facing the first substrate.

That is, the gate insulating film and the protective film are removed between each gate pad link and the data pad link to increase the surface area of the sealing material and form a transparent electrode surrounding the remaining protective film, gate insulating film, gate pad link, and data pad link. Thus, the bonding force between the protective film and the sealing material of the first substrate may be increased.

Such a liquid crystal display panel and a method of manufacturing the same will be described with reference to the accompanying drawings.

5 is a plan view of the liquid crystal display panel of the present invention.

As shown in FIG. 5, the liquid crystal display panel of the present invention includes a plurality of gate lines G1, G2,..., Gn and data lines crossing and disposed in the active region A to define a plurality of pixel regions. (D1, D2, ..., Dn) are formed, and the pixel electrode 71 is formed in each pixel area.

The pad region P may include a plurality of gate pads GP1, GP2,..., GPn electrically connected to an external driving IC, and the gate lines G1, G2,..., Gn, and gates. A gate pad link PL_g electrically connecting the pads GP1, GP2,..., GPn, and a transparent conductive layer 71a formed simultaneously with the pixel electrode 71 are formed on the gate pad link PL_g. It is.

Similarly, a data pad link PL_d connecting the data lines D1, D2, ..., Dn and the data pads DP1, DP2, ..., DPn and a transparent conductive film 71a are formed on the pad link. Formed.

In the pad link portion PL where the two pad links PL_g and PL_d, which are covered with the transparent conductive material 71a, are disposed, the first substrate 61 and the second substrate are formed along the outer portion of the active area A. The sealing material 67 for joining 61a) is formed.

Here, the gate lines G1, G2, ..., Gn and the data lines D1, D2, ..., Dn, the gate pads GP1, GP2, ..., GPn and the data pads DP1, DP2, ..., DPn are made of an opaque metal such as aluminum (Al), chromium (Cr), molybdenum (Mo), copper (Cu), and an aluminum alloy or a double layer thereof, and the pad link PL_g ( The transparent conductive film 71a covering the PL_ds is a conductive material such as indium tin oxide (ITO), and is formed of a material having good bonding force with the sealing material 67.

FIG. 6 is a cross-sectional view taken along line III-III ′ of FIG. 5, and is illustrated with a center of the gate pad.

As illustrated in FIG. 6, a gate pad link PL_g connecting the gate line G1 and the gate pad GP1 is formed on the first substrate 61, and is disposed on the upper side of the gate pad link PL_g. A gate insulating layer 81 is formed, and a passivation layer 83 is formed on the gate insulating layer 81, and the upper portion of the passivation layer 83, the gate insulating layer 81, and the gate pad link PL_g and a part of both sides. A transparent conductive film 71a formed on the surface of the first substrate is formed.

The gate line G1 and the gate pad GP1 may be made of an opaque metal such as aluminum (Al), chromium (Cr), molybdenum (Mo), copper (Cu), an aluminum alloy, or a double layer thereof.

In particular, when the passivation layer 83 is made of BCB (Banzocyclobutene), since the bonding force 81 with the gate insulating layer is weak, the gate insulating layer 81 and the passivation layer 83 are formed using the transparent conductive layer 71a. ) And the transparent conductive film 71a may be formed on the surface of the first substrate 61 on the upper and both sides of the gate pad link PL_g to increase the bonding force of the sealing material (67 of FIG. 5). .

Although not shown in the figure, a semiconductor layer used as a channel of a thin film transistor is formed on the gate insulating film 81 of the active region A, and a source electrode and a drain electrode of the thin film transistor are formed on the semiconductor layer. A pixel electrode 71 is formed on the passivation layer 83 to be electrically connected to the drain electrode through a connection hole.

Accordingly, a transparent conductive film 71a is formed simultaneously with the pixel electrode 71 on the gate pad link connecting the gate line and the gate pad.

On the other hand, in the active region A on the second substrate 61a, a light blocking layer 85 for preventing light from being transmitted to a region other than the pixel electrode formed on the first substrate 61 is provided with the pad link PL_g. A plurality of color filter layers 87 are formed to extend to the formed region, and a common electrode for applying a voltage to the liquid crystal layer LC together with the pixel electrode 71 formed on the first substrate 61. 89 is formed.

The first substrate 61 and the second substrate are disposed between the transparent conductive film 71a and the first substrate 61 surface on the gate pad link PL_g and the light blocking layer 85 on the second substrate 61a. The sealing material 67 for joining the board | substrate 61a is formed.

Therefore, since the area | region to which the said sealing material 67 adheres is enlarged, and the said transparent conductive film 71a is formed on the adhesive surface, the adhesion improvement of the said 1st board | substrate 61 and the 2nd board | substrate 61a is improved. As a result, the reliability of the product can be improved.

7 to 8 are cross-sectional views of IV to IV 'according to the first to second embodiments of the present invention of FIG. 5, where “PL_d” indicates a pad link.

First, the liquid crystal display panel according to the first exemplary embodiment of the present invention is similar to the cross-sectional view of FIG. 6 except that the data pad link PL_d is formed on the gate insulating layer 81.

That is, as shown in FIG. 7, the gate insulating film 81 is formed on the entire surface of the first substrate 61, and a plurality of data interconnects D1 and the data pad DP1 are connected on the gate insulating film 81. A data pad link PL_d is formed, a passivation layer 83 is formed on the data pad link PL_d, and a portion of the gate insulating layer 81 above and both sides of the passivation layer 83 and the data pad link PL_d. The transparent conductive film 71a is formed on it.

Secondly, in the liquid crystal display panel according to the second embodiment of the present invention, the data pad link PL_d is formed on the gate insulating film 81, and the insulating film 81 is formed between the data pad links PL_d. This is etched.

As shown in FIG. 8, a gate insulating film 81 is formed in a predetermined portion of the first substrate 61, and the data line D1 and the data pad DP1 are formed on the gate insulating layer 81 formed in the predetermined portion. A plurality of data pad links PL_d to be connected are formed, and a passivation layer 83 is formed on the data pad link PL_d, and the first and second portions of the upper portion and both sides of the passivation layer 83 and the data pad link PL_d are formed. A transparent conductive film 71a is formed on the surface of the substrate 61 at the same time as the pixel electrode 71 of FIG. 5.

Such a liquid crystal display panel manufacturing method of the present invention will be described with reference to the drawings.

9A to 9D are cross-sectional views taken along line III-III 'of FIG. 5.

As shown in FIG. 9A, a plurality of pad links (not shown) made of the same opaque conductive metal to connect the gate pads (not shown) and the plurality of gate wires (not shown) formed on the first substrate 61. PL_g).

Here, the gate wiring and the pad link PL_g are opaque metals such as aluminum (Al), chromium (Cr), molybdenum (Mo), copper (Cu), and an aluminum alloy or a double layer thereof.

Subsequently, a gate insulating film 81 of FIG. 6 is formed on the entire surface of the first substrate 61 including the gate pad and the gate wiring, and in the active region (A of FIG. 5) on the gate insulating film 81, as shown in FIG. A plurality of data lines (not shown) made of an opaque metal are formed, and a plurality of data pads (DP1, DP2, DP3 in FIG. 5) made of the same material as the data lines are formed in the pad region (P in FIG. 5). .

In this case, the semiconductor layer used as the channel of the thin film transistor, the source and the drain electrode are formed on the gate insulating film 81 of the active region A.

Thereafter, as shown in FIG. 9B, the passivation layer 83 is formed on the entire surface of the first substrate 61 including the data pad (not shown) and the data wiring (not shown), and each gate pad link PL_g is formed. ) And the protective film 83 and the gate insulating film 81 between the data pad link (not shown) are etched.

As illustrated in FIG. 9C, the first substrate (not shown) of the remaining gate insulating layer 81, the passivation layer 83, the gate pad link PL_g and the data pad link (not shown) may be formed. 61) A transparent conductive film 71a is formed on the surface. In this case, the gate insulating layer 81 is not etched between the data pad links, and a transparent conductive film (not shown) is formed on the passivation layer 83 and the surface of the gate insulating layer 81 on portions of both sides of the data pad link PL_d. 71a) may be formed.

Subsequently, as shown in FIG. 9D, a light blocking film 85, a color filter layer (not shown), and a common electrode (not shown) are formed on the second substrate 61a and formed on the gate pad link PL_g. After forming the sealing material 67 for bonding the first substrate 61 and the second substrate 61a on the substrate, the two substrates are bonded together and then liquid crystal (not shown) is injected to inject the liquid crystal display panel of the present invention. The manufacturing process of is completed.

As described above, the liquid crystal display panel of the present invention has the following effects.

First, the bonding force may be increased by removing the space between the gate pad link and the data pad link connecting the respective pads and the wiring to increase the surface area to be bonded to the sealing material for bonding the first substrate and the second substrate.

Second, the bonding force with the sealing material may be enhanced by surrounding the gate insulating layer and the protective layer on the gate pad link and the data pad link and forming a transparent conductive layer on the first substrate or the gate insulating layer on both sides of the gate pad link and the data pad link. have.

Therefore, the surface area in contact with the sealing material is increased, and the gate insulating film and the protective film on the gate pad link and the data pad link can be wrapped with the transparent conductive film having good bonding force with the sealing material, thereby improving the bonding between the two substrates and eliminating the defect of the bonding. As a result, the reliability of the product can be improved.

Claims (8)

A first substrate and a second substrate; Respective pad links electrically connecting gate wirings and gate pads formed on the first substrate, and data wirings and data pads; A protective film formed on the pad link; A transparent conductive film formed to cover the protective film and the pad link; And And a sealing material formed between the transparent conductive film and the first and second substrates. The liquid crystal display panel of claim 1, wherein the transparent conductive layer is formed on a gate insulating layer and a protective layer corresponding to the gate pad link, and on both sides of the gate pad link and a portion of the first substrate. The liquid crystal display panel of claim 1, wherein the transparent conductive layer is formed on an upper side of a protective layer corresponding to the data pad link, on both sides of the data metal, and a surface of the first substrate. The liquid crystal display panel of claim 1, wherein the transparent conductive layer contacts a portion of the gate insulating layer through a protective layer on the data pad link. Forming a plurality of gate wirings and gate pads on the first substrate; Forming a data line and a data pad through a gate insulating film on the gate line and the gate pad; Forming a protective film on the gate insulating film, the data line and the data pad; And And forming a transparent conductive material in contact with each of the pad links connecting the gate line and the gate pad and the data line and the data pad having the protective layer formed thereon. 6. The method of claim 5, further comprising removing a gate insulating film and a protective film formed between each of the pad links and the pad links. The method of claim 5, further comprising removing a protective film formed between the data pad link and the data pad link. 6. The liquid crystal of claim 5, further comprising: forming a sealing material along the periphery of the second substrate corresponding to the region where the respective pad links are formed after forming the respective pad links. Display panel manufacturing method.