KR100462395B1 - Epi Structure and Fabrication Method of InP based MOSFET for Uniform Device Characteristics - Google Patents

Abstract

The present invention relates to an epitaxial structure for a MOSFET and a method of manufacturing a device using the same. The epitaxial structure of the present invention according to the first aspect of the present invention is doped with a semi-insulating InP substrate 10 and impurities grown on the substrate. Non-InAlAs or InP buffer layer 11, InGaAs channel layer 12 grown on the buffer layer, InP antioxidant layer 13 grown on the InGaAs channel layer and high concentration N type grown on the InP antioxidant layer Epitaxial structures for MOSFETs comprising an InGaAs ohmic / oxide layer 14 doped with impurities.

In addition, the present invention can implement a device having a stable and uniform device characteristics by performing a two-step oxidation process of the liquid phase oxidation process and the oxygen plasma treatment step in the formation of the oxide film when the device using the epi structure of the structure.

Description

Epi Structure and Fabrication Method of InP based MOSFET for Uniform Device Characteristics with INP-based MOSFET Epitaxial Structure with Uniform Device Characteristics

The present invention relates to an epitaxial structure for a MOSFET and a method of manufacturing the device using the same, and more particularly to an epitaxial structure for an InP-based MISFET (InGaAs channel MOSFET and InP channel MOSFET) having a uniform device characteristics and a device fabrication process using the same will be.

Compound semiconductor-based MISFETs (Metal Insulator Semiconductor Field Effect Transistors) are used in devices in the microwave or millimeter-wave (10-100 GHz) bands because they have superior electron velocity characteristics compared to silicon-based MISFETs (or MOSFETs). Since compound semiconductor-based MISFETs utilize MIS gates, they have higher gate breakdown voltage and lower gate leakage current than MESFET or (p-) HEMT fabricated by forming Schottky gates on existing compound semiconductors. These advantages and superior speed characteristics make compound semiconductor-based MISFETs one of the most important device technologies that can be used to develop high-performance millimeter-wave band wireless communication circuits and components or optical communication circuits and components of several tens of Gbps or more.

Conventional MISFET fabrication method using compound semiconductor is divided into 1) method of depositing a dielectric such as Si ₃ N ₄ , SiO ₂ , Ga ₂ O ₃ , Gd ₂ O ₃ by various methods, and 2) oxidizing compound semiconductor. do. Dielectric deposition methods are generally difficult to form high-quality dielectric / compound semiconductor interface characteristics, and due to the high interface state density, the fabricated MISFETs do not switch completely. It was often inappropriate for the application. In order to obtain good dielectric / compound semiconductor properties, special compound semiconductor surface treatment is required. Recently, IBM has treated GaAs surface in MBE growth chamber and Ga ₂ O ₃ and ultra high vacuum deposition device directly connected to MBE growth chamber. Successfully fabricated a GaAs C-MOSFET capable of device application by vacuum deposition of Gd ₂ O ₃ , but has the disadvantage that expensive equipment is required for oxide film formation. A conceptual cross sectional view of a device fabricated in this manner is shown in FIG.

Although many efforts have been made to oxidize the surface of GaAs to form an oxide film, a high quality oxide film having physically, chemically and electrically stable properties has not been produced. Recently, however, H. H. Wang et al. Oxidized GaAs by liquid phase oxidation to produce a high-quality oxide film and succeeded in manufacturing a depletion mode GaAs MOSFET with excellent device characteristics. A conceptual cross sectional view of a device fabricated through oxidation of GaAs is shown in FIG. 1B.

InP-based materials (InGaAs, InP, etc.) have higher electron mobility (InGaAs case) or saturation rate (InP case) than GaAs, so the velocity characteristics of electronic devices manufactured using them are higher than those of GaAs electronic devices. Much better. Therefore, InGaAs MOSFETs exhibit superior speed characteristics compared to GaAs MOSFETs. However, in the case of MOSFETs having InGaAs or InP as a channel, it is difficult to form a high-quality oxide film, and thus a device having excellent characteristics has not been manufactured. Therefore, there is a need for a technique for forming a high quality oxide film for fabricating a MOSFET utilizing InGaAs or InP as a channel. In addition, in order to manufacture a device showing uniform characteristics, it is required to develop an epitaxial structure and a manufacturing process that can improve the uniformity of device characteristics.

As described above, InP-based compound semiconductors (InP or InGaAs) have superior thermal conductivity, electron mobility, and saturation velocity characteristics compared to GaAs, but high quality oxide film formation technology has not been developed. Many limitations to circuit applications follow.

Accordingly, an object of the present invention is to provide a stable high quality InGaAs oxide film manufacturing process that can be applied to InGaAs channel or InP channel MOSFET device, InGaAs channel or InP channel MOSFET epitaxial structure to obtain uniform device characteristics and device manufacturing process using the same In providing.

Figure 1 (a) is a cross-sectional view of a GaAs MOSFET fabricated using the oxide film deposition method of the prior art.

Figure 1 (b) is a cross-sectional view of a GaAs MOSFET fabricated using the liquid phase oxidation method of the prior art.

Figure 2 (a) is a cross-sectional view of the InGaAs channel MOSFET epi structure of the present invention.

Figure 2 (b) is a cross-sectional view of the InP channel MOSFET epi structure of the present invention.

2 (c) to 2 (f) is a manufacturing process diagram of the InGaAs channel MOSFET of the present invention.

Figure 2 (g) to 2 (j) is a manufacturing process diagram of the InP channel MOSFET of the present invention.

Figure 3 (a) is a schematic diagram of the InGaAs liquid phase oxidation process apparatus of the present invention.

Figure 3 (b) is a graph of the relationship between the thickness of the InGaAs and the pH of the solution grown using the liquid phase oxidation treatment of the present invention.

Figure 3 (c) is a schematic diagram of the oxygen plasma treatment process apparatus of the liquid oxidized InGaAs oxide film of the present invention.

<Code Description of Main Parts of Drawing>

10,30: substrate 11,31: buffer layer

12,32: channel layer 13: InP antioxidant layer

14: InGaAs ohmic / oxide layer 15,35: ohmic metal

16,36: Antioxidant film 17,37: Oxidation window

18,38: InGaAs oxide film 19,39: source electrode

20, 40: drain electrode 21, 41: gate electrode

33: InGaAs spacer layer 50: water heater

51: stirred heater 52: temperature controller

53: temperature meter 54: pH meter

55: pH electrode 56: oxidation solution

57: Sample (InGaAs) 58: Sample Holder

60: vacuum device 61: RF source

62: heating electrode

The present invention is epitaxial structure for MOSFET,

The epitaxial structure of the present invention according to the first aspect is a semi-insulated InP substrate 10 as shown in FIG. 2A, an InAlAs or InP buffer layer 11 which is not doped with impurities grown on the substrate, and grown on the buffer layer. The InGaAs channel layer 12, the InP antioxidant layer 13 grown on the InGaAs channel layer, and the InGaAs ohmic / oxide layer 14 doped with high concentration N-type impurities grown on the InP antioxidant layer. An epitaxial structure for a MOSFET is included.

Also, the epitaxial structure as the second aspect of the present invention is grown on the semi-insulated InP substrate 30, the InAlAs or InP buffer layer 31 which is not doped with impurities grown on the substrate, and the buffer layer as shown in FIG. 2B. The InP channel layer 32, the InGaAs spacer layer 33 grown on the InP channel layer and doped with impurities, and the InGaAs ohmic / oxide layer 34 doped with high concentration N-type impurities grown on the InGaAs spacer layer. Epitaxial structure for a MOSFET characterized in that it comprises a.

First, a MOSFET epitaxial structure including an InGaAs channel layer shown in FIG. 2A will be described.

An undoped InAlAs or InP buffer layer 11 is formed on the semi-insulated InP substrate 10. InGaAs channel layer 12 formed on the buffer layer is preferably doped with n-type impurity in the depletion mode, do not doping or very low p-type doping in the enhancement mode (enhancement mode) do. The InP antioxidant layer 13 formed on the InGaAs channel layer 12 is a crystal layer for improving the uniformity of device characteristics, and serves to prevent the InGaAs channel layer from being oxidized during the InGaAs oxide film fabrication process. The InGaAs ohmic / oxide layer 14 formed on the InP antioxidant layer 13 is preferably doped with a high concentration of n-type (n ⁺ ) impurities. When doping with a high concentration of n-type impurities as described above, it is possible to form an electrode having a very low ohmic resistance when forming the source and drain ohmic electrodes of the MOSFET.

The portion below the gate metal electrode on InGaAs ohmic / oxide layer 14 is provided to form the oxide layer. Preferably, the InGaAs oxidation method applied to the present invention is a selective oxidation method that oxidizes only InGaAs but does not oxidize InP. Therefore, n ⁺ n ⁺ -InGaAs ohmic / oxide layer (14, the thickness of the oxide film is determined during epitaxial growth even if a sufficiently long time (over-oxidation) oxide to -InGaAs when oxidizing the oxide layer to form a uniform InGaAs layer oxide film of good quality ) Is determined by the thickness. In the absence of the InP anti-oxidation layer 13, the oxidation of InGaAs may penetrate into the InGaAs channel layer 12. In order to control the thickness of the oxide film, precise time control is required, resulting in inferior uniformity or reproducibility. Device characteristics are obtained.

Next, a MOSFET epitaxial structure including an InP channel layer shown in FIG. 2B will be described.

An undoped InAlAs or InP buffer layer 31 is formed on the semi-insulated InP substrate 30. The InP channel layer 32 formed on the buffer layer is preferably doped with n-type impurities in the depletion mode, and do not do or do very low p-type doping in the enhancement mode. The InGaAs spacer layer 33 formed on the InP channel layer 32 is preferably not doped, and impurities of the n ⁺ -InGaAs ohmic / oxide layer 34 to be formed on the spacer are diffused into the InP channel layer 32. It is a crystalline layer for preventing influence on device characteristics. The InGaAs ohmic / oxide layer 34 formed on the InGaAs spacer layer 33 is preferably doped with a high concentration of n-type (n ⁺ ) impurities and its role is the same as that of the InGaAs channel MOSFET of FIG. . The InP channel MOSFET epistructure does not have an InP antioxidant layer 13, because the InP channel layer 32 also serves as an antioxidant layer. This structure enables the formation of an InGaAs oxide film that is very uniform and highly reproducible in the case of InPA channel MOSFETs, just like InGaAs channel MOSFETs.

The manufacturing process diagrams of the InGaAs channel MOSFET and the InP channel MOSFET of the present invention are shown in Figs. 2 (c) to 2 (f) and 2 (g) to 2 (j), respectively.

First, an InGaAs channel MOSFET fabrication process diagram shown in FIGS. 2 (c) to 2 (f) is as follows. First, mask the device region of the MOSFET with a photoresist or the like, and then n ⁺ -InGaAs ohmic / oxide layer 14, InP antioxidant layer 13, InGaAs channel layer 12, InAlAs or InP buffer layer 11, semi-insulated InP substrate ( A portion of 10) is etched to perform a device isolation process. The ohmic metal 15 is then deposited to form source and drain ohmic electrodes. A cross-sectional view of the device after these processes is shown in Figure 2 (c).

Next, an oxide film 16 such as silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ) is deposited on the sample, and an oxidation window for oxidation of the gate region is performed through lithography using a photoresist. window) 17. The cross-sectional view of the device that has been processed so far is shown in FIG.

An InGaAs oxide film is formed using the sample. The InGaAs oxidation process is preferably performed by a two step process as follows.

Liquid phase oxidation process

(1) Preparation of Liquid Oxidation Solution

Preparation of the oxidizing solution for the liquid phase oxidation process is not particularly limited. In the present invention, according to the method used by H. H. Wang mentioned above was performed as follows.

First, Ga or In is dissolved in a nitric acid solution heated to about 60 ° C. Dilute the solution by adding about 10 times the volume of pure water. At this time, the pH of the diluted oxidant shows high acidity of about 1-2. The pH was measured while adding the diluted ammonia water, and adjusted to have a pH value (about 4.0 to 5.0, preferably about 4.7) suitable for InGaAs oxidation. When pH is adjusted by the addition of aqueous ammonia, a precipitate is formed in the oxidizing solution, and the precipitate is preferably removed using a filter paper or a centrifugal separator in order to form a high quality oxide film.

(2) Oxidation of Ga and As in InGaAs

After the oxidizing solution is prepared, InGaAs is oxidized using the liquid phase oxidizing apparatus shown in FIG. The temperature of the oxidizing solution 56 is controlled using a temperature controller 52 provided with a water heater 50, a stirring heater 51 for heating the water heater, and a temperature measuring device 53, which provides energy for the reaction. The acidity of the oxidizing solution 56 is monitored using a pH meter 54 having a pH electrode 55 for measuring the pH of the liquid. The InGaAs sample 57 is supported by the sample holder 58 and is located in the oxidizing liquid 56. The relationship between the thickness and pH of the InGaAs oxide film using the liquid phase oxidation method is shown in FIG. 3 (b).

The InGaAs oxide film formed through the liquid phase oxidation method as described above has a finite electrical conductivity and thus cannot be used as an oxide film of an InGaAs MOSFET. X-ray photoelectron spectroscopy (XPS) analysis of the InGaAs oxide film formed by the liquid phase oxidation method shows that the metal In is present in the oxide film, which causes finite electrical conductivity.

Oxygen Plasma Treatment Process

In order to solve the finite electrical conductivity problem of the InGaAs oxide film formed by the liquid phase oxidation method, the metal In in the oxide film must be oxidized. This can be performed using the known oxygen plasma processing equipment of Figure 3 (c). Basically, the oxygen plasma processing equipment includes a vacuum device 60 capable of maintaining the degree of vacuum in the chamber, an RF source 61 for generating plasma, a heating electrode 62 for heating the sample 57, and the like. The metal In in the InGaAs oxide film formed through the liquid phase oxidation method is oxidized while controlling the pressure, RF power, temperature, and time of the oxygen inside. At this time, the applicable oxygen plasma treatment conditions may vary depending on the thickness of the oxide film, but for InGaAs oxide film having a thickness of about 400 kV, the oxygen pressure is 1 Torr and the plasma RF power is about 100 W while the sample is heated to about 300 ° C. in a vacuum chamber. Handle for about 1 hour while maintaining.

A cross-sectional view of the device after the above process is shown in FIG.

Next, a window for the metal electrode is opened on the source and drain ohmic metal 15, and the gate electrode 21 and the source metal electrode 19 / drain metal electrode 20 are formed through photoresist to form an InGaAs channel. The MOSFET process is complete. A device cross section of the completed InGaAs channel MOSFET is shown in FIG. 2 (f).

The process of fabricating the InP channel MOSFET shown in Figs. 2 (g) to 2 (j) of the present invention is as follows. First, mask the device region of the MOSFET with a photoresist or the like, and then n ⁺ -InGaAs ohmic / oxide layer 34, InGaAs spacer layer 33, InP channel layer 32, InAlAs or InP buffer layer 31, semi-insulated InP substrate ( A part of 30) is etched to perform the device isolation process. The ohmic metal is then deposited to form the source and drain ohmic electrodes 35. The cross-sectional view of the device after the above processes are shown in Fig. 2 (g).

Next, an oxide layer 36 such as silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ) is deposited on the sample, and an oxidation window for oxidation of the gate region is performed through lithography using photoresist. window) 37. The cross-sectional view of the device which has been processed so far is shown in Fig. 2 (h).

The InGaAs oxide film 38 is formed using the sample, and the process is the same as that of the InGaAs channel MOSFET. A cross-sectional view of the device after the process of forming the InGaAs oxide film 38 is shown in FIG.

Next, a window for the metal electrode is opened on the source and drain ohmic metal 35, and the gate electrode 41 and the source metal electrode 39 / drain metal electrode 40 are formed through photoresist to form an InP channel. The MOSFET process is complete. A device cross-sectional view of the completed InP channel MOSFET is shown in FIG. 2 (j).

The InGaAs channel and InP channel MOSFET epitaxial structures of the present invention are designed to form a high quality uniform oxide film, so that devices with uniform characteristics can be manufactured and can be utilized for the development of high yield MMIC. In addition, the device fabrication process using the InGaAs channel and InP channel MOSFET epitaxial structure of the present invention enables the fabrication of InGaAs or InP channel MOSFETs having excellent characteristics such as low ohmic resistance, low leakage current, and high breakdown voltage. Compared to MMIC, speed, noise, power, etc. are superior, and can be used for the development of MMIC that can be used for ultra wideband signal processing.

Claims (7)

In the epi structure for MOSFET, A semi-insulated InP substrate, an InAlAs or InP buffer layer that is not doped with impurities grown on the substrate, an InGaAs channel layer grown on the buffer layer, an InP antioxidant layer and an InP antioxidant layer grown on the InGaAs channel layer An InGaAs ohmic / oxidized layer doped with a high concentration N-type impurity grown on the channel layer, wherein the channel layer is doped with n-type impurity in the depletion mode, and the impurities are not doped or doped with a low p-type impurity in the enhancement mode. Epistructure for MOSFET characterized in that the doped. In the epi structure for MOSFET, A semi-insulated InP substrate, an InAlAs or InP buffer layer that is not doped with impurities grown on the substrate, an InP channel layer grown on the buffer layer, an InGaAs spacer layer grown on the InP channel layer and doped with impurities An InGaAs ohmic / oxidation layer doped with a high concentration of N-type impurities grown on the InGaAs spacer layer, wherein the channel layer is doped with n-type impurities in the depletion mode, and dopants are not doped or low in the enhancement mode. An epitaxial structure for a MOSFET characterized in that it is doped with p-type impurities. delete Forming a source and a drain ohmic electrode on the epitaxial structure of claim 1 or 2, respectively; Forming an anti-oxidation film on the epi structure and the ohmic electrode; Forming an oxide window for oxidizing the gate region in the region where the gate is to be formed; Forming an InGaAs oxide film under the oxide window; Forming a window for depositing a source / drain metal electrode on the ohmic metal, and And depositing a self-aligned metal electrode on each of the formed windows. The method of claim 4, wherein the forming of the InGaAs oxide film, (a) oxidizing Ga and As in InGaAs with a predetermined liquid oxidizing solution controlled to acidity; (b) oxidizing the metal In in the InGaAs oxide film oxidized in the step (a) by oxygen plasma treatment. The method of claim 5, A liquid acid solution is prepared by dissolving Ga or In in nitric acid. The method of claim 5, The acidity of the liquid acid solution is a pH manufacturing method characterized in that about 4-5.