KR100462377B1 - Interface circuit for pattern display of liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern display interface circuit in which a gradation can be easily expressed, an RGB data can be easily driven for a gradation, and can be directly interfaced with a liquid crystal module or interfaced through a transceiver according to an interface type. . According to the present invention, a pattern display interface circuit includes a programmable logic device for interfacing grayscale and RGB data for grayscale and grayscale to a liquid crystal module or a transceiver according to a source clock, and a signal from the programmable logic device. A transceiver for transmitting to the liquid crystal module, an oscillator for providing first and second oscillation frequencies as a source clock signal to the programmable logic device, and the first and second signals generated from the oscillator and applied to the programmable logic device. A clock selection unit for selecting one of two oscillation frequencies as a clock signal, a gradation selection unit for raising or lowering the gradation from a preset reference gradation, and a color display according to the gradation selected by the gradation selection unit Display selection section to Characterized in having a.

Description

Interface circuit for pattern display of liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device, and more particularly, to an interface circuit for pattern display of a liquid crystal display device in which 64 gray levels can be easily expressed and RGB data is easily driven for the gray levels.

In general, the liquid crystal display device displays 64 gray levels ranging from 0 to 63 gray levels. In the past, such 64 gradations were adjusted using a resistance string.

However, the conventional method of adjusting the gradation is not only difficult to easily adjust the gradation, but also has a problem in that it is not easy to interface and display the selected gradation in the same manner as the liquid crystal module.

Therefore, in order to solve the above problems, the present invention provides a simple circuit to display 64 gray scales and to easily drive RGB data for the gray scales. The purpose is to provide.

Another object of the present invention is to express the selected gradation and color display according to the interface type by directly interface with the liquid crystal module or by interface with the liquid crystal module through the transceiver, it is easy to check the general operation of the liquid crystal module An object of the present invention is to provide an interface circuit for pattern display of a liquid crystal display device.

In order to achieve the above object of the present invention, the interface circuit for pattern display of the liquid crystal display device according to the present invention,

Programmable logic elements for interfacing the grayscale and RGB data for the grayscale and the grayscale according to the source clock to the liquid crystal module in parallel or through a transceiver;

A transceiver for inputting a signal from the programmable logic device to the liquid crystal module;

An oscillator for providing first and second oscillation frequencies to the programmable logic device as a source clock signal;

A clock selector for selecting one of the first and second oscillation frequencies generated from the oscillator and applied to the programmable logic element as a clock signal;

A gradation selection unit for raising or lowering the gradation from a preset reference gradation;

And a display selection unit for selecting a color display according to the gradation selected by the gradation selection unit.

The first oscillation frequency is 66MHz, the second oscillation frequency is characterized in that 40MHz.

The clock selector includes a first switch having a first variable contact grounded and a second variable contact connected to a power supply terminal through a first resistor, and a common terminal connected to a clock selection terminal of the programmable logic device. When the common contact of is connected to the first variable contact, select one of the two oscillation frequencies 66MHz and 40MHz, and if the common contact of the switch is connected to the second variable contact, the other one of the two oscillation frequencies 66MHz and 40MHz is clock signal It is characterized by supplying a signal for selection.

The gradation selection unit includes a gradation raising means for raising the gradation from the standard gradation and a gradation descending means for lowering the gradation from the reference gradation.

The gray level increasing means includes a second switch having one end grounded and the other end connected to a gray-up terminal of the programmable logic element, and a power supply voltage applied to one end and the other end of the gray-up of the programmable logic element. A third switch having a second resistor connected to a terminal, wherein the gradation lowering means has one end grounded and the other end connected to a gray down terminal of the programmable logic device; A power supply voltage is applied to one end thereof, and the other end includes a third resistor connected to the other end of the third switch and the gray down terminal of the programmable logic device.

The display selector is configured as a rotary switch for displaying all of the RGB or only one color of R, G, and B in the selected gradation by the gradation selector, the common contact being connected to the ground, The fourth variable contact point is connected to a terminal for selecting to display all RGB of the programmable logic device, and a terminal for selecting to display only R, G, and B only among RGB.

A gray display further includes a gray display for displaying a gray selected by the gray selector, wherein the gray display includes two digit segments and inputs data about the gray applied from the programmable logic device to apply from the programmable logic device. According to the chip select signal, the first segment is driven to display the tens digit first, and then the second segment is driven to display the gray scale by a multiplexing method representing the first digit.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a block diagram of an interface circuit for pattern display of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 shows a detailed view of the interface circuit of FIG.

1 and 2, an interface circuit for pattern display of a liquid crystal display according to an exemplary embodiment of the present invention may include a programmable logic device (PLD) 10 having a gate array type and a PLD 10. LVDS transceiver 20 for transmitting the signal to the liquid crystal module (not shown).

In addition, the interface circuit according to the embodiment of the present invention is generated from the oscillation unit 10 and the oscillation unit 10 for providing the oscillation frequency of 66MHz and 40MHz to the PLD 10 as a clock signal to the PLD (10) And a clock selector 40 for selecting one of the oscillation frequencies 66 MHz and 40 MHz applied as a clock signal.

In the embodiment of the present invention, the oscillator 10 includes a first oscillator OSC1 for generating a 66 MHz oscillation frequency to the PLD 10 and a second oscillator for generating a 40 MHz oscillation frequency to the PLD 10. Is made of.

The clock selector 40 has a first variable contact a1 grounded and a second variable contact a2 connected to a power supply terminal Vcc through a resistor R1, and a common terminal c is connected to the PLD ( It consists of a switch (SW1) connected to the clock select terminal (Clock select) of 10).

Therefore, when the common contact c of the switch SW1 is connected to the first variable contact a1, the clock selector 40 uses, for example, a 66 MHz oscillation frequency of two oscillation frequencies 66 MHz and 40 MHz as a clock signal. The signal for selection is supplied to the PLD 10. On the other hand, when the common contact c of the switch SW1 is connected to the second variable contact a2, the PLD 10 selects a signal for selecting, for example, a 40 MHz oscillation frequency as a clock signal from two oscillation frequencies 66 MHz and 40 MHz. To feed.

In addition, the interface circuit of the present invention displays the color display according to the gradation selected by the gradation selector 50 and the gradation selector 50 for raising the gradation toward the 63 gradation from the preset reference gradation or descending to 0 gradation. A display selector 60 for selecting is provided.

The gradation selection unit 50 includes a gradation raising means for raising the gradation from the standard gradation and a gradation descending means for lowering the gradation from the reference gradation.

The gradation rising means is a pull-up switch (SW2) is connected to the gray-up terminal (Gray Up) of the programmable logic device 10, the other end is grounded, the power supply voltage (Vcc) is applied to one end and the other end is The resistor R2 is connected to the other end of the switch SW2 and the gray up terminal Gray up of the programmable logic device 10.

The gray scale lowering means has a pull-down switch (SW3) connected to a gray down terminal (Gray Down) of the programmable logic device 10 at one end of the ground and the other end thereof, and a power supply voltage (Vcc) is applied to the other end thereof. The resistor R3 is connected to the other end of the switch SW3 and the gray down terminal Gray down of the programmable logic device 10.

The display selector 60 selects all of the RGB or only one of the colors R, G, and B. The display selector 60 includes a rotary switch SW4.

The common contact c of the rotary switch SW4 is connected to ground, and the first variable contact a1 is connected to the terminal Color All of the PLD 10 for selecting to display all RGBs. The first variable contact a1 is connected to the terminal Color All of the PLD 10 for selecting to display all RGB, and the second variable contact a2 is for selecting to display only R of RGB. A third variable contact a3 is connected to a terminal G Only of the PLD 10 for selecting to display only G among RGB, and a fourth The variable contact a4 is connected to a terminal B Only of the PLD 10 for selecting to display only B among RGB.

Therefore, when the common contact c of the switch SW4 is connected to the first variable contact a1, RGB is displayed at the gray level selected by the gray level selector 50. When the common contact c is connected to the variable contacts a2 to a4, the PLD 10 displays only R, only G, or only B at the gray level selected by the gray level selector 50, respectively.

In addition, the interface circuit according to the embodiment of the present invention further includes a gradation display unit 70 for displaying the gradation selected by the gradation display unit 50. The gradation display section 70 is composed of two-digit segments to display gradations in two digits. In this case, the gradation display unit 70 does not input data about the gradation applied from the PLD 10 and simultaneously expresses it in two digits, but according to the chip select signal CS applied from the PLD 10. The segment S1 is first driven to display the tens digit first, and then the gray scale is represented by two digits by a multiplexing method representing the ones digit by driving the second segment S2.

The PLD 10 of the present invention is a clock signal CLK, a data enable signal DE, and R, G, B data (R5-R0), (G5-G0) when a 66 MHz oscillation frequency is selected as the source clock. , (B5-B0) is transmitted to the LVDS transceiver 20, and the transceiver 20 is clock (CLK +, CLK-) and 6 bits of RGB data (R +, R-), (G +, G-), ( B +, B-) is applied to the liquid crystal module to interface. In this case, the 6-bit RGB data is transmitted from the PLD 10 to the transceiver 20 in a parallel manner, and the RGB data from the transceiver 20 is applied to the liquid crystal module in a serial manner.

On the other hand, the PLD 10 of the invention has a clock signal CLK, a data enable signal DE, and R, G, B data R5-R0, (G5-G0) when a 40 MHz oscillation frequency is selected as the source clock. ), (B5-B0) is transmitted directly to the liquid crystal module instead of the LVDS transceiver 20 to directly interface. At this time, RGB data R5-R0, G5-G0, and B5-B0 of 6 bits are respectively applied to the liquid crystal module in a parallel manner.

Referring to the operation of the pattern display interface circuit of the liquid crystal display device of the present invention having the configuration as described above is as follows.

First, the oscillator 30 generates a 66 MHz oscillation frequency and a 40 MHz oscillation frequency through the oscillators OSC1 and OSC2 and applies them to the PLD 10. The PLD 10 inputs a 66 MHz oscillation frequency and a 40 MHz oscillation frequency applied from the oscillator 30 to select a corresponding one of the 66 MHz oscillation frequency and the 40 MHz oscillation frequency according to the selection of the clock selector 40.

For example, when the common contact c of the switch SW1 is connected to the variable contact a1, the clock selector 40 receives a low signal through a clock select terminal of the PLD 10. The PLD 10 selects a 40 MHz oscillation frequency as the source clock.

At this time, when the 40MHz oscillation frequency is selected as the source clock in the PLD 10, the clock signal CLK and the data enable signal DE generated from the PLD 10 and the RGB data signals R5-R0 and G5-G0 ), (B5-B0) is directly interfaced to the liquid crystal module without passing through the transceiver (20).

On the contrary, when the common contact c of the switch SW1 is connected to the variable contact a2, the clock selector 40 receives a high state signal, which is a power supply voltage, as a clock select terminal of the PLD 10. Applied, the PLD 10 selects a 66 MHz oscillation frequency as the source clock.

At this time, when the 66MHz oscillation frequency is selected as the source clock in the PLD 10, the clock signal CLK, the data enable signal DE, and the RGB data R5-R0, (G5-G0) and (B5-B0) Is applied to the liquid crystal module via the transceiver 20.

When the PLD 10 transmits the RGB data to the transceiver 20 or directly to the liquid crystal module, the PLD 10 initially transmits RGB data for a preset gray scale from 0 to 63 gray scales. At the same time, in the case of expressing all of the RGB colors, only R, G, or B may be selected and expressed.

For example, assuming that the initial state is set to express all 32 gradations for RGB, the PLD 10 applies the RDB data for the 32 gradations to the transceiver 20 or the liquid crystal module.

If the user wants to increase the gray level, the gray level is increased by one level using the pull-up switch SW2 of the gray level selector 40, and the PLD 10 inputs the increased gray level through the terminal Gray Up. Then, the RGB data for the elevated gradation level, or the data of only R, G, or B is transmitted to the transceiver 20 or the liquid crystal module in the manner described above.

If the user wants to lower the gray level, the gray level may be lowered by one level using the pull-down switch SW3. Similarly, the PLD 10 inputs the lowered gradation level through the terminal (Gray Down), and transmits the RGB data for the lowered gradation level or only the R, G, or B data as described above. ) Or transmit to the liquid crystal module.

Also, if the user wants to express the selected gradation by only one color by lowering or increasing, select one of R, G, and B using the rotary switch SW4 of the display selection unit 60, and express the gradation for the selected color. It is also possible.

In the present invention, the display unit 70 is provided so that the selected gray level can be represented by two digits. Instead of simultaneously displaying two digits, two digits are multiplexed and displayed by the chip select signal CS.

That is, since the chip select signal CS applied from the PLD 10 is applied to the first segment S1 as it is and inverted to the second segment S2 through the inverter IN, only the segment is driven first. By driving the second segment, it is possible to express the gray scale in two digits.

As described in detail above, in the embodiment of the present invention, not only 64 grays can be freely expressed using a simple circuit, but also there is an advantage in that the color display of the selected grays can be freely selected and expressed as desired.

In addition, in the present invention, when color display in grayscale and grayscale is applied to the liquid crystal module, the interface with the liquid crystal module may be directly interfaced with the form of the interface or may be interfaced with the liquid crystal module through the transceiver. It is easy to check the driving of the liquid crystal module.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

1 is a block diagram of an interface circuit for pattern display of a liquid crystal display device according to an embodiment of the present invention;

FIG. 2 is a detailed circuit diagram of the interface circuit for pattern display of FIG. 1; FIG.

(Explanation of symbols for the main parts of the drawing)

10: programmable logic device 20: transceiver

30: oscillator 40: clock selector

50: gradation selector 60: display selector

70: display unit OSC1, OSC2: oscillator

SW1-SW4: Switch R1-R3: Resistance

S1, S2: Segment

Claims (14)

A programmable logic element for interfacing the grayscale and the RGB data for the grayscale according to the source clock to the liquid crystal module in a parallel manner or through a transceiver; A transceiver for inputting a signal from the programmable logic device to a liquid crystal module; An oscillator for providing first and second oscillation frequencies to the programmable logic device as a source clock signal; A clock selector for selecting one of the first and second oscillation frequencies generated from the oscillator and applied to the programmable logic element as a clock signal; A gradation selection unit for raising or lowering the gradation from a preset reference gradation; And a display selection unit for selecting a color display according to the gradation selected by the gradation selection unit. The method of claim 1, The first oscillation frequency is 66MHz, And said second oscillation frequency is 40 MHz. The method of claim 1, The clock selector may include a first switch having a first variable contact grounded, a second variable contact connected to a power supply terminal through a first resistor, and a common terminal connected to a clock select terminal of the programmable logic device. An interface circuit for pattern display of a liquid crystal display device. The method of claim 3, wherein The clock selector selects one of the first and second oscillation frequencies when the common contact of the switch is connected to the first variable contact. And a signal for selecting the other one of the first and second oscillation frequencies as a clock signal when a common contact of the switch is connected to a second variable contact. The method of claim 1, And the gradation selection unit comprises a gradation raising means for raising the gradation from the reference gradation and a gradation descending means for lowering the gradation from the reference gradation. The method of claim 5, wherein And gradation is selected through gradation increasing means or gradation descending means of the gradation selection unit, the PLD transfers RGB data for the selected gradation to a liquid crystal module or a transceiver. The method of claim 5, wherein the tone increasing means, A second switch having one end grounded and the other end connected to a gray-up terminal of the programmable logic device; An interface circuit for a pattern display of a liquid crystal display device, characterized in that a power supply voltage is applied to one end thereof and a second resistor connected to the other end of the second switch and the gray-up terminal of the programmable logic device. The method of claim 5, wherein the tone increasing means, A third switch having one end grounded and the other end connected to a gray down terminal of the programmable logic device; An interface circuit for pattern display of a liquid crystal display device, characterized in that a power supply voltage is applied to one end thereof and a third resistor connected to the other end of the third switch and the gray down terminal of the programmable logic device. The display display device of claim 1, wherein the display selection unit comprises: And a rotary switch for displaying all RGB or only one color of R, G, and B in the gradation selected by the gradation selector. The rotary switch of claim 9, wherein The common contact is connected to ground, and the first to fourth variable contacts are connected to terminals for selecting to display all RGB of the programmable logic device, and terminals for selecting to display only R, G, and B of RGB. Interface circuit for pattern display of the liquid crystal display device, characterized in that each connected. The method of claim 10, When a signal is selected to display all of the RGB by the rotary switch of the display selection unit or to select only one color of R, G, and B to be displayed in the gradation selected by the gradation selection unit, the selected color is displayed on the gradation selection unit. An interface circuit for pattern display of a liquid crystal display device, characterized by transferring data on a color selected to be represented by a gray level selected by the liquid crystal module or a transceiver. The method of claim 1, And a gradation display unit for displaying the gradation selected by the gradation selection unit. The display device of claim 12, wherein the gradation display unit comprises two digit segments, and inputs data about the gradation applied from the programmable logic device to drive the first segment according to a chip select signal applied from the programmable logic device. Wherein the tenth digit is first displayed, and then the second segment is driven to express the gray scale by a multiplexing method of representing the first digit. The method of claim 1, When the first oscillation frequency is selected as the source clock by the clock selector, the programmable logic device interfaces with the direct liquid crystal module in parallel without passing through the transceiver. And when the second oscillation frequency is selected as the source clock, the programmable logic device interfaces with the liquid crystal module through the transceiver.

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