KR100458293B1 - Post treatment method of metal interconnection of semiconductor device to avoid increase of resistance of aluminum metal interconnection and contact resistance - Google Patents

Post treatment method of metal interconnection of semiconductor device to avoid increase of resistance of aluminum metal interconnection and contact resistance Download PDF

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KR100458293B1
KR100458293B1 KR1019970071315A KR19970071315A KR100458293B1 KR 100458293 B1 KR100458293 B1 KR 100458293B1 KR 1019970071315 A KR1019970071315 A KR 1019970071315A KR 19970071315 A KR19970071315 A KR 19970071315A KR 100458293 B1 KR100458293 B1 KR 100458293B1
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metal interconnection
metal wiring
chlorine
resistance
semiconductor device
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KR1019970071315A
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KR19990051895A (en
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박정수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

PURPOSE: A post treatment method of a metal interconnection of a semiconductor device is provided to avoid an increase of resistance of an aluminum metal interconnection and contact resistance by forming the aluminum metal interconnection by an etch process using chlorine-containing plasma and by eliminating a corrosion factor and a byproduct generating factor that remain on the aluminum metal interconnection. CONSTITUTION: The chlorine radical(14) remaining on a metal interconnection formed by an etch process using chlorine-containing plasma is eliminated by a CF4 plasma process. After Ar gas of 50-200 sccm(standard cubic centimeters per minute) is introduced to a chamber of a temperature of 200 deg.C or higher, the fluorine radical(15) remaining on the metal interconnection after the CF4 plasma process is degassed from the metal interconnection by an Ar plasma process in which radio frequency of 300-600 watts is applied.

Description

반도체 소자의 금속 배선 후처리 방법Metal wiring post-processing method of semiconductor device

본 발명은 반도체 소자의 금속배선 후처리(post treatment) 방법에 관한 것으로, 특히 반도체 소자의 제조 공정중 염소계(Cl2, BCl3) 플라즈마를 이용한 식각공정으로 알루미늄 금속배선을 형성한 후, 알루미늄 금속배선의 표면에 잔존하는 부식(corrosion)요인과 부산물의 생성 요인을 제거하여, 알루미늄 금속배선의 자체 저항 및 콘택 저항이 증가되는 것을 방지할 수 있는 반도체 소자의 금속배선 후처리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a post-treatment method of a metal device for a semiconductor device. In particular, after forming an aluminum metal wire by an etching process using a chlorine (Cl 2 , BCl 3 ) plasma during the manufacturing process of the semiconductor device, The present invention relates to a post-processing method for metallization of a semiconductor device capable of preventing an increase in self-resistance and contact resistance of aluminum metallization by removing corrosion factors and by-products remaining on the surface of the interconnection.

일반적으로, 반도체 소자의 제조 공정중 금속배선 형성 공정 후에 금속배선의 전기적 저항을 증가시키는 요인을 제거하기 위하여 후처리 공정을 실시한다. 금속배선의 재료로 알루미늄이 널리 사용되고 있으며, 또한 반도체 소자의 고집적화 및 소형화에 따라 다층 금속배선 구조가 적용되고 있다.In general, a post-treatment process is performed to remove a factor of increasing the electrical resistance of the metal wiring after the metal wiring forming process in the semiconductor device manufacturing process. Aluminum is widely used as a material for metal wiring, and a multilayer metal wiring structure is applied according to high integration and miniaturization of semiconductor devices.

도 1(a) 내지 도 1(c)는 다층 금속배선 구조를 갖는 종래 반도체 소자의 금속배선 후처리 방법을 설명하기 위한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of a device for explaining a metallization post-processing method of a conventional semiconductor device having a multilayer metallization structure.

도 1(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(1)상에 제 1 층간 절연막(2)을 형성하고, 제 1 층간 절연막(2)상에 알루미늄 증착 공정 및 식각 공정으로 하부 금속배선(3)을 형성한다.Referring to FIG. 1A, a first interlayer insulating film 2 is formed on a substrate 1 having various elements for forming a semiconductor device, and an aluminum deposition process is performed on the first interlayer insulating film 2. And forming the lower metal wiring 3 by an etching process.

염소계(Cl2, BCl3) 플라즈마를 이용한 식각 공정으로 하부 금속배선(3)을 형성하는데, 형성된 하부 금속배선(3)의 표면에는 염소기(4)가 잔존하게 되고, 이 염소기(4)는 하부 금속배선(3)을 부식시키는 요인으로 작용한다.The lower metal wiring 3 is formed by an etching process using chlorine-based (Cl 2 , BCl 3 ) plasma, and the chlorine group 4 remains on the surface of the formed lower metal wiring 3. Acts as a factor to corrode the lower metal wiring (3).

도 1(b)를 참조하면, CF4플라즈마 공정으로 염소기(4)를 제거하는데, 챔버내에 CF4가스를 유입(flow)시킨 후, 고주파(RF)를 인가하여 발생되는 불소기(5)로 염소기(4)를 치환시켜 하부 금속배선(3) 표면에 잔존하는 염소기(4)를 제거한다.하부 금속배선(3) 표면에 잔존하는 염소기(4)는 제거하였지만, 하부 금속배선(3) 표면에는 불소기(5)가 잔존하게 된다.Referring to FIG. 1 (b), the chlorine group 4 is removed by a CF 4 plasma process, and the fluorine group 5 generated by applying a high frequency (RF) after flowing CF 4 gas into the chamber. The chlorine group 4 is substituted to remove the chlorine group 4 remaining on the lower metal wiring 3 surface. The chlorine group 4 remaining on the lower metal wiring 3 surface is removed, but the lower metal wiring is removed. (3) The fluorine group 5 remains on the surface.

도 1(c)를 참조하면, 하부 금속배선(3)을 포함한 전체구조상에 제 2 층간 절연막(6)을 형성하고, 금속 콘택 공정을 통해 하부 금속배선(3)과 연결되는 상부 금속배선(7)을 형성한다. 그런데, 하부 금속배선(3) 표면에 잔존하는 불소기(5)는 하부 금속배선(3)의 알루미늄과 반응하여 Al2F3라는 부산물(8)을 생성하게 되고, 이 부산물(8)은 하부 금속배선(3)과 상부 금속배선(7)의 콘택 저항을 증가시키게 되어 소자의 전기적 특성이 저하된다.Referring to FIG. 1C, the second interlayer insulating film 6 is formed on the entire structure including the lower metal wiring 3 and the upper metal wiring 7 connected to the lower metal wiring 3 through a metal contact process. ). However, the fluorine group 5 remaining on the surface of the lower metal wiring 3 reacts with aluminum of the lower metal wiring 3 to produce a byproduct 8 of Al 2 F 3, which is a lower portion of the lower metal wiring 3. The contact resistance of the metallization 3 and the upper metallization 7 is increased to degrade the electrical characteristics of the device.

부산물(8)을 생성시키는 요인인 불소기를 제거하기 위하여, 도 1(b)의 CF4플라즈마 공정 이후에 순수(DI water)로 하부 금속배선(3)을 세정하고, 스핀(spin) 방식으로 건조시킨다. 그러나, 건조가 불충분할 경우 물 얼룩(water spot)이 남게되고, 이 물 얼룩은 파티클(particle)을 유발시키는 요인으로 작용하며, 또한 순수 세정을 하더라도 불소기(5)가 완전히 제거되지 않아 콘택 저항의 증가를 초래하게 된다.In order to remove the fluorine group, which causes the by-product 8, the lower metal wiring 3 is washed with DI water after the CF 4 plasma process of FIG. 1 (b), and dried in a spin method. Let's do it. However, if the drying is insufficient, water spots are left, and the water spots act as a factor causing particles, and even with pure cleaning, the fluorine group 5 is not completely removed, resulting in contact resistance. Will cause an increase.

따라서, 본 발명은 반도체 소자의 제조 공정중 염소계(Cl2, BCl3) 플라즈마를 이용한 식각 공정으로 알루미늄 금속배선을 형성한 후, 알루미늄 금속배선의 표면에 잔존하는 부식(corrosion)요인과 부산물의 생성 요인을 제거하여, 알루미늄 금속배선의 자체 저항 및 콘택 저항이 증가되는 것을 방지할 수 있는 반도체 소자의 금속배선 후처리 방법을 제공함에 그 목적이 있다.Accordingly, the present invention forms an aluminum metal wiring by an etching process using chlorine (Cl 2 , BCl 3 ) plasma during the manufacturing process of a semiconductor device, and then generate corrosion factors and by-products remaining on the surface of the aluminum metal wiring. It is an object of the present invention to provide a metal wiring post-treatment method of a semiconductor device capable of preventing an increase in self resistance and contact resistance of an aluminum metal wiring by removing the factor.

이러한 목적을 달성하기 위한 본 발명의 금속배선 후처리 방법은 염소계 플라즈마를 이용한 식각 공정으로 형성된 금속배선의 표면에 잔존하는 염소기를 CF4플라즈마 공정으로 제거하는 단계; 및 상기 CF4플라즈마 공정후 상기 금속배선의 표면에 잔존하는 불소기를 고온의 Ar 플라즈마 공정으로 상기 금속배선으로부터 탈기시키는 단계를 포함하여 이루어지는 것을 특징으로 한다.The metallization post-processing method of the present invention for achieving the above object comprises the steps of removing the chlorine groups remaining on the surface of the metallization formed by the etching process using a chlorine-based plasma by CF 4 plasma process; And degassing the fluorine group remaining on the surface of the metal wiring after the CF 4 plasma process from the metal wiring by a high temperature Ar plasma process.

도 1(a) 내지 도 1(c)는 종래 반도체 소자의 금속배선 후처리 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of a device for explaining a metallization post-processing method of a conventional semiconductor device.

도 2(a) 내지 도 2(d)는 본 발명의 실시예에 따른 반도체 소자의 금속배선 후처리 방법을 설명하기 위한 소자의 단면도.2 (a) to 2 (d) are cross-sectional views of devices for explaining a metallization post-processing method of a semiconductor device according to an embodiment of the present invention.

＜도면의 주요 부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

1 및 11: 기판 2 및 12: 제 1 층간 절연막1 and 11: Substrate 2 and 12: First interlayer insulating film

3 및 13: 하부 금속배선 4 및 14: 염소기3 and 13: bottom metallization 4 and 14: chlorine group

5 및 15: 불소기 6 및 16: 제 2 층간 절연막5 and 15: fluorine groups 6 and 16: second interlayer insulating film

7 및 17: 상부 금속배선 8: 부산물7 and 17: upper metallization 8: by-products

18: 아르곤기18: argon

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2(a) 내지 도 2(d)는 다층 금속배선 구조를 갖는 본 발명의 실시예에 따른 반도체 소자의 금속배선 후처리 방법을 설명하기 위한 소자의 단면도이다.2 (a) to 2 (d) are cross-sectional views of devices for explaining a metallization post-processing method of a semiconductor device according to an embodiment of the present invention having a multi-layered metallization structure.

도 2(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(11)상에 제 1 층간 절연막(12)을 형성하고, 제 1 층간 절연막(12)상에 알루미늄 증착 공정 및 식각 공정으로 하부 금속배선(13)을 형성한다.Referring to FIG. 2A, a first interlayer insulating layer 12 is formed on a substrate 11 having various elements for forming a semiconductor device, and an aluminum deposition process is performed on the first interlayer insulating layer 12. And forming the lower metal wiring 13 by an etching process.

염소계(Cl2, BCl3) 플라즈마를 이용한 식각 공정으로 하부 금속배선(13)을 형성하는데, 형성된 하부 금속배선(13)의 표면에는 염소기(14)가 잔존하게 되고, 이 염소기(14)는 하부 금속배선(13)을 부식시키는 요인으로 작용한다.The lower metal wiring 13 is formed by an etching process using chlorine-based (Cl 2 , BCl 3 ) plasma, and the chlorine group 14 remains on the surface of the formed lower metal wiring 13. Acts as a factor to corrode the lower metal wiring 13.

도 2(b)를 참조하면, CF4플라즈마 공정으로 염소기(14)를 제거하는데, 챔버내에 CF4가스를 유입(flow)시킨 후, 고주파(RF)를 인가하여 발생되는 불소기(15)로염소기(14)를 치환시켜 하부 금속배선(13) 표면에 잔존하는 염소기(14)를 제거한다. 하부 금속배선(13) 표면에 잔존하는 염소기(14)는 제거하였지만, 하부 금속배선(13) 표면에는 불소기(15)가 잔존하게 된다.Referring to FIG. 2 (b), the chlorine group 14 is removed by a CF 4 plasma process, and the fluorine group 15 generated by applying a high frequency (RF) after flowing CF 4 gas into the chamber. The chlorine group 14 remaining on the surface of the lower metal wiring 13 is removed by replacing the furnace chlorine group 14. The chlorine group 14 remaining on the lower metal wiring 13 surface is removed, but the fluorine group 15 remains on the lower metal wiring 13 surface.

도 2(c)를 참조하면, 고온의 Ar 플라즈마 공정으로 불소기(15)를 탈기시키는데, 약 200℃ 이상의 온도를 유지한 챔버내에 Ar 가스를 50 내지 200sccm 유입시킨 후, 300 내지 600W의 고주파를 인가하여 발생되는 아르곤기(18)로 불소기(15)를 하부 금속배선(13)으로부터 탈기시킨다. Ar 플라즈마 공정은 약 30초 정도 실시한다.Referring to FIG. 2 (c), the fluorine group 15 is degassed by a high temperature Ar plasma process. 50 to 200 sccm of Ar gas is introduced into a chamber maintained at a temperature of about 200 ° C. or higher, and then a high frequency of 300 to 600 W is applied. The fluorine group 15 is degassed from the lower metal wiring 13 by the argon group 18 generated by application. The Ar plasma process is performed for about 30 seconds.

도 2(d)를 참조하면, 하부 금속배선(13)을 포함한 전체구조상에 제 2 층간 절연막(16)을 형성하고, 금속 콘택 공정을 통해 하부 금속배선(13)과 연결되는 상부 금속배선(17)을 형성한다.Referring to FIG. 2 (d), the second interlayer insulating layer 16 is formed on the entire structure including the lower metal interconnection 13, and the upper metal interconnection 17 connected to the lower metal interconnection 13 through a metal contact process. ).

상술한 바와 같이, 본 발명은 금속배선 식각 공정시 잔존하는 부식 요인인 염소기를 CF4플라즈마로 제거하고, CF4플라즈마 공정후에 잔존하는 불소기를 고온의 Ar 플라즈마로 탈기시키므로써, 금속배선의 자체 저항 및 콘택 저항이 증가되는 것을 방지하여 소자의 신뢰성을 향상시킬 수 있다.As described above, the present invention provides self-resistance of metal wiring by removing chlorine groups, which are corrosion factors remaining in the metal wiring etching process, by CF 4 plasma, and degassing the fluorine groups remaining after the CF 4 plasma process by high temperature Ar plasma. And it is possible to prevent the contact resistance is increased to improve the reliability of the device.

Claims (2)

염소계 플라즈마를 이용한 식각 공정으로 형성된 금속배선의 표면에 잔존하는 염소기를 CF4플라즈마 공정으로 제거하는 단계; 및Removing the chlorine group remaining on the surface of the metal line formed by the etching process using the chlorine-based plasma by the CF 4 plasma process; And 200℃ 이상의 온도를 유지한 챔버내에 Ar 가스를 50 내지 200sccm 유입시킨 후, 300 내지 600W의 고주파를 인가하여 실시되는 Ar 플라즈마 공정으로 상기 CF4플라즈마 공정후 상기 금속배선의 표면에 잔존하는 불소기를 상기 금속배선으로부터 탈기시키는 단계를 포함하여 이루어지는 것을 특징으로 반도체 소자의 금속배선 후처리 방법.50 to 200 sccm of Ar gas is introduced into the chamber maintained at a temperature of 200 ° C. or higher, and then a fluorine group remaining on the surface of the metal wiring after the CF 4 plasma process is performed by an Ar plasma process performed by applying a high frequency of 300 to 600 W. And degassing from the metal wiring. 제 1 항에 있어서,The method of claim 1, 상기 금속배선은 알루미늄으로 형성되는 것을 특징으로 하는 반도체 소자의 금속배선 후처리 방법.And the metal wiring is formed of aluminum.
KR1019970071315A 1997-12-20 1997-12-20 Post treatment method of metal interconnection of semiconductor device to avoid increase of resistance of aluminum metal interconnection and contact resistance KR100458293B1 (en)

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KR100462761B1 (en) * 2002-06-11 2004-12-20 동부전자 주식회사 Method for manufacturing metal line of semiconductor device

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JPS59210644A (en) * 1983-05-16 1984-11-29 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH0536839A (en) * 1991-07-29 1993-02-12 Nec Corp Manufacture of semiconductor device
JPH10256232A (en) * 1997-03-12 1998-09-25 Nec Corp Manufacture of semiconductor device
KR0185489B1 (en) * 1995-02-03 1999-04-15 스기야마 카즈히코 Manufacture of semiconductor device

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JPS59210644A (en) * 1983-05-16 1984-11-29 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH0536839A (en) * 1991-07-29 1993-02-12 Nec Corp Manufacture of semiconductor device
KR0185489B1 (en) * 1995-02-03 1999-04-15 스기야마 카즈히코 Manufacture of semiconductor device
JPH10256232A (en) * 1997-03-12 1998-09-25 Nec Corp Manufacture of semiconductor device

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