KR100451737B1 - Digital Micro-mirror Device Panel - Google Patents

Abstract

The present invention is to provide a DMD panel, comprising a plurality of unit pixels consisting of a plurality of sub-pixels, and time-dividing the first bit data into the first bit data by a PWM method per segment to apply to the unit pixels Each time subdivision of the first bit data is applied to each sub-pixel constituting the unit pixel, second bit data corresponding to the number of the sub-pixels is applied to turn on the sub-pixel. -Off) is provided with a driving unit for controlling the gradation process, by dividing the unit pixel into a plurality of sub-pixels to increase the screen gradation by the number of sub-pixels to increase the color realization of the DMD panel, Due to the increase in gray level, the number of sub-fields is reduced, thereby reducing the address clock speed.

Description

DMD panel {Digital Micro-mirror Device Panel}

The present invention relates to a screen gray scale processing method and driving method using a digital micro-mirror element in which unit pixels are divided.

The present invention relates to a display gray scale process and a driving method of a DMD panel used as a panel of a DLP that has recently been spotlighted by a reflective projector.

1A is a structural cross-sectional view of a unit pixel of a DMD panel according to the prior art.

As shown in Figures 1B and 1C, two address electrodes and a metal under the micro-mirror are driven by a pulse with two electrical signals, on-off. It is driven by Pulse Width Modulation (PWM).

The driving method reflects or distorts the incident light by deflecting the micro-mirror according to the polarity of the address electrode of the lower plate by a positive bias applied to the lower metal of the upper micro-mirror of the upper plate.

In FIG. 1B, an electric attraction force is applied between the address electrode and the micro-mirror lower metal to show that the micro-mirror is biased to the left.

In this state, when light enters the micro-mirror from the left side, the light path is reflected perpendicular to the direction of incidence. By this process, the output state of the external screen is turned on.

In FIG. 1C, an electric attraction force is applied between the address electrode and the micro-mirror lower metal to show a state in which the micro-mirror is deflected to the right.

In this state, when light enters the mirror to the left, the light is not reflected but becomes distorted. By this process, the output state of the external screen is turned off.

The DMD panel does not have analog nonlinear electro-optic characteristics and uses only on-off digital signals.

When using a DMD panel as a display panel, it is necessary to express the gradation of the screen using the PWM method. For example, the projector divides the color wheel into segments of red, green, blue, and white and segments the screen using the time division PWM method.

Since this method uses 8-bit image signals in each segment, there is a problem that a high-speed clock is used when using the time division PWM method.

In addition, such a simple PWM driving method causes problems such as false contour noise, which degrades the image quality. Therefore, image information must be uniformly distributed through sub-field expansion and rearrangement.

Figure 2a is a PWM driving method initially proposed in the field of PDP.

The gradation representation method of the PWM method expresses gradation by accumulating the upper bit to the lower bit for one gradation. For example, gradation expression is performed by time division by dividing a frame of one field into eight sub-field frames. Do it.

This PWM method displays gradations according to the time for projecting light. Therefore, for example, when expressing gradations with 8 bits, the upper bits have a long time for projecting light and the lower bits have a time for projecting light. It will be short.

In this case, when the clock speed is high, the lower bit may have a shorter projection time, which may cause a gray level problem.

FIG. 2B illustrates a first field and a second field continuously generated in the moving picture.

For example, in FIG. 2B, all values (1, 2, 3, 4, 5, 6, and 7) except for the MSB value 8 of the first field and the MSB of the second field subsequent to each other may have a Hi value. In this case, the image information felt by the retina has 256 values. Due to this phenomenon, the image information value is distorted, resulting in false contour noise.

In order to solve this problem, the contour noise can be compensated by extending the 8-bit image information to 13 bits and rearranging the display time.

When this method is used for DMD, contour noise can be removed to some extent, but there is a problem that a high speed address is required.

In particular, since the time allocated to each RGBW segment is small in DMD, it can be seen that there are many problems in addressing and many problems in efficient contour noise removal.

Accordingly, the present invention has been made to solve the above-mentioned problems, and increases the time allocated to each RGBW segment to enable efficient addressing. The purpose is to provide a removed DMD panel.

1A is a structural cross-sectional view of a unit pixel of a DMD panel according to the prior art.

1B and 1C are operation diagrams of unit pixels of the DMD panel shown in FIG. 1A.

FIG. 2A illustrates a PWM driving scheme initially proposed in the PDP field.

3A is a diagram conceptually illustrating a unit pixel of a DMD according to the present invention.

3B illustrates each sub-pixel driver of the DMD panel for driving the unit pixel of FIG. 3A according to the present invention.

FIG. 3C is a diagram of applying a signal for driving a unit pixel by using each sub-pixel driver of the DMD panel shown in FIG. 3B.

FIG. 4A illustrates a sub-pixel structure of a DMD panel according to the present invention, and FIG. 4B is a view schematically illustrating the AA ′ direction of FIG. 4A.

5 is a conceptual diagram illustrating screen gray scale processing of unit pixels of a DMD panel according to the present invention.

* Explanation of symbols for main parts of the drawings

10: latch 11: inverter

20: DMD sub-pixel 22, 24: hinge

26 mirrors 28 and 30 address electrodes

32: insulating layer 34: silicon substrate

36 spacer 38 hinge metal layer

39: mirror metal layer

Features of the DMD panel according to the present invention for achieving the above object is a hinge, a hinge formed to face one side of the mirror, a hinge metal layer connected to the hinge around the mirror, the hinge metal layer is formed simultaneously with the hinge, the hinge A mirror metal layer formed simultaneously with the mirror, a mirror, a hinge, a hinge metal layer, and a mirror metal layer formed on a metal layer, formed on an insulating layer formed on a silicon substrate, and formed on the insulating layer on both sides of the lower side of the hinge axis, A unit consisting of a plurality of sub-pixels comprising an address electrode biased by the driving unit to deflect the mirror and a spacer connected to the hinge metal layer and the mirror metal layer on the insulating layer to support the hinge metal layer and the mirror metal layer PWM system with a plurality of pixels and the first bit data per segment A latch which is time-divided into the first bit data to be applied to the unit pixel, and is provided for each of the sub-pixels, and inputs and stores second bit data of the sub-pixels according to a clock and outputs the second bit data according to the clock; And an inverter for inputting and inverting the second data output from the latch of the sub-pixel, one for each sub-pixel, to each sub-pixel constituting the unit pixel. The apparatus may include a driver configured to apply second bit data corresponding to the number of sub-pixels each time-division application to control the sub-pixels on-off and to perform gradation processing.

The driving unit is provided with one for each sub-pixel, the latch for inputting and storing the second bit data of the sub-pixel in accordance with the clock and output according to the clock; One inverter for each sub-pixel, the inverter configured to input and invert the second data output from the latch of the sub-pixel, and output the latch to the address electrode through an address line connected to the address electrode; And biasing the mirror by applying a corresponding bias according to the output of the inverter and maintaining the deflection state until the next second bit data is input.

In this case, the second bit data may be applied to each of the latches simultaneously.

According to an aspect of the present invention, for one segment of RGBW, for example, the first bit data having a size of 6 bits is time-divided to perform screen gradation processing of a unit pixel, and the second bit dependent on each of the first bit data. By setting the data size to 2 bits, the unit pixel is divided into 2 bits, that is, 4 sub-pixels, and the sub-pixels are controlled on-off to increase the screen gradation level by the number of sub-pixels to perform screen gradation processing. In addition, 256-bit grayscale processing of video data (8bit) can be performed, and accurate implementation of the lower bits can be enabled even by driving a high speed clock speed, which is required for the accurate implementation of the conventionally allocated lower time bits. .

That is, if one segment of a unit pixel is time-divided into 6 bits for screen gradation processing and on-off using four sub-pixels, not only is it possible to process 2 bits of screen gradation but also 8 bits as conventional Since two bits are reduced compared to the time division method, a lower speed address is possible.

In addition, due to the low speed address, it is possible to eliminate the contour noise causing the deterioration of image quality due to the high speed clock.

In addition, the memory characteristics are given to reduce the address line and maintain the deflection state by using a latch and an inverter to enable efficient addressing.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

A preferred embodiment of the DMD panel according to the present invention will be described with reference to the accompanying drawings.

3A is a diagram conceptually illustrating a unit pixel of a DMD panel according to the present invention.

As shown in Fig. 3A, the unit pixel of the DMD panel is composed of four sub-pixels of pixel 1, pixel 2, pixel 3, and pixel 4.

FIG. 4A shows the sub-pixel structure of the DMD panel according to the present invention, and FIG. 4B shows the A-A 'direction of FIG. 4A briefly.

The sub-pixel structure of the DMD panel will be described with reference to FIGS. 4A and 4B as follows.

The deflection beam DMD sub-pixel 20 has a mirror 26, hinges 22 and 24 formed opposite to one side of the mirror 26, and connected to the hinges 22 and 24 around the mirror 26. A hinge metal layer 38 formed simultaneously with the hinges 22 and 24, a mirror metal layer 39 formed simultaneously with the mirror 26 on the hinge metal layer 38, and a lower portion of the mirror 26. The silicon substrate 34, the insulating layer 32 formed on the silicon substrate 34, and the insulating layers 32 on both sides of the lower sides of the hinges 22 and 24, respectively. Address electrodes 28 and 30 for biasing the mirror 26 by a bias) and a hinge metal layer connected to the hinge metal layer 38 and the mirror metal layer 39 on the insulating layer 32. And a spacer 36 supporting the mirror metal layer 39.

After etching the mirror metal layer 39 and the hinge metal layer 38, the hinges 22 and 26 and the spacer 36 under the mirror 26 are removed to remove the sub-pixels of the DMD panel as shown in FIGS. 4A and 4B. 20) can be obtained.

3B illustrates each sub-pixel driver of the DMD panel for driving the unit pixel of FIG. 3A according to the present invention.

As shown in Fig. 3B, each sub-pixel 20 is driven by one latch 10 and a drive driven by an inverter 11.

Data dat input to each latch 10 is transferred to the address line through the inverter 11 and the line. The transferred data deflects the mirror 26 by the characteristics of the latch 10 and remains deflected until the next data signal is input.

This method is used in combination with the PWM method, and the clock frequency can be lowered than the conventional PWM method, and data processing for the screen gray scale processing becomes easy.

FIG. 3C is a diagram of applying a signal for driving a unit pixel by using each sub-pixel driver of the DMD panel shown in FIG. 3B.

As shown in Fig. 3c, when D1 = L, D2 = H, D3 = H, and D4 = H and sampling using Clock, the data is L in latch 1, H in latch 2, H in latch 3, and latch. H is stored at 4.

At this time, when the data dat input to each latch 10 is transferred to the address line through the inverter 11 and the line, in pixel 1, the electrical attraction between the mirror A and the address electrode A1 and the mirror A ) And the address electrode A2 act to bias the mirror A toward A1, and to the mirrors B, C, and D toward B2, C2, D2.

At this time, when the incident direction of light is from left to right, A reflects light to turn on the output, and B, C, and D distort light to turn off the output.

Here, the H and L values become positive and negative biases at the output unit. For the purpose of explaining the concept only, the part related to bias is omitted. As a method for screen gray level processing, PWM and sub-pixels are used.

5 is a conceptual diagram illustrating screen gray scale processing of unit pixels of a DMD panel according to the present invention.

If one segment of RGBW is time-divided into 6 bits for screen gradation processing and on-off is performed using four sub-pixels, 2 bits of screen gradation processing is possible.

Using this method, video data (8bit) 256 screen gradation processing is possible, and the clock speed can be improved.

The DMD panel according to the present invention as described above has the following effects.

When the unit pixel is divided into a plurality of sub-pixels, the screen gray level is increased by the number of sub-pixels, thereby improving color realization of the DMD panel.

In addition, the number of sub-fields is reduced by increasing the gray level due to the increase of sub-pixels, thereby reducing the address clock speed.

In addition, a latch and an inverter are used to reduce address lines and maintain deflection to enable efficient addressing.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (5)

A mirror, a hinge formed facing one side of the mirror, a hinge metal layer connected to the hinge around the mirror and formed simultaneously with the hinge, a mirror metal layer formed simultaneously with the mirror on the hinge metal layer, the mirror, the hinge, An address layer formed below the hinge metal layer and the mirror metal layer, formed on an insulating layer formed on the silicon substrate, one on the insulating layer on both sides of the lower side of the hinge axis, and biased by the driver to bias the mirror; A plurality of unit pixels including a plurality of sub-pixels formed of spacers connected to the hinge metal layer and the mirror metal layer to support the hinge metal layer and the mirror metal layer on the insulating layer, and the first bit data per segment Time-divided into the first bit data to apply to the unit pixel, One latch for each sub-pixel, and one latch for inputting and storing second bit data of the sub-pixel according to a clock and outputting the second bit data according to the clock, and one latch for the sub-pixel, A second bit corresponding to the number of sub-pixels each time-division application of the first bit data is applied to each sub-pixel constituting the unit pixel by inputting and inverting the second data outputted from the second pixel; And a driver configured to apply data to control the sub-pixels on-off and to perform gradation processing. delete delete The method of claim 1, wherein the driving unit A latch provided for each of the sub-pixels and configured to input and store second bit data of the sub-pixels according to a clock and output the second bit data according to the clock; One inverter for each sub-pixel, and configured to input and invert the second data output from the latch of the sub-pixel, By applying a corresponding bias according to the output of the latch and the output of the inverter through the address line connected to the address electrode, the mirror is deflected, and the deflection state is maintained until the next second bit data is input. DMD panel, characterized in that. 5. The DMD panel of claim 4, wherein the second bit data is simultaneously applied to each latch.