KR100444172B1 - multi chip semiconductor package - Google Patents

multi chip semiconductor package Download PDF

Info

Publication number
KR100444172B1
KR100444172B1 KR10-2001-0087583A KR20010087583A KR100444172B1 KR 100444172 B1 KR100444172 B1 KR 100444172B1 KR 20010087583 A KR20010087583 A KR 20010087583A KR 100444172 B1 KR100444172 B1 KR 100444172B1
Authority
KR
South Korea
Prior art keywords
semiconductor package
semiconductor
chip
semiconductor chip
present
Prior art date
Application number
KR10-2001-0087583A
Other languages
Korean (ko)
Other versions
KR20030057194A (en
Inventor
손영호
박계찬
Original Assignee
동부전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부전자 주식회사 filed Critical 동부전자 주식회사
Priority to KR10-2001-0087583A priority Critical patent/KR100444172B1/en
Publication of KR20030057194A publication Critical patent/KR20030057194A/en
Application granted granted Critical
Publication of KR100444172B1 publication Critical patent/KR100444172B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 반도체 칩이 탑재된 반도체 패키지 내부에 또다른 반도체 칩이 탑재된 반도체 패키지를 직각으로 세워 결합할 수 있도록 하므로 기울기를 감지함과 동시에 또 다른 다양한 전기적인 신호를 외부와 상호 전달할 수 있도록 하므로 소형화 및 집적화를 실행할 수 있는 잇점을 갖는 멀티 칩 반도체 패키지에 관한 것이다.According to the present invention, the semiconductor package in which the semiconductor chip is mounted may be coupled to the semiconductor package in which the semiconductor chip is mounted at a right angle, thereby detecting a tilt and simultaneously transferring another various electrical signals to the outside. The present invention relates to a multi-chip semiconductor package having an advantage of miniaturization and integration.

Description

멀티 칩 반도체 패키지{multi chip semiconductor package}Multi chip semiconductor package

본 발명은 멀티 칩 반도체 패키지에 관한 것으로서, 더 자세하게는 반도체 칩이 탑재된 반도체 패키지 내부에 또다른 반도체 칩이 탑재된 반도체 패키지를 직각으로 세워 결합할 수 있도록 하므로 기울기를 감지함과 동시에 또 다른 다양한 전기적인 신호를 외부와 상호 전달할 수 있도록 하므로 소형화 및 집적화를 실행할수 있도록 하는 멀티 칩 반도체 패키지에 관한 것이다.The present invention relates to a multi-chip semiconductor package, and more particularly, it is possible to combine a semiconductor package mounted with another semiconductor chip at a right angle inside the semiconductor package on which the semiconductor chip is mounted so as to detect a tilt and at the same time The present invention relates to a multi-chip semiconductor package capable of carrying out miniaturization and integration since electrical signals can be transmitted to and from the outside.

최근 반도체칩의 급속한 고집적화 및 소형화 추세에 따라 전자기기나 가전제품들도 소형화되고 있고, 이러한 추세에 따라 반도체패키지의 크기도 반도체칩의 크기로 축소되고 있다. 이와 같이 반도체칩의 크기로 축소된 반도체패키지로서는 여러 종류가 있으나 대표적으로 칩싸이즈(Chip size) 반도체패키지, 마이크로 볼그리드어레이(Micro ball grid array) 반도체패키지 등이 있으며, 이중에서도 상기 마이크로 볼그리드어레이 반도체패키지는 초소형의 반도체칩에 역시 초소형의 가요성회로기판을 접착하고 봉지재로 감싼 반도체패키지로서 초소형의 전자기기나 부품 등에 많이 사용되고 있다.Recently, electronic devices and home appliances are becoming smaller due to the rapid integration and miniaturization of semiconductor chips, and the size of the semiconductor packages is being reduced to the size of the semiconductor chips. As described above, there are many kinds of semiconductor packages reduced to the size of semiconductor chips, but there are representative chip size semiconductor packages, micro ball grid array semiconductor packages, and the like. The semiconductor package is a semiconductor package that is also bonded to an ultra-small semiconductor chip and is also a semiconductor package wrapped with an encapsulant, which is widely used for microelectronic devices and components.

이와 같이 소형화 및 집적화를 실행하기 위한 종래의 기술을 첨부된 도면 도 1을 참조하여 설명하면, 전자기기나 가전제품등의 기울기를 감지할 목적으로 사용하기 위해 미세한 회로기판(2)과 리드 프레임(3)만으로 이루어져 수지봉지재(1)가 둘러 싸여 있는 메인 반도체 패키지(8)의 내부에 상하로 세워진 또 다른 부 반도체 패키지(9) 반도체 칩(6)의 전기적인 신호를 상호 전달할 수 있도록 회로기판(5)을 연결하고, 회로기판(5)의 좌우측에는 외부의 전기적인 신호가 전달할 수 있도록 리드프레임(4)이 연결되어 있다.As described above with reference to the accompanying drawings of the prior art for carrying out the miniaturization and integration, the fine circuit board 2 and the lead frame (2) for use for the purpose of detecting the inclination of electronic devices or home appliances, etc. 3) a circuit board capable of mutually transferring electrical signals of another semiconductor package 9, a semiconductor chip 6, which is made up and down, in a main semiconductor package 8 surrounded by a resin encapsulant 1 only. (5) is connected, and the lead frame 4 is connected to the left and right sides of the circuit board 5 so that an external electric signal can be transmitted.

한편, 부 반도체 패키지(9)는 내부의 반도체 칩(6)을 중심으로 아래에는 회로기판(5)이 연결되어 있으며, 상기 반도체 칩(6)의 전기적인 신호가 외부와 상호 전달될 수 있도록 와이어(7)를 매개로 좌우측 끝단의 리드프레임(4)가 연결될 수 있도록 되어 있다.On the other hand, the sub-semiconductor package 9 has a circuit board 5 connected to the bottom of the semiconductor chip 6 therein, and wires are used so that electrical signals of the semiconductor chip 6 can be transmitted to the outside. The lead frame 4 at the left and right ends can be connected via (7).

이와 같이 구성된 종래의 기술은 부 반도체 패키지(9)의 반도체 칩(6)을 직각으로 세워 몰딩하기 위해 먼저 메인 반도체 패키지(8)에 회로기판(2)를 연결하고 부 반도체 패키지(9)의 몰딩작업과 트림을 실행한 후 부 반도체 패키지(9)가 직각으로 세워진 상태에서 전체적으로 몰딩작업하는 순서를 실행하였다.In the conventional technology configured as described above, in order to mold the semiconductor chip 6 of the secondary semiconductor package 9 at right angles, the circuit board 2 is first connected to the main semiconductor package 8, and the molding of the secondary semiconductor package 9 is performed. After the work and trim were executed, the entire molding operation was executed with the sub-semiconductor package 9 standing upright.

이로 인해 종래의 기술은 반도체 칩이 단일 개수만을 부착시키 되므로 기울기를 감지하는 전기적인 신호 이외의 다양한 신호를 얻어내지 못하게 되어 집적화 및 소형화할 수 없는 등의 문제점을 가지고 있다.For this reason, the prior art has a problem in that since a single number of semiconductor chips are attached, various signals other than an electrical signal for detecting a tilt cannot be obtained, and thus, integration and miniaturization cannot be achieved.

본 발명은 이와 같은 종래의 제반 문제점을 해결하기 위기 위한 것으로서 그 목적은 반도체 칩이 탑재된 반도체 패키지 내부에 또 다른 반도체 칩이 탑재된 반도체 패키지를 직각으로 세워 결합할 수 있도록 하므로 기울기를 감지함과 동시에 또 다른 다양한 전기적인 신호를 외부와 상호 전달할 수 있도록 하므로 소형화 및 집적화를 실행할 수 있도록 하는 데 있다.The present invention is to solve such a conventional problem, the object of the present invention is to detect the inclination because it can be coupled to the semiconductor package mounted with another semiconductor chip at a right angle inside the semiconductor package on which the semiconductor chip is mounted. At the same time, it is possible to carry out other various electrical signals to the outside, so that miniaturization and integration can be executed.

도 1은 종래의 기울기 감지용 반도체 패키지의 단면 구성도이다.1 is a cross-sectional view of a conventional semiconductor package for detecting tilt.

도 2는 본 발명의 실시예에 따른 멀티 팁 반도체 패키지의 단면구성도이다.2 is a cross-sectional view of a multi-tip semiconductor package according to an embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 몰딩된 반도체 패키지가 부착된 멀티 칩 반도체 패키지의 단면구성도이다.3 is a cross-sectional view of a multi-chip semiconductor package with a molded semiconductor package according to an embodiment of the present invention.

-도면의 주요부분에 대한 부호설명-Code descriptions for the main parts of the drawings

1,15,25;수지봉지재 2,5,11,22;회로기판1,15,25; resin encapsulant 2,5,11,22; circuit board

3,4,14,24;리드 프레임 6,12,21;반도체 칩3,4,14,24; lead frames 6,12,21; semiconductor chips

7,13,23;와이어 8,10;메인반도체 패키지7,13,23; wire 8,10; main semiconductor package

9,20;부 반도체 패키지9,20; secondary semiconductor package

이하, 이 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 이 발명을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 이 발명의 가장 바람직한 실시예를 첨부된 도면을 참조로 하여 상세히 설명하기로 한다. 이 발명의 목적, 작용, 효과를 포함하여 기타 다른 목적들, 특징점들, 그리고 동작상의 이점들이 바람직한 실시예의 설명에 의해 보다 명확해질 것이다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings in order to describe in detail enough to enable those skilled in the art to easily carry out the present invention. . Other objects, features, and operational advantages, including the object, operation, and effect of the present invention will become more apparent from the description of the preferred embodiment.

참고로, 여기에서 개시되는 실시예는 여러가지 실시가능한 예중에서 당업자의 이해를 돕기 위하여 가장 바람직한 예를 선정하여 제시한 것일 뿐, 이 발명의 기술적 사상이 반드시 이 실시예에만 의해서 한정되거나 제한되는 것은 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 다양한 변화와 변경이 가능함은 물론, 균등한 타의 실시예가 가능함을 밝혀 둔다.For reference, the embodiments disclosed herein are only presented by selecting the most preferred examples to help those skilled in the art from the various possible examples, the technical spirit of the present invention is not necessarily limited or limited only to this embodiment. However, various changes and modifications are possible within the scope without departing from the technical spirit of the present invention, as well as other equivalent embodiments.

본 발명은 복수 이상의 반도체 칩을 실장할 수 있으며 반도체 패키지 내부에 다른 반도체 패키지를 직각으로 세워 몰딩시킬 수 있는 기술에 관한 것으로서, 도 2 도는 도 3에서 보는 바와 같이 미세한 회로패턴이 형성된 회로기판(11) 상단에 탑재된 반도체 칩(12)과, 상기 반도체 칩(12)의 전기적인 신호를 외부와 상호 전달할 수 있도록 와이어(13)가 연결된 리드프레임(14)이 연결되는 메인 반도체 패키지(10)를 갖는다.The present invention relates to a technology capable of mounting a plurality of semiconductor chips and molding the other semiconductor package upright inside the semiconductor package, as shown in FIG. 2 or 3, a circuit board 11 having a fine circuit pattern is formed. The main semiconductor package 10 to which the semiconductor chip 12 mounted on the top and the lead frame 14 to which the wire 13 is connected are connected so as to transfer the electrical signal of the semiconductor chip 12 to the outside. Have

상기 메인반도체패키지(10)의 내측 반도체 칩(12) 측부에는 부 반도체 패키지(20)가 연결되어 있다.The sub-semiconductor package 20 is connected to the inner side of the semiconductor chip 12 of the main semiconductor package 10.

상기 부 반도체 패키지(20)는 기울기를 감지하여 전기적인 신호를 출력할 수 있도록 하는 반도체 칩(21)을 중심으로 아래에는 미세한 회로 패턴이 형성된 회로기판(22)이 연결되어 있다.The sub-semiconductor package 20 is connected to a circuit board 22 having a fine circuit pattern formed below the center of the semiconductor chip 21 to detect an inclination and output an electrical signal.

또한 부 반도체 패키지(20)는 별도로 몰딩이 이루어질 수 있도록 상기 회로 기판(22) 에 탑재된 반도체 칩(21)의 좌우측에 와이어(23) 본딩되어 전기적인 신호를 메인반도체 패키지(10)와 상호 전달될 수 있도록 하는 리드 프레임(24)과, 상기 반도체 칩(21)의 외주면을 둘러 싸아 보호할 수 있도록 충진되는 수지봉지재(25)가 형성되는 구성을 갖는다.In addition, the sub-semiconductor package 20 is wire 23 bonded to the left and right sides of the semiconductor chip 21 mounted on the circuit board 22 so that molding can be performed separately, thereby transferring an electrical signal to the main semiconductor package 10. The lead frame 24 and the resin encapsulant 25 filled to surround and protect the outer circumferential surface of the semiconductor chip 21 may be formed.

이와 같이 구성되는 본 발명의 작용효과를 상세히 설명하면 다음과 같다.Referring to the effects of the present invention configured as described in detail as follows.

본 발명은 복수 이상의 반도체 칩을 실장할 수 있으며 반도체 패키지 내부에 다른 반도체 패키지를 직각으로 세워 몰딩시킬 수 있는 기술에 관한 것으로서, 도 2 또는 도 3에서 보는 바와 같이 미세한 회로패턴이 형성된 회로기판(11)의 상단에 반도체 칩(12)을 탑재하고 그 반도체 칩(12)의 측부에는 직각으로 또 다른 반도체 칩(21)과 회로기판(22)을 결합하게 된다.The present invention relates to a technology capable of mounting a plurality of semiconductor chips and to mold the other semiconductor package upright in the semiconductor package, as shown in Figure 2 or 3, the circuit board 11 is formed with a fine circuit pattern The semiconductor chip 12 is mounted on the upper end of the c), and another semiconductor chip 21 and the circuit board 22 are coupled to the side of the semiconductor chip 12 at a right angle.

여기서, 상기 직각으로 세워진 반도체 칩(21)은 전자기기나 가전제품등에서 기울기 등을 감지할 수 있는 것으로 한다.Here, the semiconductor chip 21, which is erected at right angles, is capable of detecting a tilt or the like in an electronic device or a home appliance.

또한, 상기 수평으로 연결된 반도체 칩(12)과 직각으로 세워진 반도체 칩(21)간에 전기적인 신호를 상호 전달할 수 있도록 와이어(13)를 상호 연결하여 리드 프레임(14)에 제공하는 것이다.In addition, the wires 13 are interconnected to the lead frame 14 so as to transfer electrical signals between the horizontally connected semiconductor chips 12 and the semiconductor chips 21 that are perpendicular to each other.

한편, 본 발명은 메인반도체패키지(10) 내부에 몰딩된 부 반도체 패키지(20)의 반도체 칩(21)을 탑재할 수 있도록 하기 위해 첨부도면 도 3에서 보는 바와 같이 미세한 회로패턴(22)이 형성된 회로기판(22)의 상단에 반도체 칩(21)을 탑재하고 그 반도체 칩(21)의 측부에는 직각으로 몰딩된 부 반도체 패키지(20)를 탑재하는 것이다.Meanwhile, in the present invention, in order to mount the semiconductor chip 21 of the secondary semiconductor package 20 molded in the main semiconductor package 10, as shown in FIG. 3, a fine circuit pattern 22 is formed. The semiconductor chip 21 is mounted on the upper end of the circuit board 22, and the secondary semiconductor package 20 molded at right angles is mounted on the side of the semiconductor chip 21.

여기서, 몰딩된 부 반도체 패키지(20)는 메인반도체패키지(10)의 반도체 칩(12)의 측부에 직각으로 세워져 탑재될 수 있도록 부 반도체 패키지(20)의 리드 프레임(14)을 트림하여 회로기판(11)의 긴밀한 결합이 이루어질 수 있도록 한다.Here, the molded sub-semiconductor package 20 trims the lead frame 14 of the sub-semiconductor package 20 so that the molded sub-semiconductor package 20 can be mounted on the side of the semiconductor chip 12 of the main semiconductor package 10 at a right angle. Allow close coupling of (11) to be achieved.

이와 같이 작용하는 본 발명은 반도체 칩이 탑재된 반도체 패키지 내부에 또다른 반도체 칩이 탑재된 반도체 패키지를 직각으로 세워 결합할 수 있도록 하므로 기울기를 감지함과 동시에 또 다른 다양한 전기적인 신호를 외부와 상호 전달할 수 있도록 하므로 소형화 및 집적화를 실행할 수 있는 잇점을 갖는다.The present invention that acts as described above allows the semiconductor package on which the semiconductor chip is mounted to be coupled at a right angle to the semiconductor package on which the semiconductor chip is mounted, thereby detecting a tilt and simultaneously transferring another various electrical signals to the outside. Since it can be delivered, it has the advantage of miniaturization and integration.

Claims (2)

반도체 패키지(10) 내부에 또 다른 반도체 패키지(20)가 직각으로 세워지는 반도체 패키지에 있어서, 상기 직각으로 세워진 반도체 패키지(20)의 내부 반도체 칩(21)이 수평으로 형성된 반도체 패키지(10)의 회로기판(11)에 반도체 칩(12)을 탑재한 후 측부에 연결될 수 있도록 하는 멀티 칩 반도체 패키지.In a semiconductor package in which another semiconductor package 20 is erected perpendicularly inside the semiconductor package 10, the semiconductor package 10 of the semiconductor package 10 in which the internal semiconductor chips 21 of the semiconductor package 20 erected at right angles are horizontally formed. The multi-chip semiconductor package to be connected to the side after mounting the semiconductor chip 12 on the circuit board (11). 제 1항에 있어서, 상기 수평으로 탑재된 반도체 칩(12) 측부에 직각으로 세워진 반도체 칩(21)이 수지봉지재(25)에 의해 몰딩되어 연결될 수 있도록 상기 반도체 칩(21)의 전기적인 신호를 상호 전달할 수 있도록 와이어가 몰딩되며 절단 처리된 리드 프레임(24)이 연결되어 이루어진 멀티 칩 반도체 패키지.The electrical signal of the semiconductor chip 21 according to claim 1, wherein the semiconductor chip 21 perpendicular to the horizontally mounted side of the semiconductor chip 12 is molded by the resin encapsulant 25 and connected thereto. The multi-chip semiconductor package is formed by connecting the lead frame 24 is molded with a cutting wire so as to transfer to each other.
KR10-2001-0087583A 2001-12-28 2001-12-28 multi chip semiconductor package KR100444172B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-2001-0087583A KR100444172B1 (en) 2001-12-28 2001-12-28 multi chip semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2001-0087583A KR100444172B1 (en) 2001-12-28 2001-12-28 multi chip semiconductor package

Publications (2)

Publication Number Publication Date
KR20030057194A KR20030057194A (en) 2003-07-04
KR100444172B1 true KR100444172B1 (en) 2004-08-11

Family

ID=32215310

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-0087583A KR100444172B1 (en) 2001-12-28 2001-12-28 multi chip semiconductor package

Country Status (1)

Country Link
KR (1) KR100444172B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0357251A (en) * 1989-07-26 1991-03-12 Hitachi Ltd Semiconductor device
JPH0555273A (en) * 1991-08-28 1993-03-05 Nec Corp Resin-sealed semiconductor device
JPH0661406A (en) * 1991-02-08 1994-03-04 Toshiba Corp Semiconductor device, its manufacture, and tape carrier
KR19980061616A (en) * 1996-12-31 1998-10-07 김광호 Stacked chip package with chip-on-chip structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0357251A (en) * 1989-07-26 1991-03-12 Hitachi Ltd Semiconductor device
JPH0661406A (en) * 1991-02-08 1994-03-04 Toshiba Corp Semiconductor device, its manufacture, and tape carrier
JPH0555273A (en) * 1991-08-28 1993-03-05 Nec Corp Resin-sealed semiconductor device
KR19980061616A (en) * 1996-12-31 1998-10-07 김광호 Stacked chip package with chip-on-chip structure

Also Published As

Publication number Publication date
KR20030057194A (en) 2003-07-04

Similar Documents

Publication Publication Date Title
US6492726B1 (en) Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US7190062B1 (en) Embedded leadframe semiconductor package
US6339255B1 (en) Stacked semiconductor chips in a single semiconductor package
US8703599B2 (en) Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts
US6469395B1 (en) Semiconductor device
US7968807B2 (en) Package having a plurality of mounting orientations
US5969416A (en) Ball grid array semiconductor package
KR100444172B1 (en) multi chip semiconductor package
US20050224936A1 (en) Chip package structure
KR100351922B1 (en) Semiconductor package amd method of manufacturing the same
KR100444164B1 (en) multi chip semiconductor package
KR100444175B1 (en) ball grid array of stack chip package
KR20030056218A (en) Stack type semiconductor package
KR100373149B1 (en) Semiconductor package
KR100478202B1 (en) ultra semiconductor package
KR100708050B1 (en) semiconductor package
KR100444173B1 (en) cube type of semiconductor package
KR100567045B1 (en) A package
KR100216065B1 (en) Multi-lead on chip package
KR100461012B1 (en) ultra thine pin for semiconductor package
US20020145190A1 (en) Arrangement and method of arrangement of stacked dice in an integrated electronic device
KR200241482Y1 (en) structure of SBGA package
KR0164130B1 (en) Multi die plastic package
KR19990033884A (en) VISAI Semiconductor Package
KR20000061707A (en) A Package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110719

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20120726

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee