KR100442815B1 - Single electron transistor formed by porous silicon and fabricating method thereof - Google Patents

Abstract

PURPOSE: A single electron transistor and a fabricating method thereof are provided to improve reproducibility and homogeneity of a size of an island by using porous silicon as the island of the single electron transistor. CONSTITUTION: A porous silicon layer(40) including apertures having diameters less than 5nm is formed on a substrate(10). A source(20) and a drain(30) are formed on both sides of the porous silicon layer by using a metal. An insulating layer(50) is formed on the porous silicon layer by using an oxide. A gate(60) is formed on the insulating layer. The substrate is formed with an SOI substrate. A thickness of the porous layer is less than 10nm.

Description

Single-electron transistor using porous silicon and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single electron transistor prepared by applying porous silicon of tens of nanometers size obtained by electrochemically corroding silicon and a method of manufacturing the same.

1A and 1B are schematic vertical cross-sectional views of a conventional single electronic transistor. A conventional single electron transistor has two tunnel barriers 5 between a source 2 and a drain 3 on a silicon substrate 1, as shown in FIG. 1A. Or an island 4 formed thereon, or as shown in FIG. 1B, a source (on the top surface of the SOI substrate 11 having the SiO ₂ insulating film 11b formed on the silicon substrate 11a). 12) and the drain 13, and then granular in nanometer size (nm) by metallization (e.g. PVD) or chemical (e.g. CVD) deposition in the dielectric 15. This is a structure in which the island 14 is formed.

However, according to reference T. Wada et al Jpn. J. Appl. Phys 34,12B (1995) 6961, the size of the island 15 is uniform to nanometer size for a single electronic transistor as shown in FIG. Is very difficult to control. In particular, according to K. Matsumoto et al Appl. Phys. Lett 68 (1996) 34, when scanning probe microscopy (SPM) is applied, the tunnel barrier is degraded in air, so there is no operational reproducibility of a single electron transistor. And according to references W. Chen et al Appl. Phys. Lett 66 (1995) 3383 and A. Dutta etal Jpn. J. Appl. Phys 36,6B (1997) 4038, the use of a single electronic transistor as shown in FIG. In this case, it is difficult to reproducibly control the distance between the source 12 and the drain 13 determining the number of islands 14 and the manufacturing process is complicated because the process itself is complicated. Thus, implementing reproducible, room temperature operated single-electron transistors requires a simple process and a new structure and fabrication method that can easily control the size of the island to nanometers.

SUMMARY OF THE INVENTION The present invention has been made to improve the above problems, and an object thereof is to provide a single-electron transistor using pore silicon and a method of manufacturing the same, which are operated at room temperature and can be applied to next generation ultra high density (1Tb) memory and logic.

1A and 1B are schematic vertical cross-sectional views of a conventional single electron transistor,

2 is a vertical cross-sectional view of a single electron transistor using pore silicon according to the present invention;

3A and 3B are vertical cross-sectional views after a step-by-step process of manufacturing a single electron transistor using the pore silicon of FIG.

4A to 4C are vertical cross-sectional views after another step-by-step process of manufacturing a single electron transistor using the pore silicon of FIG.

5 is a vertical cross-sectional view of a single electron transistor using another pore silicon according to the present invention;

6a to 6c are vertical cross-sectional views after the step-by-step process of manufacturing a single electron transistor using the pore silicon of FIG.

7A to 7C are vertical cross-sectional views after another manufacturing step process of the single-electron transistor using the pore silicon of FIG. 5.

<Description of the symbols for the main parts of the drawings>

1. Silicon Substrate 2. Source

3. drain 4. island

5. Tunnel barrier

11a. Silicon substrate 11b. SiO ₂ insulating film

11. SOI Substrate 12. Source 12

13. Drain 14. Island

15. Dielectric.

10. SOI substrate 20. Source

30. Drain 40. Pore Silicon Layer

41.Porosity 42.Silicone

50. Insulation layer 60. Gate

100. SOI substrate 200. Source

300. Drain 400. Pore Silicon Layer

410. Pore 420. Silicon

500. Insulation Layer 600. Gate

In order to achieve the above object, a single electron transistor using pore silicon according to the present invention includes a substrate; A pore silicon layer in which pores having a diameter of 5 nm or less are formed as a channel on the substrate; A source and a drain formed of metal on both sides of the pore silicon layer; An insulating layer made of an oxide on top of the pore silicon layer; And a gate formed on the insulating layer.

In the present invention, the thickness of the pore silicon layer is preferably 10 nm or less.

In addition, in order to achieve the above object, the method of manufacturing a single-electron transistor using the porous silicon according to the present invention, (A) the silicon layer by immersing the SOI substrate having a thickness of 10 nm or less in HF-based solution Electrochemically corroding to form a porous silicon layer having pores having a diameter of 5 nm or less; (B) etching portions of the pore silicon layer at regular intervals to secure source and drain regions, and then depositing metal in place to form sources and drains having a thickness of 100 nm or less; And (c) depositing silicon dioxide having a thickness of 10 nm or less by chemical vapor deposition on the pore silicon layer between the source and the drain, and forming a gate having a thickness of 100 nm or less thereon. do.

In the present invention, in the step (b), the metal is preferably deposited using physical or chemical vapor deposition. In the step (b) and (c), the source, drain, and gate may be selectively etched or lifted. It is preferable to form using an off process.

In addition, another method of manufacturing a single-electron transistor using pore silicon according to the present invention to achieve the above object, (A) by selectively etching the silicon layer on an SOI substrate having a thickness of 10 nm silicon layer Exposing portions to be formed with sources and drains, and depositing a metal having a thickness of 100 nm or less on the exposed regions to form sources and drains; (B) forming a resist on the source and drain to expose only the silicon layer, and then immersing the SOI substrate in an HF-based solution to electrochemically corrode the exposed silicon layer to form pores of less than 5 nm in diameter. Forming a; And (c) depositing silicon dioxide having a thickness of 10 nm or less on the pore silicon layer by chemical vapor deposition, and forming a gate having a thickness of 100 nm or less thereon.

In the present invention, in the step (a), the metal is preferably deposited using physical or chemical vapor deposition. In the steps (a) and (c), the source, drain, and gate may be selectively etched or lifted. It is preferable to form using an off process.

In order to achieve the above object, a single electron transistor using another pore silicon according to the present invention includes a substrate; A pore silicon layer in which pores having a diameter of 5 nm or less are formed as a channel on the substrate; A source and a drain formed of silicon containing impurities having a predetermined concentration or higher on both sides of the pore silicon layer; An insulating layer made of an oxide on top of the pore silicon layer; And a gate formed on the insulating layer.

In the present invention, the pore silicon layer has a thickness of 10 nm or less, and the source and drain preferably contain impurities having a concentration of 10 ²⁰ / cm ³ or less, and the source and drain are preferably formed in n ⁺ or p ⁺ type.

In addition, in order to achieve the above object, a method of manufacturing a single-electron transistor using another porous silicon according to the present invention, (A) forming a resist pattern at regular intervals on an SOI substrate having a thickness of 10 nm or less of the silicon layer. Then immersing the SOI substrate in an HF-based solution to electrochemically corrode the exposed portion of the silicon layer to form a pore silicon layer having pores less than or equal to 5 nm in diameter; (B) removing the resist pattern and forming a resist pattern only on the top surface of the porous silicon layer to expose the remaining portions of the silicon layer, and to include a source or a drain by including impurities at a predetermined concentration on the exposed silicon layer; step; And (c) depositing an insulating layer having a thickness of 10 nm or less on the pore silicon layer by chemical vapor deposition, and forming a gate having a thickness of 100 nm or less thereon.

In the present invention, in the step (b), the impurity is included in the silicon layer at a concentration of 10 ²⁰ / cm ³ or less through an ion implantation method or a doping process, and in the step ( ^c ), the size of the pore silicon layer is The SiO _{2 is} controlled through a forming process, and the insulating layer is preferably formed by depositing silicon dioxide with a thickness of 10 nm or less.

In addition, another method of manufacturing a single-electron transistor using another porous silicon according to the present invention in order to achieve the above object, (A) selectively to the silicon layer in the SOI substrate having a thickness of 10 nm silicon layer; Including impurities to form a source and a drain; (B) selectively forming a resist on the source and drain to expose only the silicon layer between the source and drain, and then immersing the SOI substrate in an HF-based solution to electrochemically corrode the exposed silicon layer to a diameter of 5 nm. Forming a porous silicon layer having the following pores; And (c) depositing an insulating layer having a thickness of 100 nm or less on the pore silicon layer by chemical vapor deposition, and forming a gate having a thickness of 100 nm or less thereon.

In the present invention, in the step (a), the impurity is included in the silicon layer at a concentration of 10 ²⁰ / cm ³ or less through an ion implantation method or a doping process, and in the step ( ^c ) the size of the pore silicon layer is The SiO _{2 is} controlled through a forming process, and the insulating layer is preferably formed by depositing silicon dioxide with a thickness of 10 nm or less.

Hereinafter, a single electron transistor and a method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a vertical cross-sectional view of a single electron transistor using pore silicon according to the present invention. As shown, the single-electron transistor using pore silicon according to the present invention is provided with a pore silicon 40 layer having pores 41 having a diameter of 5 nm or less as a channel on the SOI substrate 10, and these pores. A source 20 and a drain 30 formed by depositing metal on both sides of the silicon layer 40 are provided, and the insulating layer 50 and the gate 60 made of oxide are sequentially formed on the pore silicon layer 40. It has a laminated structure. Here, the silicon 42 between the pores 41 of the pore silicon layer 40 as a channel acts as an island, and the thickness of the pore silicon layer 40 is 10 nm or less.

There are two methods for manufacturing a single electron transistor having such a structure.

The first method is to first form a pore silicon layer for a channel, and then to form a source and a drain with a metal.

First, as shown in FIG. 3A, the SOI substrate 10 having a thickness of 10 nm or less is electrochemically corroded in an HF-based solution to form a porous silicon layer 40 ′. At this time, the pore diameter of the pore silicon layer 40 'is formed to 5 nm or less. Here, the electrochemical corrosion simply includes a method of quenching by quenching without applying a voltage in the HF-based solution.

Next, as shown in FIG. 3B, the source and drain regions are secured through an etching process, and metal is deposited therein to form a source 20 and a drain 30 having a thickness of 100 nm or less. In this case, metal deposition uses physical or chemical vapor deposition (PVD or CVD). Of course, a metal layer may be formed by a plating method to form a source and a drain. In this case, there is a constriction between the island and the island. This constriction acts as a tunnel barrier due to quantum mechanical size effects and the size (thickness and diameter) of the pore silicon layer 40 is freely controlled through the formation of silicon dioxide (SiO ₂ ) in the furnace. Adjustable with

Next, silicon dioxide 50 having a thickness of 10 nm or less is deposited on the pore silicon layer 40 by physical or chemical vapor deposition, and a gate having a thickness of 100 nm or less is formed thereon through an etching or lift-off process. 60 is formed to complete an element. In this case, the metal deposition method is the same as the deposition method for forming the source and the drain.

The second method is to first form a source and a drain from a metal, and then form a pore silicon layer for the channel.

First, the SOI substrate 10 'having a thickness of 10 nm of the silicon layer 40' as shown in FIG. 4A is selectively etched to expose the portion where the source and drain will be formed, as shown in FIG. 4B. .

Next, as illustrated in FIG. 4C, a source 20 and a drain 30 having a thickness of 100 nm or less are formed through metal deposition. Of course, the metal layer is deposited by physical or chemical vapor deposition (PVD or CVD) method, it is also formed by the plating method.

Next, the silicon layer 40 ′ left for the channel is electrochemically corroded in an HF-based solution to form the porous silicon layer 40. Electrochemical corrosion here simply involves quenching in HF-based solutions without quenching.

Next, as described above, the silicon dioxide layer 50 having a thickness of 10 nm or less is formed through physical or chemical vapor deposition, and then the gate 60 having a thickness of 100 nm or less is formed thereon through an etching or liftoff process. Complete In this case, the metal deposition method uses the same method as the deposition method for forming the source and the drain.

On the other hand, Figure 5 is a vertical cross-sectional view of a single electron transistor using another pore silicon in accordance with the present invention. As shown, this embodiment is provided with a layer of pore silicon 400 having pores 410 with a diameter of 5 nm or less as a channel on the SOI substrate 100, on both sides of these pore silicon layers 400. A source 200 and a drain 300 doped with n ⁺ or p ⁺ type impurities are provided, and the insulating layer 500 and the gate 600 made of oxide are sequentially stacked on the pore silicon layer 40. Has a structure. Here, the silicon 420 between the pores 410 of the pore silicon layer 400 as a channel acts as an island, and the thickness of the pore silicon layer 400 is 10 nm or less.

There are two methods for manufacturing a single electron transistor having such a structure.

The first method is to form a source and a drain by first implanting or doping impurities into silicon, and then forming a porous silicon layer.

First, as shown in FIG. 6A, a resist pattern is formed by a lithography process on a silicon layer 400 ′ of an SOI substrate 100 ′ having a thickness of 10 nm of the silicon layer 400 ′. As shown in FIG. 6B, the source 200 and the drain 300 may be doped by ion implantation or doping n ⁺ (or p ⁺ type) impurities to a concentration of 10 ²⁰ / cm ³ or less. Form.

Next, the resist PR is removed to expose a portion to be formed by the pore silicon layer, and as shown in FIG. 6C, a portion where the source and drain are formed is formed with a resist pattern so as not to be exposed to the HF-based corrosion solution. The exposed silicon layer is then electrochemically corroded to form the pore silicon layer 400. At this time, the pore diameter is adjusted to 5 nm or less. In this case, the electrochemical corrosion simply includes a method of quenching through quenching without applying voltage to the HF-based solution.

Next, as shown in FIG. 5, silicon dioxide 500 having a thickness of 100 nm or less is formed on the pore silicon layer 400 by physical or chemical vapor deposition, and thereafter, selective etching or a lift-off process is used thereon. To form a gate 600 with a thickness of 100 nm or less to complete the device. The gate 600 deposits a metal by physical or chemical vapor deposition (PVD or CVD), and may be used by plating.

There are two methods for manufacturing a single electron transistor having such a structure.

The second method is to form a pore silicon layer for a channel first, and then form a source and a drain by implanting or doping impurities.

First, as shown in FIG. 7A, a resist pattern PR is formed by a lithography process on a silicon layer 400 ′ of an SOI substrate 100 ′ having a thickness of 10 nm of the silicon layer 400 ′. Next, the exposed silicon layer is electrochemically corroded to form the pore silicon layer 400. At this time, the pore diameter is adjusted to 5 nm or less. In this case, the electrochemical corrosion simply includes a method of quenching through quenching without applying voltage to the HF-based solution.

Next, the resist PR is removed to expose the portion where the source and drain are to be formed, and as shown in FIG. 7C, the porous silicon layer 400 is not exposed to the HF-based corrosion solution. And then implanting n ⁺ or p ⁺ impurities into the exposed source and drain regions using ion implantation or diffusion to ensure a doping concentration of 10 ²⁰ / cm ³ or less. Doped to form source and drain. Next, as shown in FIG. 5, the resist is removed, and silicon dioxide 500 having a thickness of 10 nm or less is formed on the pore silicon layer 400 by physical or chemical vapor deposition, and then selective etching is performed thereon. The gate 600 having a thickness of 100 nm or less is formed by using a lift-off process to complete the device. Of course, the gate 600 deposits a metal by physical or chemical vapor deposition (PVD or CVD), and may be a plating method.

The operating principle of the single electron transistor using the pore silicon according to the present invention produced by the above method is as follows.

When a voltage is applied between the source and the drain, the current flows only when it reaches a certain voltage. The random voltage at this time is called the Coulomb blockade gap and no current flows, as the electrons are tunneled from the source to the island, causing charge to occur in the island so that no more electrons can be accepted. Because. If more energy than this charging energy is supplied through the gate, the coulomb blockade does not occur and a random current flows. Therefore, if the voltage between the source and drain is fixed below the coulomb blockade gap and the gate voltage is adjusted, switching occurs similarly to the conventional three-terminal transistor.

As described above, the single electron transistor using pore silicon according to the present invention is electrochemically corroded in HF-based solution with pore silicon having a diameter of 5 nm or less on a silicon substrate (SOI) composed of silicon dioxide (SiO ₂ ) underneath. Is used as an island of single-electron transistors, and forms a source, a drain, and a gate from silicon implanted or doped with metal or impurities, thereby generating island and tunnel barriers. It is easier to form, allows for mass production, and the size of the island can be adjusted in the oxidation furnace, making it easy to manufacture single-electron transistors that can operate at room temperature. In particular, the constricted portions of the pore silicon act as tunnel barriers by quantum mechanical size effects, thereby ensuring the reproducibility and homogeneity of the island size. That is, in the conventional single-electron transistor manufacturing, it is required to go through a lot of efforts, complex and precise manufacturing process to form the oxide as a tunnel barrier, and even through such a process, island size reproducibility and homogeneity cannot be guaranteed. Accordingly, the present invention can greatly improve the above two problems by using pore silicon as an island of a single electron transistor. Moreover, the size of the island can be easily controlled to nm size, the manufacturing process is easy, and the mass production is easy, so the production is easy. Therefore, the single electron transistor manufactured by the present invention may be applied to a 1 Tb class memory and a logic device.

Claims (27)

Board; A pore silicon layer in which pores having a diameter of 5 nm or less are formed as a channel on the substrate; A source and a drain formed of metal on both sides of the pore silicon layer; An insulating layer made of an oxide on top of the pore silicon layer; And A gate formed on the insulating layer; Single electron transistor using pore silicon, characterized in that provided. The method of claim 1, The substrate is a single-electron transistor using a porous silicon, characterized in that the SOI substrate. The method of claim 1, The thickness of the pore silicon layer is a single electron transistor using pore silicon, characterized in that less than 10nm. (A) dipping an SOI substrate having a thickness of 10 nm or less in an HF-based solution to electrochemically corrode the silicon layer to form a porous silicon layer having pores having a diameter of 5 nm or less; (B) etching portions of the pore silicon layer at regular intervals to secure source and drain regions, and then depositing metal in place to form sources and drains having a thickness of 100 nm or less; And (C) depositing silicon dioxide having a thickness of 10 nm or less by chemical vapor deposition on the pore silicon layer between the source and the drain, and forming a gate having a thickness of 100 nm or less thereon; A method of manufacturing a single electron transistor using pore silicon, characterized in that it comprises a. The method of claim 4, wherein In the step (b), the metal is deposited using a physical or chemical vapor deposition method. The method of claim 4, wherein In the step (b), the metal is deposited using a plating method. The method of claim 4, wherein The silicon size of the pore silicon layer in the step (c) is controlled by the SiO ₂ forming process, characterized in that the manufacturing method of a single electron transistor using a pore silicon. The method of claim 4, wherein In the step ( ^c ), the gate is a metal and n ⁺ or p ⁺ doped semiconductor to form less than 10 ²⁰ / cm ³ using a lift-off process method of manufacturing a single electron transistor using a pore silicon. (A) Selectively etch the silicon layer on an SOI substrate having a thickness of 10 nm to expose a portion where a source and a drain are to be formed, and deposit a metal having a thickness of 100 nm or less on the exposed region to form a source and a drain. Forming; (B) forming a resist on the source and drain to expose only the silicon layer, and then immersing the SOI substrate in an HF-based solution to electrochemically corrode the exposed silicon layer to form pores of less than 5 nm in diameter. Forming a; And (C) depositing silicon dioxide having a thickness of 10 nm or less on the pore silicon layer by chemical vapor deposition, and forming a gate having a thickness of 100 nm or less thereon; A method of manufacturing a single electron transistor using pore silicon, characterized in that it comprises a. The method of claim 9, The method of claim 1, wherein the metal is deposited using physical or chemical vapor deposition. The method of claim 9, In the step (a), the metal is deposited using a plating method. The method of claim 9, The method of manufacturing a single electron transistor using pore silicon, characterized in that in the step (c) the size of the pore silicon layer is controlled through a SiO ₂ formation process. The method of claim 9, In the step ( ^c ), the gate is a metal and n ⁺ or p ⁺ doped semiconductor to form less than 10 ²⁰ / cm ³ using a lift-off process method of manufacturing a single electron transistor using a pore silicon. Board; A pore silicon layer in which pores having a diameter of 5 nm or less are formed as a channel on the substrate; A source and a drain formed of silicon containing impurities having a predetermined concentration or higher on both sides of the pore silicon layer; An insulating layer made of an oxide on top of the pore silicon layer; And A gate formed on the insulating layer; Single electron transistor using pore silicon, characterized in that provided. The method of claim 14, The substrate is a single-electron transistor using a porous silicon, characterized in that the SOI substrate. The method of claim 14, The thickness of the pore silicon layer is a single electron transistor using pore silicon, characterized in that less than 10nm. The method of claim 14, The source and drain contain impurities having a concentration of 10 ²⁰ / cm ³ or less, so that the source and drain are formed in n ⁺ or p ⁺ type single electron transistor using a silicon. (A) Form a resist pattern at regular intervals on an SOI substrate having a thickness of 10 nm or less, and then immerse the SOI substrate in an HF-based solution to electrochemically corrode the exposed portion of the silicon layer to 5 nm or less in diameter. Forming a porous silicon layer having pores of; (B) removing the resist pattern and forming a resist pattern only on the top surface of the pore silicon layer to expose the remaining portions of the silicon layer, and to form a source and a drain by including impurities above a predetermined concentration on the acid-exposed silicon layer. step; And (C) depositing an insulating layer having a thickness of 10 nm or less on the pore silicon layer by chemical vapor deposition, and forming a gate having a thickness of 100 nm or less thereon; A method of manufacturing a single electron transistor using pore silicon, characterized in that it comprises a. The method of claim 18, In the step (b), the impurity is a method of manufacturing a single-electron transistor using pore silicon, characterized in that to include in the silicon layer at a concentration of 10 ²⁰ / cm ³ or less. The method of claim 18, In the step (b), the impurity is included in the silicon layer through an ion implantation method or a doping process, characterized in that the manufacturing method of a single electron transistor using a pore silicon. The method of claim 18, The method of manufacturing a single electron transistor using pore silicon, characterized in that in the step (c) the size of the silicon of the pore silicon layer is controlled through a SiO ₂ forming process. The method of claim 18, The method of claim 1, wherein the insulating layer is formed by depositing silicon dioxide to a thickness of 10 nm or less. (A) forming a source and a drain by selectively including impurities in the silicon layer in an SOI substrate having a thickness of 10 nm; (B) selectively forming a resist on the source and drain to expose only the silicon layer between the source and drain, and then immersing the SOI substrate in an HF-based solution to electrochemically corrode the exposed silicon layer to a diameter of 5 nm. Forming a porous silicon layer having the following pores; And (C) depositing an insulating layer having a thickness of 10 nm or less on the pore silicon layer by chemical vapor deposition, and forming a gate having a thickness of 100 nm or less thereon; A method of manufacturing a single electron transistor using pore silicon, characterized in that it comprises a. The method of claim 23, wherein In the step (a), the impurity is a method of manufacturing a single-electron transistor using a pore silicon, characterized in that to include a concentration of 10 ²⁰ / cm ³ or less in the silicon layer. The method of claim 23, wherein In the step (a), the impurity is a method of manufacturing a single-electron transistor using a porous silicon, characterized in that included in the silicon layer through the ion implantation method or doping process. The method of claim 23, wherein The method of manufacturing a single electron transistor using pore silicon, characterized in that in the step (c) the size of the silicon of the pore silicon layer is controlled through a SiO ₂ forming process. The method of claim 23, wherein The method of claim 1, wherein the insulating layer is formed by depositing silicon dioxide to a thickness of 10 nm or less.