KR100441871B1 - Column repair device, especially related to increasing a repair efficiency by enabling a repair without a spare cell - Google Patents

Abstract

PURPOSE: A column repair device is provided to continuously use a bit line having data in a bit line sense amplifier, and to replace a bit line for supplying a reference voltage value with a bit line of other cell array block, thereby enabling a column repair operation without a spare cell. CONSTITUTION: Plural cell array blocks(100,120) consist of plural word lines, bit lines, and cells. A bit line sense amplifier senses and amplifies cell data transmitted to the bit lines. N-MOS type transistors are connected to bit line pairs between the cell array blocks(100,120) and the bit line sense amplifier, respectively, and separate the bit lines. Switching controllers(L1-L4) continuously use bit lines having data during a column repair while replacing bit lines having reference voltages with bit lines of other cell array block to cause a sensing process.

Description

Column repair device

The present invention relates to a column repair apparatus for replacing a defective memory cell, and more particularly, to a column repair apparatus implemented to enable repair without a spare cell.

In general, when a defect occurs in any cell in the cell array, the column repair apparatus replaces a bit line to which a defective cell is connected with an extra spare bit line to compensate for the defect. When an address for selecting a defective cell is applied to the inside of the device, the normal path for selecting a defective cell is broken, and instead, the repair apparatus operates to enable the bit line to which the repaired cell is connected, thereby performing the column repair operation. You lose.

1 is a block diagram of a semiconductor memory device for explaining a conventional column repair method.

In the conventional column repair method of the above structure, a repair operation is performed by arranging an extra cell in a specific portion of a cell array block, and then replacing the extra cell with a defective cell when a repair is required. As described above, the memory device needs an additional cell necessary for the repair in addition to the cell capacity of the memory in order to perform the repair operation. As a result, since an extra cell to be used for the repair is additionally configured in addition to the cell as much as the memory capacity, an additional area is required, and circuits necessary for controlling the repair cell must be additionally added during the repair operation. there was.

Accordingly, an object of the present invention is to provide a column repair apparatus implemented to repair without an extra cell.

In order to achieve the above object, the column repair apparatus according to the present invention is a semiconductor memory device of a cell array block structure in which one sense amplifier is shared with each other,

A plurality of cell array blocks comprising a plurality of word lines, bit lines, and cells;

A bit line sense amplifier for sensing and amplifying cell data transmitted to the bit line;

Bit line separating means connected to the bit line pairs between the cell array block and the bit line sense amplifier, for separating the bit lines; and

When the column is repaired, the bit line having the data is used as it is, and the other bit line having the reference voltage is replaced with the bit line of the other cell array block in which the word line is not selected to control the operation of the bit line separating means so that sensing occurs. And switching control means.

1 is a configuration diagram of a semiconductor memory for explaining a conventional column repair method.

2 is a block diagram of a semiconductor memory including a column repair apparatus according to an embodiment of the present invention.

3A and 3B are state diagrams of input signals used in the present invention.

<Description of the code | symbol about the principal part of drawing>

10, 100: cell array block controlled by AX89 address

20, 120: Cell array block controlled by AX / 89 address

30, 130: Cell array block controlled by AX8 / 9 address

40, 140: Cell array block controlled by AX / 8/9 address

11: bitline sense amplifier

50: bit line sense amplifier array block

A: Block in which a defective cell is generated

B: Spare block to be used for repair

The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a semiconductor memory including a column repair apparatus according to an embodiment of the present invention.

In the semiconductor memory device having a cell array block structure in which one sense amplifier is shared with each other, a plurality of cell array blocks including a plurality of word lines, bit lines, and cells, and cell data transmitted through the bit lines are sensed. Bit line sense amplifiers for amplifying, bit line pairs connected between the cell array block and the bit line sense amplifiers, respectively, and N-MOS transistors for separating the bit lines, and bit lines having column repair data. Switching control means (L1 to L4) for controlling the operation of the bit line separating means so that the other bit line having the reference voltage and having the reference voltage is replaced with the bit line toward the other cell array block in which the word line is not selected. It was provided.

First, when no repair is performed, a signal as shown in the truth table of FIG. 3A is input to the first to fourth lines L1 to L4 connected to the gates of the N-MOS transistors, respectively, so that normal operation is performed. do. In the case of FIG. 3A, cells of the upper and lower cell array blocks 100 and 120 sharing one sense amplifier array block 150 are not selected. At this time, the first to fourth lines L1 to L4 are all in a low state, and the bit lines are separated by turning off all of the N-MOS transistors connected to the bit lines. In the case of B or C of FIG. 3A, when any one cell of two cell array blocks 100 and 120 sharing one sense amplifier array block 150 is selected, the selected cell belongs to a block side. The N-MOS transistor is turned on to allow normal operation.

On the other hand, in the case of repairing, a defective column can be repaired without an extra column by inputting a signal such as that shown in the truth table of FIG. 3B to the first to fourth lines L1 to L4.

For example, if the sense amplifier array block 150 needs to be repaired when the first word line WL1 of the block 100 controlled by the AX89 address is turned on, the signal of case C shown in the truth table of FIG. Enter it. Then, only the N-MOS transistors connected to the second line L2 and the fourth line L4 are turned on so that the sense amplifier sensed by the bit line eye BLi and the bit line eye bar / BLi is a bit line eye bar. (/ BLi) and bit line BLj.

When the repair is performed when the second word line WL2 is turned on instead of the first word line WL1, the sense amplifier senses the data by the bit line eye BLi and the bit line J bar / BLj. do. Therefore, the signal in case B of FIG. 3B is inputted.

In addition, when the first word line WL1 of the block 120 controlled by the AX / 89 address is turned on and needs to be repaired in the sense amplifier array block 150, the bit line J bar (/ BLj) and the bit line are required. Since the sense amplifier is sensed by the eye BLi, a signal similar to the case of B of FIG. 3B is input to the first to fourth lines L1 to L4. Also, when the second word line WL2 of the block 130 controlled by the AX / 89 address is turned on, the sense amplifier in the sense amplifier array block is turned on by the bit line Jay BLj and the bit line IVA / BLi. Will be sensed. Therefore, repair is performed by inputting the signal in case C of FIG. 3B.

As described above, the column repair apparatus according to the present invention uses a bit line having data in a bit line sense amplifier and a bit line toward another cell array block in which a bit line providing a reference voltage value is not operated. In this sense, the column repair operation can be performed without the extra cells required for the repair. In addition, since it can be used simultaneously with the prior art without the addition of a circuit for the operation of the present invention has the effect of improving the repair efficiency.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (3)

A plurality of cell array blocks comprising a plurality of word lines, bit lines and cells, A plurality of bit lines shared by a predetermined one of the plurality of cell array blocks and connected to a pair of bit lines and bit line bars of each of the shared cell array blocks or for sensing and amplifying cell data transmitted to the bit lines A plurality of bitline sense amplifier arrays including sense amplifiers, Bit line separation means for separating the bit line and the bit line bar pair between the cell array block and the bit line sense amplifier; Switching control means for controlling the selective separation operation of the bit line separation means, During the column repair, the bit line separating means may be configured to: bit the bit line having the reference voltage of the bit line of the shared cell array block in which the word line is selected and the other unique cell array block in which the word line is not selected. A column repair device, which is connected to a line sense amplifier. The method of claim 1, And said bit line separating means is a MOS transistor. The method of claim 2, And said MOS transistor is N-MOS.