KR100440468B1 - Formation method of semiconductor device - Google Patents
Formation method of semiconductor device Download PDFInfo
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- KR100440468B1 KR100440468B1 KR10-2001-0082637A KR20010082637A KR100440468B1 KR 100440468 B1 KR100440468 B1 KR 100440468B1 KR 20010082637 A KR20010082637 A KR 20010082637A KR 100440468 B1 KR100440468 B1 KR 100440468B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
반도체 소자의 제조 방법에 관한 것으로, 그 목적은 콘택홀 또는 비아홀의 구석 위치에도 베리어 메탈이 잘 형성되도록 하는 데 있다. 이를 위해 본 발명에서는 반도체 기판 상부의 콘택홀 또는 비아홀의 내벽에 베리어 메탈, 또는 베리어 메탈의 증착성 향상을 위한 글루층을 형성할 때, 웨이퍼에 전기장 및 자기장을 서로 수직한 방향으로 가한 상태에서 콘택홀 또는 비아홀의 내벽에 베리어 메탈 또는 글루층을 형성함으로써, 증착되는 금속입자가 나선운동을 하여 홀의 내벽 전면에 잘 증착되도록 한다.The present invention relates to a method of manufacturing a semiconductor device, and an object thereof is to allow barrier metals to be formed well in corners of contact holes or via holes. To this end, in the present invention, when forming a glue layer for depositing barrier metal or barrier metal on the inner wall of a contact hole or via hole on the upper surface of the semiconductor substrate, the contact is applied while the electric and magnetic fields are applied to the wafer in a direction perpendicular to each other. By forming the barrier metal or the glue layer on the inner wall of the hole or via hole, the deposited metal particles are spirally moved to be well deposited on the entire inner wall of the hole.
상기 요약은 구리 메탈 다마신 공정에서 홀 또는 금속배선을 포함한 홀이 형성된 절연막 상에 베리어 메탈이나 시드층을 형성할 때 적용할 수도 있다.The above summary may be applied when forming a barrier metal or seed layer on an insulating film on which a hole or a hole including a metal wiring is formed in a copper metal damascene process.
Description
본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 컨택홀 또는 비아홀의 내벽에 베리어 메탈을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for forming a barrier metal on the inner wall of a contact hole or via hole.
반도체 소자가 점차 고집적화, 다층화됨에 따라 중요한 기술의 하나로 다층 배선 기술이 등장하게 되었는데, 이와 같은 다층 배선 기술은 금속 배선층과 절연막층을 회로 소자가 형성된 반도체 기판 상부에 교대로 형성하며, 절연막에 의해 분리된 금속 배선층 사이를 컨택홀(contact hole) 또는 비아홀(via hole)을 통해 전기적으로 접속함으로써 회로 동작이 이루어지도록 하는 것이다.As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring has emerged as one of the important technologies. The multilayer wiring technology alternately forms a metal wiring layer and an insulating film layer on the semiconductor substrate on which the circuit elements are formed, and is separated by an insulating film. The circuit operation is performed by electrically connecting the metal wiring layers through contact holes or via holes.
도전성 물질로 충진된 컨택홀 또는 비아홀을 형성하기 위해서는, 먼저 홀의 내벽에 베리어 메탈을 먼저 형성한 후, 베리어 메탈 상에 도전성 물질을 형성하여홀의 내부를 충진시키며, 경우에 따라서는 베리어 메탈의 증착성을 향상시키기 위해 홀의 내벽에 글루층을 먼저 형성한 후, 글루층 상에 베리어 메탈을 형성하고 이어서 홀의 내부를 도전성 물질로 충진시킨다.In order to form a contact hole or via hole filled with a conductive material, a barrier metal is first formed on the inner wall of the hole, and then a conductive material is formed on the barrier metal to fill the inside of the hole. A glue layer is first formed on the inner wall of the hole in order to improve the efficiency, and then a barrier metal is formed on the glue layer, and then the inside of the hole is filled with a conductive material.
최근 반도체 소자가 고집적화되어 갈수록 홀의 형상이 보다 더 좁고 깊어지므로, 이와 같이 좁고 깊은 형상의 홀 내벽 전체면에 장벽 금속막을 빠짐없이 잘 증착시키는 것이 관건이 되고 있다.In recent years, as semiconductor devices become more highly integrated, the shape of holes becomes narrower and deeper. Therefore, it is important to deposit a barrier metal film on the entire inner surface of the narrow and deep hole.
도 1은 종래 방법에 의해 반도체 소자의 비아홀 내벽에 화학기상증착법으로 베리어 메탈을 형성하는 것을 도시한 단면도이다.1 is a cross-sectional view illustrating the formation of a barrier metal on the inner wall of a via hole of a semiconductor device by a chemical vapor deposition method by a conventional method.
도 1에 도시된 바와 같이, 비아홀(1)의 내벽에 베리어 메탈(2)을 증착하면, 홀(1)의 입구 부분에 우선적으로 증착되어 오버행(overhang, 도 1에서 H로 표시)이 형성된다. 이러한 오버행(H)에 의해 가려지는, 이른바 그림자 효과(shadow effect)에 의해 하부의 홀 구석부분(도 1에서 G로 표시)에는 베리어 메탈(2)이 증착되지 못하는 문제점이 발생하였다.As shown in FIG. 1, when the barrier metal 2 is deposited on the inner wall of the via hole 1, the barrier metal 2 is preferentially deposited at the inlet of the hole 1 to form an overhang (indicated by H in FIG. 1). . The barrier metal 2 could not be deposited in the lower hole corner (marked with G in FIG. 1) due to the so-called shadow effect, which is covered by the overhang H.
이를 극복하는 방법으로서, 증착되는 금속입자에 직진성을 부여하기 위해, 증착되는 금속입자를 이온화하고 웨이퍼에 전기장을 걸어주는 방법, 또는 물리기상증착 방법을 이용할 때 컵 형태의 타겟(target)을 사용하는 방법 등을 시도하였으나, 이러한 방법들은 홀 바닥의 스텝 커버리지만을 향상시킬 뿐으로, 홀 구석 위치에서의 베리어 메탈 증착을 향상시키지는 못하는 문제점이 있었다.As a method of overcoming this, in order to impart linearity to the deposited metal particles, a cup-shaped target is used when ionizing the deposited metal particles and applying an electric field to the wafer, or when using physical vapor deposition. Although attempts have been made to the method, these methods only improve the step coverage of the hole bottom, and there is a problem that does not improve the barrier metal deposition at the hole corner position.
이와 같이, 홀 구석 위치에서 베리어 메탈 특성이 취약하게 되면 홀 저항이 증가하고, 홀 내부에 도전성 물질이 완전히 충진되지 못하는 등, 반도체 소자를 동작불능 상태에 이르게 하는 문제점이 있었다.As described above, when the barrier metal property becomes weak at the hole corner, there is a problem in that the semiconductor device is in an inoperable state, such as an increase in the hole resistance and incomplete filling of the conductive material in the hole.
또한 구리 메탈 다마신 공정에서 홀 또는 금속배선을 포함한 홀이 형성된 절연막 상에 베리어 메탈, 또는 구리 메탈 박막의 전기도금법(Electro Plating) 증착을 가능하게 하기 위한 시드(Seed)층을 형성할 때도 하부의 홀 구석부분에 베리어 메탈과 시드층이 증착되지 못하는 문제점이 발생하였다.In addition, when forming a seed layer for enabling electroplating deposition of a barrier metal or a copper metal thin film on an insulating film including a hole or a metal wiring including a hole in a copper metal damascene process, Barrier metal and seed layer could not be deposited in the hole corner problem occurred.
이와 같이, 홀 구석에서 베리어 메탈과 시드층이 취약하게 되면 구리 메탈 다마신 공정에 의한 구리 증착이 일어나지 않아 구리선의 단락이 발생해 반도체 소자를 동작불능 상태에 이르게하는 문제점이 있다.As described above, when the barrier metal and the seed layer become weak in the hole corners, copper deposition by the copper metal damascene process does not occur, resulting in a short circuit of the copper wire, thereby causing the semiconductor device to become inoperable.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 콘택홀 또는 비아홀 또는 금속배선용을 포함한 듀얼 다마신 홀의 구석 위치에도 베리어 메탈과 글루층 또는 베리어 메탈과 시드층이 잘 형성되도록 하는 데 있다.The present invention is to solve the problems as described above, the object is to ensure that the barrier metal and glue layer or barrier metal and seed layer well formed even in the corner position of the dual damascene hole including the contact hole or via hole or metal wiring. have.
도 1은 종래 방법에 의해 반도체 소자의 비아홀 내벽에 베리어 메탈을 형성하는 것을 도시한 단면도이다.1 is a cross-sectional view illustrating the formation of a barrier metal on an inner wall of a via hole of a semiconductor device by a conventional method.
도 2는 본 발명에 따라 반도체 소자의 비아홀 내벽에 베리어 메탈을 형성하는 것을 도시한 단면도이다.2 is a cross-sectional view illustrating the formation of a barrier metal on an inner wall of a via hole of a semiconductor device according to the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 반도체 기판 상부의 콘택홀 또는 비아홀의 내벽에 베리어 메탈, 또는 베리어 메탈의 증착성 향상을 위한 글루층을 형성할 때, 웨이퍼에 전기장 및 자기장을 서로 수직한 방향으로 가한 상태에서 콘택홀 또는 비아홀의 내벽에 베리어 메탈 또는 글루층을 형성한다.In order to achieve the above object, in the present invention, when forming a glue layer for improving the deposition property of the barrier metal, or barrier metal on the inner wall of the contact hole or via hole on the semiconductor substrate, the electric and magnetic fields on the wafer The barrier metal or the glue layer is formed on the inner wall of the contact hole or the via hole while being applied in the vertical direction.
이 때, 베리어 메탈은, TiN, Ti, 및 TiW 중의 어느 한 금속을 화학기상증착(CVD :chemical vapor depositon) 또는 물리기상증착(PVD : physical vapor deposition) 중의 어느 한 방법으로 형성하는 것이 바람직하며, 글루층은 Ti로 형성하는 것이 바람직하다.In this case, the barrier metal is preferably formed of any one of TiN, Ti, and TiW by chemical vapor deposition (CVD) or physical vapor deposition (PVD). It is preferable to form a glue layer with Ti.
또한, 자기장을 가할 때에는, 웨이퍼의 하부에 상자성체 또는 전자석을 접촉 또는 비접촉시키는 것이 바람직하다.In addition, when applying a magnetic field, it is preferable to make a paramagnetic body or an electromagnet contact or non-contact below the wafer.
이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다. 도 2는 본 발명에 따라 비아홀 내벽에 베리어 메탈을 형성하는 것을 도시한 단면도이다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail. 2 is a cross-sectional view illustrating the formation of a barrier metal on an inner wall of a via hole according to the present invention.
도 2에 도시된 바와 같이, 반도체 기판의 상부에서 절연막을 관통하여 금속배선층과 연결되도록 형성된 컨택홀 또는 비아홀(10)의 내벽에 TiN, Ti, 또는 TiW와 같은 베리어 메탈(20)을 증착할 때, 웨이퍼에 전기장(E)을 가하고 이와 수직방향으로는 자기장(B)을 인가한다.As illustrated in FIG. 2, when the barrier metal 20 such as TiN, Ti, or TiW is deposited on the inner wall of the contact hole or via hole 10 formed to penetrate the insulating layer and connect to the metal wiring layer on the semiconductor substrate. The electric field E is applied to the wafer and the magnetic field B is applied in the vertical direction.
도 2에는, 전기장을 웨이퍼 면에 수직한 방향으로 인가하고 자기장을 웨이퍼 면에 평행한 방향으로 인가한 경우가 도시되어 있다.2 shows a case where an electric field is applied in a direction perpendicular to the wafer plane and a magnetic field is applied in a direction parallel to the wafer plane.
이 때, 증착되는 베리어 메탈 입자를 이온화하여 화학기상증착 또는 물리기상증착 방법으로 홀 내벽에 증착되도록 한다. 그러면, 베리어 메탈 입자는 전기장 및 자기장이 서로 수직한 방향으로 가해진 장 내에서 나선운동을 하게된다. 즉, 증착되는 베리어 메탈 입자는 홀 내에서 수직방향의 운동성분 뿐만 아니라 수평방향의 운동성분을 가지며, 이로써 홀 구석위치에 증착될 확률이 종래에 비해 대폭 증대되는 것이다.At this time, the deposited barrier metal particles are ionized to be deposited on the inner wall of the hole by chemical vapor deposition or physical vapor deposition. Then, the barrier metal particles are in a spiral motion in the field in which the electric and magnetic fields are applied in a direction perpendicular to each other. That is, the deposited barrier metal particles have not only a vertical motion component but also a horizontal motion component in the hole, thereby greatly increasing the probability of being deposited at the corner of the hole.
또한, 컨택홀 또는 비아홀 내벽에 베리어 메탈을 형성하기 전에 Ti와 같은 글루층을 먼저 형성하고, 글루층 상에 베리어 메탈을 형성할 수도 있으며, 이 경우에는 글루층을 형성할 때 전기장 및 자기장을 가하여 글루층이 홀의 모든 내벽에 잘 증착되도록 하면 된다.In addition, before forming the barrier metal on the inner wall of the contact hole or via hole, a glue layer such as Ti may be formed first, and the barrier metal may be formed on the glue layer. In this case, an electric field and a magnetic field may be applied when the glue layer is formed. The glue layer should be well deposited on all inner walls of the hole.
이와 같이, 홀 내벽에 글루층 또는 베리어 메탈을 형성할 때 자기장을 가하기 위해서는, 웨이퍼의 하부에 상자성체 또는 전자석을 둔다. 상자성체 또는 전자석은 웨이퍼에 접촉시킬 수도 있고 소정 간격을 두고 위치하도록 비접촉시킬 수도 있다.As described above, in order to apply a magnetic field when forming the glue layer or barrier metal on the inner wall of the hole, a paramagnetic material or an electromagnet is placed on the lower part of the wafer. The paramagnetic or electromagnet may be in contact with the wafer or may be in noncontact so as to be positioned at a predetermined interval.
전자석은 웨이퍼 히터로 사용할 수도 있으며 이 경우에는 자기장과 열에너지를 동시에 가하게 되는데, 이로써 베리어 메탈 또는 글루층의 증착성을 향상시킬 수도 있다.The electromagnet can also be used as a wafer heater, in which case the magnetic field and heat energy are applied simultaneously, thereby improving the deposition property of the barrier metal or the glue layer.
상기한 바와 같이, 웨이퍼에 전기장 및 자기장을 가한 상태에서 홀의 내벽에 베리어 메탈 또는 글루층을 형성하는 방법은, 구리 메탈 다마신(damascene) 공정에서 홀, 또는 금속배선을 포함한 홀이 형성된 절연막 상에 베리어 메탈이나 시드층을 형성할 때 적용할 수도 있다.As described above, the method of forming the barrier metal or the glue layer on the inner wall of the hole while applying the electric and magnetic fields to the wafer is performed on the insulating film on which the hole or the hole including the metal wiring is formed in the copper metal damascene process. It can also be applied when forming a barrier metal or seed layer.
상술한 바와 같이, 본 발명에서는 웨이퍼에 전기장 및 자기장을 가한 상태에서 컨택홀 또는 비아홀의 내벽에 베리어 메탈 또는 글루층 또는 시드층을 형성하기 때문에, 증착되는 금속입자가 나선운동을 하여 홀의 구석위치에도 잘 증착되는 효과가 있다.As described above, in the present invention, since the barrier metal or the glue layer or the seed layer is formed on the inner wall of the contact hole or the via hole in the state in which the electric and magnetic fields are applied to the wafer, the deposited metal particles are helically moved to the corner positions of the holes. It has a good deposition effect.
따라서, 홀의 내벽, 특히 홀의 구석위치에도 베리어 메탈이 빠짐없이 잘 증착되므로, 비아홀 보이드 형성을 방지하여 비아홀 저항 증가에 의한 반도체 소자성능 저하 또는 동작 불능 상태를 미연에 방지하는 효과가 있다.Therefore, since the barrier metal is well deposited on the inner wall of the hole, particularly in the corner of the hole, it is possible to prevent the formation of the via hole voids, thereby preventing the degradation of the semiconductor device performance or the inoperable state due to the increase of the via hole resistance.
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| JPS6334923A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Semiconductor manufacturing equipment |
| KR980011896A (en) * | 1996-07-25 | 1998-04-30 | 김광호 | Method of filling a contact hole in a semiconductor device |
| KR19980054455A (en) * | 1996-12-27 | 1998-09-25 | 김영환 | Metal wiring formation method of semiconductor device |
| KR20000003941A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Barrier metal of semiconductor devices |
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| JPS6334923A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Semiconductor manufacturing equipment |
| KR980011896A (en) * | 1996-07-25 | 1998-04-30 | 김광호 | Method of filling a contact hole in a semiconductor device |
| KR19980054455A (en) * | 1996-12-27 | 1998-09-25 | 김영환 | Metal wiring formation method of semiconductor device |
| KR20000003941A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Barrier metal of semiconductor devices |
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