KR100436459B1 - Analog signal amplifying method in analog signal amplifier, semiconductor ic device using the same, several kinds of analog amplifiers, and tooth saw wave oscillator and power amplifier device for being used in the analog amplifier - Google Patents

Abstract

The analog signal amplifying method and amplifying device according to the present invention compares an input signal with a first sawtooth wave which is equal to or greater than the maximum amplitude of the input signal and outputs a high output for a period in which the first sawtooth wave is larger than this input signal. Outputs a first pulse of (), outputs a narrow one-shot second pulse at each start point of the high period of the first pulse, and each high time point of the second sawtooth wave and the second pulse having the same period as the first sawtooth wave. The output voltages are continuously extracted by sampling the second sawtooth wave voltage positions in the corresponding portions, and the extracted voltage is charged to a capacitor by a high-speed switch to maintain the extracted voltage. Eliminate bone pores to facilitate filtering.

According to this configuration, the present invention can generate the linearity of the first sawtooth wave very easily and satisfactorily, and there is no limitation in the input voltage range, and since the negative feedback is not used, the distortion due to time delay can be fundamentally eliminated. Because of the low content of high frequency components, filtering is easy and the waveform itself is transformed without any significant change.

In addition, by omitting the D / A conversion part in the current digital reproducing apparatus (e.g., CDP) and directly connecting the digital signal to the amplifier according to the present invention, a signal without distortion is reproduced and circuits are reduced.

Description

ANALOG SIGNAL AMPLIFYING METHOD IN ANALOG SIGNAL AMPLIFIER, SEMICONDUCTOR IC DEVICE USING THE SAME, SEVERAL KINDS OF ANALOG AMPLIFIERS, AND TOOTH SAW WAVE OSCILLATOR AND POWER AMPLIFIER DEVICE FOR BEING USED IN THE ANALOG AMPLIFIER}

The present invention is a continuation application with priority in Korean Patent Application No. 2001-24301.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for amplifying analog signals in the field of digital amplifiers, and more particularly, to an analog signal amplification method in which an output is remarkably improved in an audio amplifier by suppressing distortion of an output waveform. The present invention also relates to an amplifying device integrated into a circuit using this amplification method. In addition, the present invention relates to an amplifier using various digital information including a PWM signal or a PCM signal as an input signal of the amplifier. The present invention also relates to sawtooth oscillators and power amplifiers for use in various amplifiers.

Conventionally, amplification elements of audio amplifiers are usually based on transistors. In the case of an amplifier using a transistor, the biggest problem is that the magnitude of the allowable input bias voltage (normal base voltage) (typically 0.6V or less) is low. In other words, in the case of transistors, the output (usually collector current or voltage) is generated at a target value below the allowable input voltage. However, when the transistor exceeds 0.6V, the waveform distortion is significantly increased. FIG. 3A shows a normal output state (the figure shows a waveform of current output but becomes a corresponding output voltage when coupled with a load resistor) for a base input voltage of 0.6 V or less, and FIG. 3B shows a base input. A diagram showing waveform distortion with respect to the output when the voltage exceeds 0.6V.

In order to solve the waveform distortion problem of the target output due to the imbalance of the input bias voltage, there is a method of compensating the input bias voltage through the negative feedback circuit with a part of the output signal reversed in this case. Due to the time delay (Td) passing through (see FIG. 4C), the input waveform itself, which is actually synthesized and compensated, becomes a waveform in which distortion occurs, and the output waveform inevitably becomes a distortion waveform inevitably. have. 4A and 4B are exemplary amplifiers for compensating for an input bias voltage, and FIG. 4C is a diagram illustrating a distorted input waveform obtained by combining an input waveform and a negative feedback waveform, and a distorted output waveform corresponding to the input waveform. . In the case of such a negative feedback compensation method, the amplification stage is low, and thus, the amplification stage must be formed in multiple stages. Accordingly, the waveform deformation of each stage is inevitably increased as the number of stages increases. there is a problem.

As a complement to the bias input voltage characteristics of the transistor, there is a method using a field effect transistor (FET) having a gate voltage of about 1.5V. However, in the case of the FET, due to the temperature change and the characteristic error of the FET itself, the operation is unstable and is used only in some special circuits.

The tube amplifier used in the past has a bias voltage of 1.5V or more and amplification gain, so the number of amplifier stages is small. Therefore, since there is almost no intermodulation distortion in an audio amplifier circuit using a vacuum tube, it is often observed that music specialists, especially in the professional domain, listen to music with a tube amplifier. Despite these advantages, however, vacuum tube amplifiers are not practical in modern times due to disadvantages such as power consumption, volume, and sound quality that change with time, manufacturing, and maintenance costs, as is known.

As a digital circuit that makes use of the advantages of the vacuum tube and supplements the disadvantages, there is a PWM (Pulse Width Modulation) type audio amplifier called "class D amplifier". 5 shows an example of a "class D amplifier". Referring to FIG. 5, the class-D amplifier has a sawtooth oscillator built in, and compares the sawtooth wave W1 and the input signal Vi6 with the comparator COMP6 to compare the input signal Vi6 with the sawtooth voltage W1. While high (see Fig. 6, P), the output is high (W2) (see Fig. 6, Q). This square wave has a pulse width converted corresponding to the magnitude change time between the input signal and the sawtooth wave (PWM modulation). The comparator output W2 switches the MOSFET at the output stage (W3) (FIG. 6, R solid line). At this time, the output signal W3 includes a large number of harmonics because of the switched square pie which turns ON / OFF the power supply voltage supplied to the output terminal, and the duty ratio changes according to the magnitude of the input voltage. When the width of the ON signal is wide, the output signal W3 has a high average voltage, and when the width of the ON signal is narrow, the average voltage is low (dashed line in Fig. 6, R). The output signal W3 is passed through a low pass filter (LPF: Low Pass Filter) to integrate and remove harmonics to obtain an analog output signal (FIG. 6, S).

However, the problem with this "class D amplifier" is that the LC filter has to be connected in multiple stages to flatten the square wave (that is, to remove the harmonic content) of the output signal, thereby increasing the volume of the coil and There is a problem that requires a high level of skill in the blocking operation. In addition, the sawtooth oscillation frequency must be increased to the maximum frequency at which the MOSFET can be switched to improve sound quality, which is why high filtering and switching techniques are required.

The present invention is to solve the above problems, it is possible to eliminate the distortion of the output waveform, while generating an output close to the original sound or analog signal, while eliminating the multi-stage filter, small volume and burdensome high filtering It is an object of the present invention to provide an analog signal amplification method which is simple and easy to manufacture and does not require any technology and switching technology, and an amplification device integrated with a semiconductor using this method.

In addition, the present invention omits the intermediate D / A conversion process in the combined state of a digital device such as a CDP and a modern power amplifier, and directly connects the digital information to the amplifier of the present invention. An object of the present invention is to provide an amplifier for inputting a digital information signal including a PWM signal capable of solving the problem.

In addition, an object of the present invention is to provide a sawtooth oscillator used in the amplifier or amplifying element.

In addition, an object of the present invention is to provide a power amplifier for use in the amplifier or amplifier.

1 is a schematic diagram illustrating one embodiment of an analog signal amplifier according to the present invention;

2a shows a waveform at each stage of the amplifier according to FIG. 1;

FIG. 2B is an enlarged detailed view showing a correspondence relationship between an input signal and an output signal in the waveform of FIG. 2A; FIG.

2C is a diagram showing an inverse relationship between an input signal and a second sawtooth wave when the output signal is doubled.

2D is a view showing a change in amplification degree of an output signal according to a change in amplitude of a first sawtooth wave.

2E illustrates one embodiment of a sawtooth wave generating circuit.

Fig. 3A is an input / output conversion characteristic diagram of a transistor in the case of a small input signal in the prior art.

3B is an input / output conversion characteristic diagram of a transistor in the case of a large input signal in the prior art.

4A is a conceptual diagram of negative feedback in a transistor one-stage amplification circuit as a prior art;

4B is a negative feedback conceptual diagram of an integrated circuit device including transistors according to the prior art;

4c is a conceptual diagram of distortion of an output waveform according to a negative feedback signal delay in the prior art;

5 is a system diagram of a class-D amplifier in the prior art.

6 is an operational waveform diagram of a class-D amplifier in the prior art;

7 is an overall circuit diagram of an analog signal amplifier according to one embodiment of the invention.

8 is a circuit diagram of a power amplifier used in the amplifier according to an embodiment of the present invention.

9 is a circuit diagram of an amplifier used for PWM signal input as in accordance with an embodiment of the present invention.

10 is a block diagram (example: CD player) showing the structure of a conventional digital apparatus.

11 is a block diagram showing a configuration of a PWM signal amplifier according to the present invention.

12 is a block diagram of a digital information (PCM signal) amplifier according to the present invention.

Fig. 13 is a circuit diagram showing an amplifier for digital information (PCM signal) input according to the present invention.

14 is a curve diagram illustrating a comparison between analog output waveforms and related waveforms according to the present invention;

15 is a curve diagram illustrating the relationship between an analog input waveform and an output waveform according to the present invention;

* Explanation of symbols for main parts of the drawings

1 to 6

101: reference tooth wave oscillation circuit,

First sawtooth wave (Win): Sawtooth wave output of the input signal voltage level,

Second sawtooth wave (Wout): Sawtooth wave output of the output signal voltage level,

102: comparator (COMP), 103: one-shot vibrator,

104: first buffer amplifier BUF1, 105: analog switch (or high speed switch),

106: second buffer amplifier (BUF2), 107: push-pull amplification circuit (current booster),

108: low pass filter (LPF), 109: output terminal 0 point control circuit

A: Input waveform of input signal and first sawtooth wave

B: comparator output waveform of A of FIG. 2A

C: Output waveform of one short vibrator (control input signal of analog switch)

D: voltage extraction point in second sawtooth wave by pulse of C of FIG. 2A

E: Voltage waveform charged to C2

F: Waveform filtered through LPF

P: Input waveform of input signal (Vi6) and sawtooth wave (W1) in class D amplifier

Q: Comparator output waveform of Fig. 6, P

R: Output waveform from class D amplifier

S: Output waveform filtered through LPF

7 to 15

(Figure 7)

7-A: Clock Oscillator

7-B: Second sawtooth wave oscillator circuit

7-C: Third Sawtooth Oscillator Circuit

7-D: Comparator Circuit

7-E: Analog switch circuit (or high speed switch circuit)

7-F: One short vibrator

7-G: Pulse Delay Circuit

PTL: First sawtooth wave signal of input signal level

PTH: Second sawtooth wave signal at output signal level

NTH: Third sawtooth signal at output signal level

A-SW1: Analog Switch (or High Speed Switch) 1

A-SW2: Analog Switch (or High Speed Switch) 2

LPF1: Low Pass Filter 1

LPF2: Low Pass Filter 2

CBST1: Power Amplifier (Current Booster)

P-OUT: Amplified output signal of input signal and in phase

N-OUT: Amplified output signal reversed from input signal

SP1: Speaker 1

(Figure 8)

IN: Analog Input Signal

(Figure 9)

9-A: amplitude modulated (PWM) input signal

9-B: Ascending time detector from low level (L) to high level (H)

RESET: High level pulse output terminal when PWM rises

9-C: Falling point detector from high level (H) to low level (L)

QHL: High level pulse output terminal when PWM falls

9-D: Second sawtooth wave generation and sawtooth wave reset circuit part

9-E: One short vibrator section

9-F: Analog switch and buffer circuit

LPF4: Low Pass Filter 4

CBST4: Power Amplifier 4 (Current Booster)

(Figure 13)

13-A: Pulse Code Modulated (PCM) Input Signal

13-B: Digital Information (PCM Signal) Processing Control Unit

13-C: Storage Comparison

13-D: Second sawtooth wave generation and sawtooth wave reset circuit

13-E: One short vibrator section

13-F: Analog Switch and Buffer Circuit

LPF5: Low Pass Filter 5

LPF6: Low Pass Filter 6

CBST5: Power Amplifier 5 (Current Booster)

CBST6: Power Amplifier 6 (Current Booster)

(Figure 14)

A: first sawtooth wave and input signal

B: First pulse which is comparator output

C: ideal second pulse

D: actual delayed second pulse

E: ideal analog waveform

F: Analog waveform with inverted top

O: First sawtooth wave and input signal

P: 1st pulse which is comparator output

Q: blanking pulse

R: ideal second pulse not generated

S: delayed second pulse not generated

T: ideal analog waveform

U: Analog waveform with upper limit

(Figure 15)

a: input analog signal and first sawtooth wave

b: first pulse

c: ideal second pulse

d: actual second pulse delayed

e: second sawtooth wave without pulse delay

f: Amplified output waveform by ideal second pulse

g: Output waveform of which upper limit is limited by delayed second pulse

h: second sawtooth wave delayed by pulse delay

i: Output waveform corrected by delayed second sawtooth wave

In order to realize this object, the analog signal amplification method in the analog signal amplifier according to the first aspect of the present invention is sufficiently large in frequency than the maximum frequency of the input signal of the amplifier, and is equal to or slightly larger than the maximum amplitude of the input signal. Outputting a first sawtooth wave having an amplitude and having a predetermined period; and comparing the first sawtooth wave with an input signal and outputting a first pulse having the output high for a period in which the first sawtooth wave is larger than the input signal. And outputting a narrow one-shot second pulse at each start point of the high period of the first pulse, and having an amplitude equal to or slightly larger than the maximum amplitude of the output signal of the amplifier, Outputting a second sawtooth wave having the same period, and a second sawtooth wave at the corresponding portion by matching each high viewpoint portion of the second pulse with the second sawtooth wave; Extracting the output voltage continuously using the voltage position as a sample, and charging the extracted voltage to a capacitor by a high-speed switch to maintain the extracted voltage, and removing the corrugation of the output waveform to facilitate filtering. Equipped.

The analog signal amplification method in the analog signal amplifier according to the second aspect of the present invention for achieving the above object is sufficiently larger in frequency than the maximum frequency of the input signal of the amplifier, and is equal to or slightly larger than the maximum amplitude of the input signal. Outputting a first sawtooth wave having an amplitude and having a predetermined period; and comparing the first sawtooth wave with an input signal and outputting a first pulse having the output high for a period in which the first sawtooth wave is larger than the input signal. And outputting a narrow one-shot second pulse at each start point of the high period of the first pulse, and having an amplitude equal to or slightly larger than the maximum amplitude of the output signal of the amplifier, Outputting a second sawtooth wave having the same period, and transmitting the second sawtooth wave at the corresponding portion by matching each high view point portion of the second pulse with the second sawtooth wave; Extracting a first output voltage continuously using a sample as a position; outputting a third sawtooth wave that is an inverse phase of the second sawtooth wave; and corresponding each high viewpoint portion of the second pulse and the third sawtooth wave Continuously extracting the second output voltage using the third sawtooth wave voltage position in the corresponding portion as a sample, and charging the capacitor by the analog switch with the extracted first output voltage and the second output voltage. Maintaining a regulated voltage, removing the corrugation of the output waveform to facilitate filtering, and obtaining a double output signal using the filtered first and second outputs.

The third feature feature of the present invention further includes the step of adjusting the gain of the amplifier by adjusting the amplitude of the first sawtooth wave in the first feature feature or the second feature feature.

In addition, the fourth feature configuration of the present invention, in the first feature configuration or the second feature configuration, amplitude-modulating the input signal by adjusting the amplitude of the first sawtooth wave through a second input signal separate from the input signal. It further comprises a step.

In addition, the fifth aspect of the present invention provides an amplifying element integrated with a semiconductor using the first to fourth aspect.

Next, a preferred embodiment according to the present invention will be described with reference to the accompanying drawings.

1 is an analog signal amplifier device according to an embodiment of the present invention, wherein the sawtooth signal oscillated in the sawtooth oscillator circuit of 101 is a frequency sufficiently higher than the maximum frequency of the input signal, has a constant period and has good linearity, There are two levels of output. One is output as a first sawtooth wave Win slightly larger than the maximum peak voltage of the input signal and is input to the non-inverting input (+) of the comparator 102, and the other is a second slightly larger than the maximum amplitude required in the output signal. It is output as a sawtooth wave (Wout) voltage, and is used by the first buffer amplifier (BUF1) 104 to use an analog switch (or a high speed switch, the present specification uses a mixture of two types because the analog switch acts as a high speed switch). When is turned on, C2 is converted into sufficient power to quickly charge and then connected to the input of the analog switch 105.

The input signal Vi is input to the inverting input (-) of the comparator COMP 102 and the first sawtooth wave Win is connected to the non-inverting input (+) so that these two signals are compared and eventually the input signal. The first pulse is output as a PWM modulated signal whose pulse width varies according to the size of. The first pulse coming out of the comparator 102 is connected to the trigger input of the one-shot vibrator 103 and is converted into a pulse having a constant narrow width at the pulse start position of the input PWM signal to output the second pulse. This output is connected to the control terminal of the analog switch 105 to turn on the analog switch 105 during the pulse period. The output of the analog switch 105 is connected to the non-inverting input (+) of the second buffer amplifier (BUF2) 106 for driving the push-pull power amplification circuit 107, to which the capacitor C2 is connected. It charges the voltage of the first buffer amplifier 104 when the analog switch 105 is ON, and maintains the voltage even when the analog switch 105 is OFF. The inverting input terminal (-) of the second buffer amplifier 106 is connected to the output of the output zero point control circuit 109 which controls the output terminal of the push-pull power amplifier circuit 107 to always be equal to the common ground voltage. do. The output of the second buffer amplifier 106 is connected to the push-pull power amplifying circuit 107, and the output of the push-pull power amplifying circuit 107 is connected to the input of the output zero point control circuit 109 and the input of the LPF 108. The output of the LPF 108 is connected to the output terminal Vo again.

Such a circuit scheme of the present invention is referred to as "CLASS-E AMPLIFIER" or "JIN AMPLIFIER".

Next, an operation of an E-class amplifier, that is, a true amplifier, according to the present invention will be described with reference to FIGS.

The analog input signal Vi and the first sawtooth wave Win are compared by the comparator 102 (A in FIG. 2A), and the period of time when the sawtooth signal Win is larger than the input signal Vi is set to HIGH. And a first pulse having the opposite state to the LOW state (B in Fig. 2A). The first pulse is supplied to the input of the one-shot vibrator 103 and shaped into a second pulse in a narrow pulse state at the start of the first pulse (C in Fig. 2A). This second pulse width may be a time sufficient for the analog switch 105 to be turned on to charge the capacitor C2. In this operation, the change in the input signal voltage is converted into a change in time by comparing the input voltage of the analog input signal Vi and the rise period RAMP of the first sawtooth wave Win, and the change in time is the first sawtooth rise period. It occurs because the position of the second pulse changes in (RAMP). In other words, when the input signal voltage is low, the second pulse is generated near the start point of the sawtooth wave, and when the input signal voltage is high, the second pulse is generated far from the start point of the sawtooth wave. That is, the magnitude of the input signal Vi and the generation position of the second pulse have a constant correspondence with each other.

The second sawtooth wave is a sawtooth wave having the same period as the first sawtooth wave and having the maximum amplitude required in the output signal, and is supplied to the input of the analog switch 105 by the first buffer amplifier BUF1 104. The control terminal of the analog switch 105 is controlled by the second pulse to turn on / off the analog switch 105. The analog switch 105 can be turned on only during the pulse generation period of the second pulse to extract the voltage of the second sawtooth wave (see the small circle display position in Figs. 2A and D) (operation 2).

A process of generating the input signal Vi and the output signal will be described in more detail with reference to FIG. 2B. In FIG. 2B, when the input signal Vi is in the a position, when the first sawtooth wave Win rises and passes a ', the output of the comparator 102 generates a first pulse as in a1, and the one-shot vibrator 103 Is shaped into a narrow second pulse, such as a2, and is supplied to the control terminal of the analog switch 105 to charge the capacitor C2 with the voltage of a " of the second sawtooth wave Wout. When the b position is lowered and the first sawtooth wave Win rises and passes b ', the output of the comparator 102 generates a first pulse like b1 and a second narrow like b2 in the one-shot vibrator 103. A pulse is shaped and supplied to the control terminal of the analog switch 105 to charge the capacitor C2 with the voltage of b "of the second sawtooth wave Wout.

Next, when the input signal Vi descends and is at the c position, when the first sawtooth wave Win rises and passes c ', the output of the comparator 102 generates a first pulse as in c1 and the one-shot vibrator 103 ) Is shaped into a narrow second pulse, such as c2, and supplied to the control terminal of the analog switch 105 to charge the capacitor C2 with the voltage of c "of the second sawtooth wave Wout.

The voltage extracted in the operation 2 is charged in the capacitor C2. This charging voltage is maintained by the capacitor C2 until the next charging (FIGS. 2A, E). The voltage charged in the capacitor C2 drives the push-pull power amplifier circuit 107 by the second buffer amplifier (BUF2) 106. Also, for example, a low pass filter (LPF) may be connected to the second buffer amplifier 106 as necessary.

The push-pull power amplification circuit 107 generally uses a class AB amplification circuit as a power amplifier for driving a load. Since the voltage waveform of the capacitor C2 is similar to the square wave as shown in E of FIG. 2A, the LPF 108 of the output terminal is integrated to remove the high frequency component and output only the audio signal.

In this conversion process, a time change proportional to the input signal is generated as the second pulse based on the first sawtooth wave having good linearity, and the capacitor is extracted by extracting the voltage at the second pulse generating position from the second sawtooth wave equal to the maximum amplitude of the output signal. Charging to C2 and amplifying the voltage by the push-pull power amplifying circuit 107 outputs the input signal Vi to the output signal voltage Vo.

Here, the amplification degree A of the amplifier is represented by the following equation.

(Equation 1)

A = [second tooth amplitude / first tooth amplitude] (times)

That is, the amplification factor is determined by the ratio of the first sawtooth wave amplitude to the second sawtooth wave amplitude. When the amplitude of the first sawtooth wave Win1 is small as shown in the left side of FIG. 2D, the output signal corresponding to the second sawtooth wave becomes relatively large, resulting in a large amplification degree, and the amplitude of the first sawtooth wave Win2 as shown in the right side of FIG. 2D. In this case, since the output waveform corresponding to the second sawtooth wave becomes relatively small, the amplification degree is small. That is, the magnitude of the vertical amplitude of the first sawtooth wave and the degree of amplification have an inverse relationship with each other.

An example of a circuit for adjusting the amplitude of the first sawtooth wave is shown in FIG. 2E. That is, referring to FIG. 2E, the current of the constant current circuit can be changed by changing the value of the emitter resistance Re of Q1, and the charging time of the capacitor changes according to the change of the current, so that the amplitude of the first sawtooth wave can be adjusted. have. This allows the amplifier gain to be adjusted by adding or subtracting the amplitude of the first sawtooth wave (equivalent to the effect of adjusting the slope of the sawtooth wave), which in the case of audio equipment is apparently equivalent to, for example, volume control. do.

As shown in FIG. 2C, a third sawtooth wave in which the phase of the second sawtooth wave is inverted may be made, and an inverted output may be obtained by extracting a voltage from the third sawtooth wave by the second pulse. When driving the load by amplifying the uninverted first output and the inverted second output, a double output voltage can be obtained, and thus it is easy to configure a BTL (Bridge Tied Load) amplifier.

As described above, the present invention generates the first pulse by the comparison operation of the input signal Vi and the first sawtooth wave Win in the comparator COMP 102 (operation 3), and forms the second pulse. The voltage at the point of occurrence of the second pulse is extracted from the two sawtooth waves (operation 4), charged to the capacitor C2, and amplified by the push-pull power amplification circuit 107 (operation 5) and output as Vo. Operation 3 enables the construction of a circuit having a good linearity of the sawtooth wave as a conversion operation. As a result, an effect of eliminating the distortion caused by intermodulation distortion can be obtained. In operation 4, the second pulse generated in operation 3 remains at the output. The push-pull power amplifying circuit 107 in operation 5 can be applied to a circuit currently used in general. Since the push-pull power amplifier circuit 107 has an amplification degree of 1, there is almost no problem in the input bias voltage characteristic of the transistor. As described above, since the present invention does not directly use the amplification operation by the transistor, it is possible to fundamentally solve the distortion factor of the output waveform. In particular, the input signal Vi is the first irrespective of the input bias voltage characteristic of the transistor. Since it is only related to the linearity of the sawtooth wave Win and the second sawtooth wave Wout, it is irrelevant to the characteristics of the transistor device which gives distortion factors of the output waveform.

Next, various analog signal amplifiers and elements used therein will be described according to still other embodiments of the present invention.

7-A of FIG. 7 is a clock oscillation circuit by the time constant of the resistor R1 and the capacitor C1, and a pulse is output to the output terminal OUT. The resistor R2 of the clock oscillating circuit 7-A is a resistor for charging voltage discharge of the capacitor C1. The inverter IC2A and the other inverter IC2B connected to the output terminal OUT of the clock oscillating circuit 7-A are used for buffering and inverting the IC1 output of the clock oscillating circuit 7-A. The positive pulse inverted by the inverter IC2A is used for synchronizing the second sawtooth wave PTH of the second sawtooth oscillating circuit 7-B. The pulse delay circuit 7-G and the inverter IC2B The sub-pulse output via is used for synchronization to generate the third sawtooth wave NTH of the third sawtooth oscillation circuit 7-C.

When the output stage of the inverter IC2A becomes the HIGH level in the second sawtooth wave oscillating circuit 7-B of FIG. 7, the current flows in a path composed of the resistor R3, the capacitor C2, the base and the emitter of the transistor Q1, and again the capacitor C2. Charges the capacitor C2. At this time, the collector and the emitter of transistor Q1 are turned on to discharge the voltage of capacitor C3. In other words, the sawtooth wave is reset. When the output stage of the inverter IC2A becomes the low level again, the voltage charged in the capacitor C2 of the second sawtooth oscillating circuit 7-B becomes the resistor R3, the output stage of the inverter IC2A, and the second sawtooth oscillating circuit 7-. Discharge via diode D1 of B) (normally, the circuit composed of C2 and D1 is called clamp circuit), and the base and emitter gap of transistor Q1 of second sawtooth oscillator circuit 7-B is -0.6V. The reverse voltage causes the collector and emitter of transistor Q1 to turn off. From this point on, the capacitor C3 starts charging at a constant speed by the constant current supplied from the constant current circuit of the transistor Q2 to the capacitor C3 of the second sawtooth oscillating circuit 7-B. Since the transistor Q2 is controlled so that the voltage across the resistor R6 is always constant by the constant voltage diode Z1 connected to the base of the transistor Q2, the current flowing through the resistor R6 is a constant current, and the current flowing through the collector of the transistor Q2 is also a constant current. A constant current is supplied to the capacitor C3 to generate a sawtooth wave having good linearity. The transistor Q1 discharges the charging voltage of the capacitor C3 instantaneously to generate a continuous sawtooth wave. The capacitor C2 functions to connect the circuit of the inverter IC2A and the transistor Q1 circuit in an alternating current, and cuts off the direct current. Even if the voltage of + -V2 is changed by the capacitor C2, it does not affect the + -V1 circuit of the clock oscillation circuit 7-A and operates normally. Therefore, it is possible to change the voltage of + -V2 of the second sawtooth wave oscillating circuit 7-B, which is proportional to the peak-to-peak voltage of the sawtooth wave. It is also proportional to the maximum output voltage of the amplifier. The amplifier output can be changed without changing the circuit by changing the + -V2 voltage of the second sawtooth oscillator circuit 7-B. In the second sawtooth wave oscillating circuit 7-B, the transistor Q3 buffers the sawtooth wave voltage generated in the capacitor C3 to lower the output impedance and drive the resistors R7 and R8. PTH, the output of transistor Q3, is used as the second sawtooth wave of the output level of the amplifier. The sawtooth wave is divided into resistors R7 and R8 to convert the first sawtooth wave PTL of the same input signal level with the same period.

7-C of FIG. 7 is a third sawtooth oscillation circuit which simultaneously generates a third sawtooth wave when the second sawtooth wave is generated. When the output stage of the inverter IC2B is at the LOW level, the third sawtooth oscillator 7-C charges the capacitor C4 via the emitter and base of the transistor Q4, the capacitor C4, and the resistor R9. Flow. At this time, the collector and the emitter of transistor Q4 are turned on to discharge the voltage of capacitor C5. In other words, the sawtooth wave is reset. When the output terminal of the inverter IC2B becomes the high level again, the charging voltage of the capacitor C4 is discharged via the diode D2, the output terminal of the inverter IC2B, and the resistor R9 (usually a circuit composed of the capacitors C4 and D2 is called a clamp circuit). ), The base and emitter of transistor Q4 become reverse voltage at + 0.6V, and the collector and emitter of transistor Q4 are turned off. At this time, the capacitor C5 starts charging at a constant speed by the constant current supplied from the constant current circuit of the transistor Q5 to the capacitor C5 of the third sawtooth oscillation circuit 7-C. Since the transistor Q5 is controlled so that the voltage across the resistor R12 is always constant by the constant voltage diode Z2 connected to the base of the transistor Q5, the current flowing through the resistor R12 is a constant current, and the current flowing through the collector of the transistor Q5 is also a constant current. A constant current is supplied to the capacitor C5 to generate a sawtooth wave having good linearity, and a continuous sawtooth wave is generated by instantaneously discharging the charging voltage of the capacitor C5 by the transistor Q4. Here, the capacitor C4 functions to connect the circuit of the inverter IC2B and the transistor Q4 circuit in an alternating current while cutting off the direct current. Even if the voltage of + -V2 of the third sawtooth oscillation circuit 7-C is changed by the capacitor C4, it does not affect the + -V1 circuit of the clock oscillation circuit 7-A and operates normally. Therefore, it is possible to change the voltage of + -V2 of the third sawtooth wave oscillating circuit 7-C, which is proportional to the peak-to-peak voltage of the sawtooth wave, and also to the maximum output voltage of the amplifier. Is also proportional. By changing the + -V2 voltage, the amplifier output can be changed without changing the circuit. In the third sawtooth oscillation circuit 7-C, the transistor Q6 buffers the sawtooth wave voltage generated in the capacitor C5 to lower the output impedance and drive the resistor R13. NTH, the output of transistor Q6, is used as the third sawtooth wave of the output level of the amplifier.

7-D of FIG. 7 compares the analog signal supplied from the comparator IC3 to the input terminal IN and the first sawtooth wave PTL to generate an output high for a period in which the first sawtooth wave PTL is larger than the input signal. Act as a radar This high signal has a variable pulse width in accordance with the magnitude of the input signal, and is shaped into a narrow pulse at the start of the pulse by the IC4 of the one-shot vibrator unit 7-F.

That is, the one-shot vibrator 7-F of FIG. 7 functions to input the first pulse output from the comparator IC3 to form a narrow second pulse. Here, the pulse width is determined by the resistor R16 and the capacitor C7. In the one-shot vibrator section 7-F, the narrow pulse of IC4 is output as a constant pulse from the Q terminal, and the control terminal C of analog switch A-SW1 and analog switch A-SW2 of the analog switch circuit 7-E is different. Supplied to. At the time when the first pulse rises, the second pulse is generated with the pulse width of the resistance R16 and the time constant of the capacitor C7 in the one-shot vibrator portion 7-F. It takes some time from the time when the first pulse rises to the time when the second pulse rises. This is called the input / output delay time Tplh of the one-shot vibrator, and is usually delayed by about 300 nS in CMOS. As shown in Fig. 14B, when the analog input signal is near the maximum value in the comparator, the first pulse is generated, and the first pulse is input to IC4 of the one-shot vibrator 7-F. If there is no delay time Tplh between the input and output (0nS) in the IC4, the second pulse is generated as shown in C of FIG. 14, and the analog output waveform is output at the maximum voltage as shown in E of FIG. 14. However, since there is a delay time Tplh of IC4, a second pulse is generated after the delay time Tplh as shown in FIG. At this time, if the second sawtooth wave (F of FIG. 14) passes the highest point of the sawtooth wave and is near the lowest point, the lowest voltage is extracted by the second pulse (D of FIG. 14), and the analog output is rapidly changed to the lowest voltage (FIG. 14). F). This output can damage the speakers when driving them through the power amplifier. No matter what happens, the output waveform should not sustain any drastic changes. A method for preventing this phenomenon is described below.

The blanking pulse (7-H of FIG. 7, Q of FIG. 14) generated from the previous high by the delay time Tplh at the time of the transition from the highest point to the lowest point of the second sawtooth wave (O in FIG. 14) is obtained. It is applied to the reset terminal (RESET) of IC4 (7-F of FIG. 7). While the blanking pulse is applied to the reset terminal RESET, the second pulse is not output even when the first pulse is input to the input A of the IC4 of the one-short vibrator. If the first pulse near the maximum value of the input signal is input to the input A of the IC4 of the one-short vibrator as shown in Fig. 14-P, the second pulse is not output because the first pulse belongs to the blanking pulse period (Fig. 14). S). At this time, it is maintained at the previously extracted voltage (U in FIG. 14; is limited), and prevents the output voltage from suddenly inverting.

With reference to Fig. 15, the second sawtooth wave or the third sawtooth wave is delayed to correct the output operation range.

In the comparator circuit 7-D of Fig. 7, the analog signal supplied from the comparator IC3 to the IN terminal is compared with the first sawtooth wave PTL for a period in which the first sawtooth wave PTL is larger than the input signal IN. It acts as a comparator that generates the output high. This high signal has a pulse width that varies depending on the magnitude of the input signal, and is shaped into a narrow pulse at the start of the pulse by IC4 of the one-shot vibrator 7-F in FIG.

Referring to FIGS. 7 and 15, a first pulse output from the comparator IC3 of the comparator circuit 7-D by the first sawtooth wave of the input signal level and the input signal IN (b of FIG. 15). This is a one-shot vibrator shaping the narrow second pulse as the input. Ideally, the second pulse is generated at the time when the first pulse is raised (FIG. 14C), but it takes some time from the time when the first pulse is raised to the time when the second pulse is raised (D in FIG. 14). This is called the input / output delay time Tplh of the one-shot vibrator, and is usually delayed by about 300 nS in CMOS. This delay time Tplh is eccentric in the extraction point when extracting the voltage of the second sawtooth wave or the third sawtooth wave from the analog switch (7-E in FIG. 7) (g in FIG. 15), and the upper part of the output waveform is distorted to maximize the output. The range becomes narrower. This phenomenon becomes even more negligible at high sawtooth frequencies. Even if this phenomenon is eliminated, there is a limit in reducing the delay time of the one-short vibrator. Therefore, the pulse delay circuit 7-G of FIG. 7 delays the reset pulse of the sawtooth oscillator by the delay time Tplh, and then the As a result of applying to the reset circuit, a sawtooth wave (second or third sawtooth wave) of the output level is delayed as shown in Fig. 15-h, and extracted from the analog switch circuit by the second pulse (d of Fig. 15) actually output. The maximum output voltage without distortion of the output can be extracted (I in FIG. 15) (the third sawtooth oscillation circuit 7-C in FIG. 7 is described as the second sawtooth wave in FIG. 15).

Next, the sample / hold circuit 7-E composed of the analog switch (or the high speed switch) in Fig. 7 will be described. In the second sawtooth oscillator circuit 7-B, the second sawtooth wave PTH of the output level is supplied to the I terminal of the analog switch A-SW1 of the sample hold circuit 7-E and the pulse of the control terminal C is applied. The capacitor C10 and the capacitor C8 are charged during the period (C8 is a sufficiently large capacity than C10), and then buffered by transistor Q7 to pass-through filter LPF1 (sample / hold circuit 7-E in FIG. 7). Located in the upper right side of the outside), the amplified analog signal having the same phase as the input signal is output to the P-OUT terminal. In addition, the third sawtooth wave NTH of the output level is supplied from the third sawtooth oscillator circuit 7-C to the terminal I of the analog switch A-SW2 and the capacitor C13 and the capacitor during the pulse period of the control terminal C. Charge C9 (C9 is larger than C13), again buffered by transistor Q8, and located at the lower right outside of the other low pass filter LPF2 (see FIG. 7 outside the sample / hold circuit 7-E). ), The amplified analog signal out of phase with the input signal is output to the N-OUT terminal. The voltage charged in the capacitor C10 should be kept constant until the next charge, but due to the large circuit impedance of the capacitor C10, the capacitance between the input (I) and the output (O) of the analog switch (A-SW1) or Due to the inter-pattern capacitance of the PCB, a reflow of the same shape as the second sawtooth wave PTH of the second sawtooth wave oscillation circuit 7 -B appears. This ripple is not completely eliminated even though the low pass filter LPF1 is passed, resulting in noise. Therefore, the third sawtooth wave (NTH) signal of the third sawtooth wave oscillation circuit (7-C) that is out of phase with the second sawtooth wave (PTH) of the second sawtooth wave oscillation circuit (7-B) is connected to the analog switch circuit 7-E. The voltage is divided by a small voltage by TC2 and capacitor C8 and superimposed on capacitor C10. By adjusting the trimmer capacitor TC2 so that the voltage of the reversed phase divided across the capacitor C8 is equal to the ripple voltage, the ripple can be canceled out.

The voltage charged to the capacitor C13 of the analog switch circuit (7-E) must also remain constant until the next charge, but the input (I) and output of the analog switch A-SW2 are very large because the circuit impedance of the capacitor C13 is very large. Reflow of the same shape as the third sawtooth wave (NTH) is caused by the capacitance between the (O) or the capacitance between the patterns of the PCB. This ripple is not completely eliminated even though the low pass filter LPF2 is passed, resulting in noise. Thus, the second sawtooth wave PTH signal, which is in phase with the third sawtooth wave NTH, is divided by a small voltage by TC1 and the capacitor C9 of the analog switch circuit 7-E and superimposed on the capacitor C13. Ripple can be canceled by adjusting trimmer capacitor TC1 such that the voltage of the reversed phase divided across capacitor C9 is equal to the ripple voltage. The output signal P-OUT of the low pass filter LPF1 amplified in phase with the input signal IN of the comparator circuit 7-D is input to a power amplifier (CBST1: current booster) connected to the low pass filter LPF1. The power amplifier is amplified to drive the speaker SP1 connected to the power amplifier CBST1.

8 is a circuit diagram of the power amplifier CBST1. Since the speaker is connected between the output terminal OUT and the common ground terminal of the circuit, the output terminal OUT should always maintain the 0V potential having the DC characteristic. Its control method uses an operational amplifier IC30. The non-inverting terminal (+) of the operational amplifier IC30 is connected to the common ground terminal, and the inverting terminal (-) is connected to the output terminal (OUT) of the power amplifier (CBST1: current booster) by R31, and the output of the operational amplifier IC30 is Is connected to the base of transistor Q30 by R30 to control the bias voltage of transistor Q30. The capacitor C31 is connected between the inverting terminal (-) of the operational amplifier IC30 and the output so that the time constant of R31 x C31 is set to a large value so as to control the DC state without controlling the signal voltage.

In the operation of the power amplifier CBST1, if the output terminal OUT is increased in the + direction, the inverting terminal (-) of the operational amplifier IC30 is increased to +, the output is lowered to the-direction, and this change is a transistor. Since the base voltage of Q30 is lowered, the emitter voltages of transistors Q31 and Q33 are lowered, and the output terminal OUT is brought back to zero potential. In addition, if the output terminal OUT is lowered in the negative direction, the inverting terminal (-) of the operational amplifier IC30 is lowered to-so that the output becomes higher in the positive direction, and this change increases the base voltage of the transistor Q30. The output voltage (OUT) is brought back to zero potential because of high voltage.

9 is a conceptual diagram illustrating an amplification method when an input signal of an amplifier is input as a pulse width modulation (PWM) signal. Nowadays, many digital devices play digital recordings such as CDP. Many devices employ digital methods in processing signals until they are output as an audible sound. FIG. 10 is an example of a conventional digital signal processing device CD PLAYER, and the digitally processed signal in this device is analog signal conversion (D / A) and filtering (FILTER) of a digital signal for the last person to hear. After amplification (AMP), the audible sound is output. In this digital / analog conversion process and amplification process, there may be deformation of the signal, and a lot of circuit components are required.

FIG. 11 is a schematic diagram of a PWM signal amplifier. In the case of a device for processing a PWM signal inside a digital device, the amplifier is simply configured by connecting the PWM signal directly to the PWM input amplifier of FIG. 9 according to the present invention. There is no need for an analog conversion circuit and there is no distortion component of the signal, such as an amplification element, so that the signal can be amplified without distortion.

Hereinafter, a PWM input amplifier operation according to the present invention will be described with reference to FIG.

In Fig. 9, the PWM signal 9-A enters the input terminal IN. The PWM signal 9-A always has a constant period at which it rises from the low level to the high level. The time point is where the PWM signal is referenced. The width of the high pulse period of the PWM signal 9-A is a signal proportional to the magnitude of the signal. Then, the point of descending from the high level to the low level changes every cycle. When the PWM signal 9-A is input to the input terminal IN, the rising point detection unit 9-B detects a point of time from the low level to the high level and outputs a high pulse to the output terminal reset terminal RESET. This pulse causes current to flow through the resistor R41 and the capacitor C41 of the second sawtooth wave generation and sawtooth reset circuit section 9-D to the base and emitter of the transistor Q41 to turn on the collector and emitter of the transistor Q41. The capacitor C42 of the two-tooth wave oscillation circuit is instantaneously discharged. Subsequently, the output pulse of the reset terminal RESET drops to the low level, so that the transistor Q41 turns off and the capacitor C42 starts charging.

A constant current always flows through the resistor R44 connected to the emitter of the transistor Q42 by the constant voltage of the constant voltage diode Z41, and this current charges the capacitor C42 at a constant speed to generate a sawtooth wave having good linearity. The sawtooth wave is buffered by transistor Q43 and supplied to input terminal I of analog switches A-SW4. Further, the falling time detection unit 9-C detects the time when the voltage signal falls to the low level from the high level of the PWM signal 9-A input to the input terminal IN and outputs a high pulse to the output QHL. The generation time point of this QHL pulse is generated in proportion to the high pulse section of the PWM signal 9-A. That is, if the high level width of the PWM signal 9-A is narrow, it is generated near the starting point of the second sawtooth wave PTH previously generated by the reset terminal RESET. If the PWM high level width is wide, the reset terminal RESET is earlier. Is generated at a position far from the start of the second sawtooth wave PTH. This QHL pulse is input to the one-shot vibrator IC41 of the one-shot vibrator section 9-E and shaped into a narrow pulse, and is connected to the control terminal C of the analog switch A-SW4 of the analog switch and buffer circuit section 9-F. Is entered. While this narrow pulse (Q of IC41) is supplied, the analog switches A-SW4 are turned on to charge the voltage of the second sawtooth wave PTH to the capacitor C44. The voltage charged to the capacitor C44 is a voltage proportional to the high level width of the PWM signal 9-A, and the second sawtooth wave PTH of the output level is applied to the narrow pulse (Q of IC41) of the one-shot vibrator section 9-E. An analog signal extracted, held, and amplified at the time of occurrence, which is a continuous analog signal without valleys. This analog signal is buffered by transistor Q44 of the buffer circuit section 9-F and filtered by a low pass filter LPF4 connected to the buffer circuit section 9-F, and a power amplifier 4 CBST4 (current booster) connected to the low pass filter LPF4. ) To drive the speaker SP4. The above operation is repeated every cycle of the PWM signal.

FIG. 13 is a conceptual diagram illustrating an amplification method when an input signal of an amplifier is input as a pulse code modulation (PCM) signal according to an embodiment of the present invention. As described above, in recent years, many devices employing a digital method for audio signal processing. As a conventional example, the device of Fig. 10 is an example of a representative CD player which performs signal processing digitally, and the signal processed by this device usually converts a digital signal into an analog signal for the last human hearing (D / A). It filters and amplifies the output. In this digital / analog conversion process and amplification process, there may be deformation of the signal, and a lot of circuit components are required. In the case of a device processing a PCM signal inside a digital device as shown in FIG. 12, the amplifier is simply configured by directly connecting the PCM signal to the PCM input amplifier of FIG. 13 according to the present invention, and a digital / analog conversion circuit is required. Since there is no distortion component of the signal such as an amplifying device, it is possible to amplify the signal without distortion.

Hereinafter, the operation of the PCM input amplifier of FIG. 13 according to the present invention will be described.

In Fig. 13, the pulse code modulation (PCM) signal 13-A is input to the input terminal IN. The pulse code modulation (PCM) signal 13-A is a signal that serially transmits a digital value (eg, 24-bit value) obtained by sampling an analog signal at a constant period (for example, 44.1 KHZ) according to a predetermined rule. The signal includes a right signal, a left signal, a control signal, and other information. Although PCM signal 13-A is an example, it is possible to receive and process information by optical output, DSD (SUPER AUDIO) format, infrared (IrDA) communication, and IEEE1394 communication in addition to PCM. Collectively. The PCM signal 13-A input to the input terminal IN separates and processes each piece of information from the digital information (here, "PCM signal") processing control unit 13-B and generates a control signal. R-CH LATCH of the storage comparator 13-C by outputting the right signal data analyzed by the digital information (PCM signal) processing control unit 13-B to the RDTO terminal and then outputting a high pulse to the RCK terminal. ) To latch the value. The storage comparison unit 13-C includes a right latch (R-CH LATCH), a left latch (L-CH LATCH), a comparator 1 (24bit COM1), a comparator 2 (24bit COM2), and a counter (24BIT COUNTER). It includes. On the other hand, the left signal data analyzed by the digital information processing controller (Fig. 13-B) is output to the LDTO terminal, and then a high pulse is output to the LCK terminal to the left latch (L-CH LATCH) of the storage comparator 13-C. Latch the value. These latched values are digital values corresponding to the right and left analog magnitudes. The digital information (PCM signal) processing control unit 13-B outputs a high pulse to the CCLR terminal to reset the 24-bit counter. At this time, the output terminals B> AL and B> AR of the 24-bit comparator 1 (24 BIT COMP 1) and the 24-bit comparator 2 (24 BIT COMP 2) are both output at the low level. Because the 24-bit counter value of terminal B of the 24-bit comparator is cleared to 0 and the latch of terminal A is set to the PCM data value, so B is not greater than A, so B> AL, B> AR terminals Is negative and is output at the low level. At the same time, when the digital information (PCM signal) processing control unit 13-B outputs a high pulse to the start terminal START when there is a data start control signal, the resistances R51 of the second sawtooth wave generation and the sawtooth wave reset circuit unit 13-D, When current flows between the base and the emitter of the capacitor C51 and the transistor Q51, the collector and the emitter of the transistor Q51 are turned on. After the capacitor C52 is discharged, the capacitor C52 starts charging when the start terminal START is at a low level. At this time, the clock is output to the CCK of the digital information (PCM signal) processing control section (Fig. 13-B), and then the 24-bit counter of the storage comparator 13-C starts the up count operation. After the 24-bit counter starts up counting, if the counter value is larger than the latch value, the B> AL and B> AR terminals of the corresponding comparator output high level. That is, if the 24-bit counter value is larger than the right latch (R-CH LATCH), the B> AR terminal is output high and is input to the A terminal of the one short vibrator IC51 of the one short vibrator unit 13-E. The shaped signal is shaped into a narrow pulse, and the shaped signal is input from the analog switch and the buffer circuit 13-F to the control terminal C of the analog switches A-SW5. While a narrow pulse is supplied through the Q terminal of the one-short vibrator IC51, the analog switch A-SW5 is turned on to charge the voltage of the second sawtooth wave PTH to the capacitor C54. The voltage charged to the capacitor C54 is a voltage proportional to the value of the right signal of the PCM signal, and at the same time, the second sawtooth wave PTH of the output level is extracted from the point of occurrence of this narrow pulse (signal generated at the Q terminal of IC51), and then maintained. It is an amplified analog signal and is a continuous analog signal without valleys. The analog signal is filtered by a low pass filter LPF5 buffered by the transistor Q54 and connected to the analog switch and the buffer circuit 13-F, and the speaker SP5 is driven by the power amplifier 5 CBST5 (current booster) connected to the low pass filter LPF5. To drive. If the 24-bit counter value is larger than the L-CH LATCH of the storage comparison unit 13-C, the B> AL terminal is output high and the one-shot vibrator unit 13-E is one short. It is inputted to A of the vibrator IC52 and shaped into a narrow pulse, which is inputted to the control terminal C of the analog switches A-SW6 of the analog switch and the buffer circuit 13-F. While a narrow pulse is supplied from Q of the one-short vibrator IC52, the analog switches A-SW6 are turned on to charge the voltage of the second sawtooth wave PTH to the capacitor C56. The voltage charged in the capacitor C56 is a voltage proportional to the left signal value of the PCM signal, and the second sawtooth wave PTH of the output level is extracted at the time of generation of the narrow pulse (Q of the IC52) of the one-shot vibrator unit 13-E. It is a sustained and amplified analog signal, and is a continuous analog signal without valleys. The analog signal is buffered by the transistor Q55 of the analog switch and the buffer circuit unit 13-F, and then filtered by the low pass filter LPF6 to drive the speaker SP6 by the power amplifier 6 CBST6 (current booster). This operation is repeated every cycle of the PCM signal.

According to the above configuration, the present invention has the following effects.

First, while the base voltage and the collector voltage characteristics of FIG. 3A are non-linear and the voltage range is narrow, distortion is easily generated, and the linear range is also narrow, whereas the linearity of the first sawtooth wave is very easy. It can be produced well and there is no limitation on the voltage range. Therefore, since the linear range uses the full amplitude of the sawtooth wave ramp (RAMP), the intermodulation distortion does not occur for signals within the linear range.

Second, in the conventional IC amplifier circuit as shown in FIG. 4B, the output waveform is negatively feedbacked by Rf to the inverting input (-) to determine the amplification degree. Thus, the distortion of the output waveform is caused by the time delay Td by the negative feedback circuit. Occurs. However, since the present invention does not use a negative feedback, it is possible to fundamentally solve the distortion caused by the above time delay.

Third, in the amplification circuit composed of the class D amplifier shown in FIG. 5, since the square wave modulated by the PWM by the input signal Vi6 and the sawtooth wave W1 is used, the valley of the waveform is deep (R in FIG. 6) and filtering to fill it. It requires a lot of high technology and equipment. In addition, it is difficult to solve the noise problem radiated from the power amplification stage because the filtering at the output stage LPF. In addition, the change in the process of converting an input signal as an analog into a square wave as a PWM signal and converting it back into an analog signal is so large that it is practically impossible to reduce it to a complete original waveform.

However, in the present invention, since the voltage is extracted from the second sawtooth wave by the second pulse and charged in the condenser, the conversion is performed to the continuous waveform without the valley of the waveform. It is transformed without, so there is little distortion.

Fourth, it is true that even today's high-end amplifiers are difficult to faithfully reproduce the syllabus, and the present invention can faithfully reproduce the syllabus by amplifying the input signal as it is due to the effects of the first and second terms. have.

Fifth, in the case of changing the maximum output of the amplifier, the conventional amplifier method had to redesign everything from the ultra-amplified stage to the speaker output stage, but in the present invention to change the peak-to-peak voltage of the second sawtooth wave or the third sawtooth wave of the output level It is easy to change the maximum output by increasing the power supply voltage and changing the power capacity of the power amplifier.

Sixth, in order to construct a BTL circuit using the conventional amplifier method, the two-channel amplifier is inputted with the reverse phase signal of one channel output to the input of the other amplifier, and the phase difference between the two channels is more severe, which further worsens the signal distortion. . In the present invention, since the second sawtooth wave and the third sawtooth wave of the output signal level are simultaneously generated, the output signal of the inverse phase can be generated at the same time. The configuration is simple and the phase delay of the two channels is the same, so that the distortion is small.

Seventh, in the past, the digital signal reproduced in a digital device such as a CDP and the like converted to an analog signal, and the filtered output signal is amplified and reproduced by the amplifier, but the digital signal processed in the digital device according to the present invention directly By inputting and reproducing the signal, it can be reproduced without distortion of the signal during digital / analog conversion and there is a circuit saving effect. In addition, long distance connection is possible without noise.

Eighth, that is, the present invention is not related to the characteristics of transistors that have a negative effect on the output waveform, and thus, if such configuration and advantages are utilized, the small signal amplifier of the analog signal, the power amplifier of the analog signal, the amplifier for driving the speaker, the integrated circuit Excellent performance can be obtained in the semiconductor devices, etc., compared to existing products.

Although the preferred embodiments and the effects thereof have been described as described above, the present invention is not limited thereto, and various changes and modifications can be made by those skilled in the art without departing from the following claims and their technical ideas. Of course.

Claims (19)

As an analog signal amplification method in an analog signal amplifier, Outputting a first sawtooth wave having a frequency sufficiently larger than the maximum frequency of the input signal of the amplifier, having an amplitude equal to or slightly larger than the maximum amplitude of the input signal, and having a predetermined period; Comparing the first sawtooth wave with the input signal and outputting a first pulse that makes the output high for a period in which the first sawtooth wave is larger than the input signal; Outputting a narrow one-shot second pulse at each start point of the high period of the first pulse; Outputting a second sawtooth wave having an amplitude equal to or slightly greater than the maximum amplitude of the output signal of the amplifier, and having a period and a phase equal to the first sawtooth wave; Associating each high time point portion of the second pulse with the second sawtooth wave and continuously extracting the output voltage using the second sawtooth wave position at the corresponding portion as a sample; Charging the extracted voltage to a capacitor by a high speed switch to maintain the extracted voltage, and removing the corrugation of the output waveform to facilitate filtering. Analog signal amplification method characterized in that it comprises. As an analog signal amplification method in an analog signal amplifier, Outputting a first sawtooth wave having a frequency sufficiently larger than the maximum frequency of the input signal of the amplifier, having an amplitude equal to or slightly larger than the maximum amplitude of the input signal, and having a predetermined period; Comparing the first sawtooth wave with the input signal and outputting a first pulse that makes the output high for a period in which the first sawtooth wave is larger than the input signal; Outputting a narrow one-shot second pulse at each start point of the high period of the first pulse; Outputting a second sawtooth wave having an amplitude equal to or slightly greater than the maximum amplitude of the output signal of the amplifier, and having a period and a phase equal to the first sawtooth wave; Associating each high time point portion of the second pulse with the second sawtooth wave and continuously extracting a first output voltage using a sample of the second sawtooth wave position at the corresponding portion; Outputting a third sawtooth wave which is an inverse phase of the second sawtooth wave; Associating each high viewpoint portion of the second pulse with the third sawtooth wave and continuously extracting a second output voltage using a sample of the third sawtooth voltage position at the corresponding portion; Charging each of the voltages extracted as the first output voltage and the second output voltage to a capacitor by a high-speed switch to maintain these extracted voltages, and removing the corrugations of the output waveform to facilitate filtering; Forming a double output signal using the two outputs in phase opposite to the first output and the second output; Analog signal amplification method characterized in that it comprises. The method according to claim 1 or 2, And adjusting the gain of the amplifier by adjusting the amplitude of the first sawtooth wave. The method according to claim 1 or 2, And modulating the amplitude of the first sawtooth wave by adjusting the amplitude of the first sawtooth wave through a second input signal separate from the input signal. An amplifying device integrated into a semiconductor using the method according to claim 1 or 2. An amplifier integrated into a semiconductor by using the method according to claim 3. An amplifier integrated into a semiconductor using the method according to claim 4. In the sawtooth oscillator circuit used in the analog signal amplifier circuit, A clock oscillator 7-A for generating a clock; The pulse generated from the clock oscillator 7-A is made into a positive pulse and a negative pulse, and the capacitor C3 discharge circuit Q1 of the output voltage level is driven with the constant pulse to reset the sawtooth wave every constant pulse to continuously output the pulse. A second sawtooth wave oscillator 7-B for obtaining a second sawtooth wave of a signal level and generating a first sawtooth wave of an input signal level using the second sawtooth wave; The output of the second sawtooth wave is reduced by the buffer circuit Q3, and at the same time, the capacitor C5 discharge circuit Q4 of the output voltage level is driven by the negative pulse generated by the clock oscillator to reset the sawtooth wave at every negative pulse. And a third sawtooth oscillator 7-C which obtains a continuous third sawtooth wave, A sawtooth wave oscillator circuit comprising: outputting the third sawtooth wave output by lowering the output impedance by a buffer circuit (Q6) to simultaneously generate two sawtooth waves of the same phase with the same period. 9. The method according to claim 8, characterized in that the first sawtooth wave of the input signal voltage level having the same phase and period is generated by attenuating the second sawtooth wave voltage of the output voltage level generated by the second sawtooth oscillator 7-B. Sawtooth oscillation circuit. The method of claim 8, A constant pulse circuit (IC2A) connected to the output of the clock oscillator (7-A) for outputting a constant pulse, and a negative pulse circuit (IC2B) connected to the constant pulse circuit for outputting a negative phase of an antiphase; , A capacitor C2 is coupled between the output of the constant pulse circuit IC2A and the capacitor discharge circuits Q1, D1, and R4 constituting the clamp circuit in the second sawtooth oscillator 7-B, and the negative pulse circuit. Between the output of the IC2B and the capacitor discharge circuits Q4, D2, and R10 constituting the clamp circuit in the third sawtooth oscillator 7-C with a capacitor C4, the second sawtooth oscillator 7- B) and sawtooth oscillator circuit, characterized in that it is easy to change the maximum output of the amplifier by changing the circuit power supply voltage (+ -V2) of the third sawtooth oscillator (7-C). A clock oscillation circuit 7-A for generating a clock; A second sawtooth oscillator 7 for generating a second sawtooth wave of an output signal level using the clock from the clock oscillator circuit 7-A and at the same time generating a first sawtooth wave of an input signal level using the second sawtooth wave; -B) A third sawtooth oscillator 7-C which generates a third sawtooth wave of an output level as an inverse phase with the second sawtooth wave from the second sawtooth oscillator 7-B; The first sawtooth wave from the second sawtooth oscillator (7-B) with an input terminal (IN) and the comparator (IC3), and the analog signal coming from the input terminal (IN) to the comparator (IC3) A comparator circuit 7-D for generating a first pulse when the first sawtooth wave signal is larger than the analog input signal, and generating an output HIGH; A one-shot vibrator 7-F for shaping the first pulse from the comparator circuit 7-D to generate a second pulse having a narrower width than the first pulse; A first output P-OUT as an analog output having the same phase as an input signal using a second pulse of the one-shot vibrator, a second sawtooth wave from the second sawtooth oscillator and a third sawtooth wave from the third sawtooth oscillator; And an analog switch circuit (7-E) for generating a second output (N-OUT) as an analog output out of phase with the input signal. The method of claim 11, The analog switch circuit 7-E comprises an analog switch 1 (A-SW1) for inputting a second sawtooth wave (PTH) signal having an output level in phase with the input signal; An analog switch 2 (A-SW2) for inputting a third sawtooth wave (NTH) signal having an output level that is in phase with the input signal; The capacitor C10 connected to the output terminal of the analog switch 1 (A-SWI) and the first sawing means (TC2, C8) connected to the third sawtooth wave (NTH) signal to divide the third sawtooth wave, First ripple canceling means for overlapping the divided signal in the condenser C10 to cancel the ripple; And a second voltage dividing means (TC1, C9) connected to an output terminal of the analog switch 2 (A-SW2) and the second sawtooth wave (NTH) to divide the second sawtooth wave. A second ripple canceling means for overlapping a signal divided by the voltage dividing means in the condenser C10 to cancel the ripple; An analog amplification circuit comprising: A power amplifier CBST1 connected to the first output of the analog amplifying circuit according to claim 11 via a low pass filter 1 LPF1, In this power amplifier CBST1, the output terminal OUT and the inverting input terminal (-) of the operational amplifier IC30 are connected through the resistor R31, and the inverting input terminal (-) and the operational amplifier IC30 of the operational amplifier IC30 are connected. A capacitor C31 is connected to a passage connecting the output terminal of the resistor. A resistor R30 is connected between the output terminal of the operational amplifier IC30 and the base of the first stage transistor Q30 of the power amplifier, and the time constant of the resistor R31 and the capacitor C31 is increased. Power amplifier device, characterized in that the power amplifier output stage (OUT) is always controlled to 0V potential by feeding back only DC The method of claim 11, When shaping the first pulse to the second pulse in the one-shot vibrator unit 7-F, the delay time between input and output of the one-shot vibrator 7-F (Tplh) at the point of switching from the highest point to the lowest point of the second sawtooth wave. When the first pulse near the maximum value of the input signal is inputted by applying the blanking pulse generated at the HIGH level to the reset terminal RESET of the one short vibrator IC4 by 2. The analog amplification circuit for preventing two pulses from being outputted to prevent the output voltage from being reversed abruptly. The method of claim 11, From the time when the first sawtooth wave of the input signal level and the first pulse which is the output of the comparator IC3 by the input signal from the input terminal IN generate | occur | produce, When a delay time between outputs occurs, the sawtooth drive pulse is delayed by the delay time, and the sawtooth wave of the output level is generated by the delayed drive pulse, and the output extracted from the analog switch circuit 7-E An analog signal amplifying circuit, characterized in that it is corrected so as to be the maximum output voltage without distortion. An amplifier that takes a PWM signal as an input, A rising section detector 9-B which detects a rising section of the PWM signal and generates a high pulse in the rising section; A falling section detector (9-C) that detects a falling section of the PWM signal and generates a high pulse in the falling section; A sawtooth oscillator 9-D which initializes with a high pulse from the rising section detector and generates a sawtooth wave of an output level; A one-shot vibrator 9-E for shaping the high pulse from the falling section detector into a narrow pulse; A continuous analog signal without valleys is turned on by shaping pulses of narrow width from the one-shot vibrator furnace 9-E and extracting the sawtooth voltage from the sawtooth oscillator 9-D to charge the capacitor. PWM signal input amplifier, characterized in that for generating. An amplifier which inputs this digital beam information from a device which digitally processes an analog signal such as a CD player and outputs digital information (PCM signal). A digital information control processor 13-B for inputting and analyzing the digital information including a right signal, a left signal, a control signal, and other information to output each analyzed signal as a control signal; A storage comparator 13-C for storing and comparing control signals from the digital information control processor 13-B and outputting high pulses corresponding to analog signal values; A one-shot vibrator section 13-E for shaping a narrow pulse at the start of the high pulse from the storage comparison section 13-C, A sawtooth generation and reset circuit section 13-D for performing a reset operation and a sawtooth generation by a high pulse output from the digital information control processing section 13-B by the data start control signal; Each capacitor C54 is controlled by the narrow narrow pulse from the one-shot vibrator portion 13-E, and the voltage corresponding to the sawtooth wave is extracted using the sawtooth wave from the sawtooth wave generation and reset circuit portion 13-D. And an analog switch (13-F) for charging and holding at C56 to generate continuous right and left analog signals without valleys. An amplifying element integrating the amplifier according to claim 16 in a semiconductor. An amplifying element integrating the amplifier according to claim 17 in a semiconductor.