KR100433934B1 - Apparatus for controlling low power lcd and method thereof - Google Patents

Abstract

An object of the present invention is to provide a low power LCD control apparatus and method which can reduce power consumption by controlling power consumption using an image signal rather than segmenting an image region.

The present invention to achieve the above object, the first signal generating means for outputting the pixel data and the control signal; DC / DC conversion means for performing DC / DC conversion and outputting a power signal; Receiving pixel data and control signals from the first signal generating means, receiving power signals from the DC / DC conversion means, generating image control signals according to individual characteristics of the pixel data, and generating image data signals and image control. Signal generating means for outputting a signal; Source driving means for receiving an image data signal and an image control signal from the signal generating means, converting the image data signal into an electrical image signal, and outputting the image signal in accordance with the image control signal; Gate driving means for receiving an image control signal from the signal generating means and outputting a control signal for designating a position to display the image signal output by the source driving means according to the image control signal; And an LCD panel displaying the image signal received from the source driving means at a position designated by the control signal of the gate driving means.

Description

Low power LCD control device and method {APPARATUS FOR CONTROLLING LOW POWER LCD AND METHOD THEREOF}

The present invention relates to a low power LCD control apparatus and method, and more particularly, to a low power LCD control apparatus and method for controlling power consumption by performing control by the characteristics of the image signal data represented on the screen using a frame memory.

In general, for low power consumption, a partial scan mode scheme in which a screen is divided and displayed according to expressed image characteristics is used. That is, as shown in FIG. 1, the full screen 110 appears in the normal mode, whereas only a partial region 120 of the screen appears in the standby mode. In this case, the control unit for controlling the LCD screen may control to display only a partial area of the screen, thereby reducing power consumption of the system.

An LCD control apparatus for reducing power consumption by using the partial scan mode in the above-described conventional technique will be described later with reference to FIG. 2.

The LCD control apparatus using the partial scan mode includes a CPU 210 for outputting pixel data and a control signal, a DC / DC conversion unit 220 for outputting a power signal, pixel data from the CPU 210, and a control signal. A control signal generator 230 for receiving an image control signal and an image data signal RGB, and mounted in the control signal generator 230 to receive and write pixel data and control signals from the CPU 210. A control signal generation circuit unit 231 for outputting a control signal, an image unit pixel signal, and a control signal; and a write control signal and an image unit pixel signal from the control signal generation circuit unit 231 mounted in the control signal generator 230. A frame memory unit 232 for receiving input image data and storing the image data in pixel units, and a control signal from the control signal generation circuit unit 231 and a frame memory unit 232. A source driver 240 for receiving an image data signal and outputting an image signal, and a gate driver 250 for receiving a control signal from the control signal generation circuit unit 231 and outputting a control signal specifying a position at which the image signal is to be displayed. ) And an LCD panel 260 that receives an image signal from the source driver 240 and a control signal from the gate driver 250 to display an image. According to such a circuit device, in order to display a screen, all gate drivers in the gate driver 250 must be sequentially designated, and one screen is refreshed at the frame rate of the system. When the refresh or non-selected areas are collectively refreshed, the gate driver driving power and the driving power of the source driver in the source driver 240 may be reduced according to the reduced number of driving of each driver.

In the case of applying the partial scan mode by the screen division used in the conventional LCD control apparatus as described above, an area without an image signal exists even though the area is selected as shown in FIG. In the partial scan mode, there is a problem in that the CPU 210 needs to perform sophisticated partial scan control for screen control.

An object of the present invention is to provide a low power LCD control apparatus and method that can reduce power consumption by controlling power consumption using an image signal rather than segmenting an image region.

1 is an exemplary view showing a display of an LCD panel according to a conventional partial scan method,

2 is a block diagram of a low power LCD control device according to the prior art;

3 is a block diagram showing a low power LCD control device according to an embodiment of the present invention;

4 is a block diagram showing a low power LCD control device according to another embodiment of the present invention;

FIG. 5 is a circuit diagram showing line buffering means mounted in a low power LCD control device according to an embodiment of the present invention according to FIG. 3;

FIG. 6 is a circuit diagram illustrating a buffering unit structure mounted in a low power LCD control device according to an embodiment of the present invention according to FIG. 5.

7 is an operation flowchart showing a low power LC control method according to an embodiment of the present invention;

8 is an operation timing diagram according to a low power LC control method according to an embodiment of the present invention;

9 is an operation timing diagram according to a low power LCD control method according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

110: screen in normal mode

120: Screen in standby mode

210: CPU

220: DC / DC conversion means

230: control signal generator

231: control signal generation circuit

232: frame memory section

240 source driving unit

250: gate driver

260 LCD panel

310: first signal generating means

320: DC / DC conversion means

330: signal generating means

331: second signal generating means

332: frame storage means

333: line buffering means

340: source driving means

350: gate driving means

360: LCD Panel

433: shift register

In order to achieve the above object, the low power LCC apparatus of the present invention includes: first signal generating means for outputting pixel data and a control signal; DC / DC conversion means for performing DC / DC conversion and outputting a power signal; Receiving pixel data and control signals from the first signal generating means, receiving power signals from the DC / DC conversion means, generating image control signals according to individual characteristics of the pixel data, and generating image data signals and image control. Signal generating means for outputting a signal; Source driving means for receiving an image data signal and an image control signal from the signal generating means, converting the image data signal into an electrical image signal, and outputting the image signal in accordance with the image control signal; Gate driving means for receiving an image control signal from the signal generating means and outputting a control signal for designating a position to display the image signal output by the source driving means according to the image control signal; And an LCD panel displaying the image signal received from the source driving means at a position designated by the control signal of the gate driving means.

In addition, in order to achieve the above object, the low power LCC method of the present invention comprises the steps of: an external control signal to a first logic state; Starting a line read; The first node is precharged for image signal evaluation; Bringing the external control signal into a second logic state; Terminating a parallel copy of the data and performing image signal evaluation; Checking through the state of the first node whether each pixel satisfies a predetermined condition; If each pixel satisfies a predetermined condition, enabling an image threshold signal; And receiving the enabled image threshold signal, performing a line related signal control, and returning to an external control signal becoming a first logic state.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

First, FIG. 3 is a block diagram showing a low power LCC apparatus according to an embodiment of the present invention. The low power LCC apparatus of the present invention may include a first signal generating unit 310, a DC / DC converting unit 320, and a signal. And a generator 330, a source driver 340, a gate driver 350, and an LCD panel 360.

The first signal generating unit 310 serves to generate a control signal by determining a scan mode based on the image signal according to the pixel data, and output the pixel data and the control signal to the signal generating unit 330 which will be described later. do.

In addition, the DC / DC conversion unit 320 performs a DC / DC conversion, and serves to output the power signal according to the signal generating means 330 to be described later.

On the other hand, the signal generating means 330 receives the pixel data from the first signal generating means 310, the control signal and the power signal from the DC / DC conversion means 320, using a frame image signal Generating an image threshold signal for switching a system mode from a general partial scan mode to a control mode based on an image signal, generating an image control signal for selecting and controlling a mode according to the image threshold signal, and generating the image control signal. It outputs to the source driving means 340 to be described later and the gate driving means 350 to be described later, and outputs the image data signal RGB for displaying an image to the source driving means 340 to be described later. The signal generating means 330 includes a second signal generating means 331, a frame storing means 332, and a line buffering means 333.

The second signal generating means 331 mounted in the signal generating means 330 receives the pixel data and the control signal from the first signal generating means 310 and receives power from the DC / DC conversion means 320. Receives a signal, and outputs the write control signal and the image unit pixel signal signal generated through the pixel data to the frame storage means 332 to be described later, and receives the image threshold signal from the line buffering means 333 to be described later It generates an image control signal by using, and outputs the image control signal to the source driving means 340 to be described later and the gate driving means 350 to be described later.

In addition, the frame storage means 332 mounted in the signal generating means 330 receives a write control signal and an image unit pixel signal signal from the second signal generating means 331, and stores the image in pixel units. It outputs the stored video signal to the line buffering means 333 which will be described later.

On the other hand, the line buffering means 333 mounted in the signal generating means 330 receives an image signal from the frame storage means 332, generates an image threshold signal using the image signal, and generates the image threshold signal. It outputs to the second signal generating means 331, and outputs the buffered image data signal RGB to the source driving means 340 which will be described later. Here, the line buffering means 333 receives a video signal from the frame storage means 332 in parallel by a data width corresponding to the number of source drivers mounted in the source driving means 340 to be described later. However, as shown in FIG. 4, image signals are sequentially received from the frame storage means 332 to generate image threshold signals, and the image threshold signals are generated by the second signal generation means ( The line buffering means 333 is functionally identical to the shift register 433 which is output to 331 and outputs the buffered image data signal RGB to the source driving means 340 which will be described later.

In addition, the source driving means 340 receives an image control signal from the second signal generating means 331, receives an image data signal from the line buffering means 333, and converts the image data signal into an electrical signal. And converts the image signal into a video signal, and outputs the video signal to the LCD panel 360 to be described later in the form of a horizontal signal.

On the other hand, the gate driving means 350 receives an image control signal from the second signal generating means 331, and a control signal for designating a position at which the image signal output by the source driving means 340 is displayed will be described later. It serves to output to the LCD panel 360.

In addition, the LCD panel 360 serves to display the image signal from the source driving means 340 at a position designated by the control signal from the gate driving means 350.

FIG. 5 is a circuit diagram showing a line buffering means mounted in a low power LCD control apparatus according to an embodiment of the present invention, wherein the line buffering means 333 includes a buffering means 510 and an image threshold signal generating means 520. do.

The buffering means 510 receives the pixel data composed of 8 bits from the frame storage means 332, and uses the pixel data and the control signals CMD, C0 to C7 from an external device (not shown). It outputs an evaluation signal of the image data for generating the threshold signal to the image threshold signal generating means 520 which will be described later. Here, the buffering means 510 includes a plurality of buffering unit structures 511 as shown in FIG. 6.

The buffering unit structure 511 includes eight registers 511a to 511h that receive 8-bit pixels one bit at a time, and output the eight-bit pixels to the wired OR logic device described later according to the control signal CMD, and the control signals C0 to. If any one of signals C7 is high, the wired OR logic device 511i implemented as a MOS transistor outputting a low signal to a first node Node 1 to be described later is included.

The image threshold signal generating means 520 enables the image threshold signal according to a control signal CMD of an external device (not shown) and a signal obtained by evaluating a video signal output from the buffering means 510. It serves to output a signal or a disable signal to the second signal generating means 331. The image threshold signal generating means 520 may include a first PMOS transistor MP1, a first NMOS transistor MN1, a first inverter INV1, a second inverter INV2, and a second PMOS transistor MP2. It includes.

The first PMOS transistor MP1 has a source terminal grounded to a power source and a drain terminal connected to a first node Node 1 that receives a signal for evaluating the image signal. The control terminal CMD is a gate terminal. Get input.

In addition, a first NMOS transistor MN1 has a drain terminal connected to the first node Node 1, and receives a control signal CMD through a gate terminal, and a source terminal of the first NMOS transistor MN1 described later. It is connected to the output terminal of.

Meanwhile, in the first inverter INV1, an output terminal is connected to a source terminal of the first NMOS transistor MN1, and an input terminal is connected to a drain terminal of a second PMOS transistor MP2 described later.

In addition, the second inverter INV2 forms a latch circuit in such a manner that an input terminal is connected to the output terminal of the first inverter and fed back, and the output terminal is connected to a source terminal of a second PMOS transistor MP2 described later. It is.

Meanwhile, the second PMOS transistor MP2 receives the control signal CMD through a gate terminal, a drain terminal is connected to an input terminal of the first inverter INV1, and a source terminal is connected to the second inverter INV2. Connected to the output terminal.

7 is an operation flowchart showing a low power LC control method according to an embodiment of the present invention, Figure 8 is a timing diagram according to a low power LC control method according to an embodiment of the present invention, according to the low power LC control of the present invention Explain how.

First, when the control signal CMD goes to a low state-a first logic state (S1), the line buffering means 333 starts reading a line from the frame storage means 332 (S2).

At this time, the first node Node 1 is precharged for image signal evaluation (S3). Here, the first PMOS transistor MP1 and the second PMOS transistor MP2 shown in FIG. 5 are turned on, and the previous signals are maintained in the two inverters INV1 and INV2 together with the precharge.

After that, the line reading is finished, so that the control signal CMD goes to a high state-a second logic state (S4).

Next, the parallel copy of data is ended by the buffering means 510, and image signal evaluation is performed (S5). At this time, in performing the video signal evaluation, the video signal may be controlled in units of bits by the plurality of control signals C0 to C7. For example, since the C0 signal controls the video signal evaluation for the first bit and the C7 signal controls the video signal evaluation for the last bit, the threshold value that can be ignored when performing the video signal evaluation by the control signals C0 to C7. Control the threshold value at which the image threshold signal can be disabled. Using the wired OR logic shown in FIG. 6, when any one of the plurality of control signals C0 to C7 is high, the signal output to the first node Node 1 is low. Thus, the first node Node 1 is discharged.

Thereafter, it is checked whether each pixel in the buffering means 510 satisfies a predetermined condition through the state of the first node Node 1 (S6). At this time, in order to improve characteristics of the signal transmitted by the first NMOS transistor MN1, the feedback path formed of the two inverters INV1 and INV2 is blocked.

If each pixel exceeds the negligible threshold value when performing the image signal evaluation, the image threshold signal is enabled (S7), and the second signal generating unit 331 receives the enabled image threshold signal and corresponds to the corresponding threshold value. After performing line-related signal control (S8), the first step (S1) is performed again.

Meanwhile, when each pixel does not satisfy a predetermined condition, the image threshold signal is disabled (S9), and the second signal generating unit 331 receives the disabled image threshold signal to perform a general partial scan mode. After that (S10), the first step (S1) is performed again.

FIG. 9 is an operation timing diagram according to a low power LC control method according to another embodiment of the present invention according to FIG. 4. In this case, since a sequential method is used for reading a memory, a clock according to a shift is required. Done. Since the rest is the same as that shown in FIG. 7, the description is omitted.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to the drawings shown.

The present invention has the advantage of effectively reducing power consumption without adding complicated devices by controlling power consumption using a video signal rather than video region division through line buffers and shift registers.

Claims (8)

First signal generating means for outputting pixel data and a control signal; DC / DC conversion means for performing DC / DC conversion and outputting a power signal; Receiving pixel data and control signals from the first signal generating means, receiving power signals from the DC / DC conversion means, generating image control signals according to individual characteristics of the pixel data, and generating image data signals and image control. Signal generating means for outputting a signal; Source driving means for receiving an image data signal and an image control signal from the signal generating means, converting the image data signal into an electrical image signal, and outputting the image signal in accordance with the image control signal; Gate driving means for receiving an image control signal from the signal generating means and outputting a control signal for designating a position to display the image signal output by the source driving means according to the image control signal; And LCD panel for displaying the image signal received from the source driving means at a position designated by the control signal of the gate driving means Low power LCD control device comprising a. The method of claim 1, wherein the signal generating means, Receiving pixel data and a control signal from the first signal generating means, receiving a power signal from the DC / DC conversion means, and receiving a write control signal and an image unit pixel signal signal generated through the pixel data and the control signal; Second signal generating means for outputting, receiving an image threshold signal, generating an image control signal using the image threshold signal, and outputting the image control signal; Frame storage means for receiving a write control signal and an image unit pixel signal signal from the second signal generation means and storing an image in pixel units and outputting the stored image signal; And Line buffering means for receiving an image signal in parallel from the frame storage means to generate an image threshold signal, outputting the image threshold signal to the second signal generating means, and outputting an image data signal to the source driving means; Low power LCD control device comprising a. The method of claim 1, wherein the signal generating means, Receiving pixel data and a control signal from the first signal generating means, receiving a power signal from the DC / DC conversion means, and receiving a write control signal and an image unit pixel signal signal generated through the pixel data and the control signal; Second signal generating means for outputting, receiving an image threshold signal, generating an image control signal using the image threshold signal, and outputting the image control signal; Frame storage means for receiving a write control signal and an image unit pixel signal signal from the second signal generation means and storing an image in pixel units and outputting the stored image signal; And Shift registers for receiving image signals sequentially from the frame storage means to generate image threshold signals, output the image threshold signals to the second signal generation means, and output image data signals to the source driving means. Low power LCD control device comprising a. The method of claim 2, wherein the line buffering means, Buffering means for receiving pixel data from the frame storage means, generating a signal evaluating an image signal using the pixel data, and outputting a signal evaluating the image signal; And Image threshold signal generating means for generating an image threshold signal by receiving a signal obtained by evaluating the video signal and outputting the image threshold signal Low power LCD control device comprising a. The method of claim 4, wherein the buffering means, A plurality of registers for receiving pixel data from the frame storage means and outputting the pixel data under external control; And Wired OR logic for performing a wired OR operation with an output signal from the register and an external control signal A plurality of buffering unit structure including Low power LCD control device comprising a. The method of claim 4, wherein the image threshold signal generating means, A first PMOS transistor having a source terminal grounded to a power source and a drain terminal connected to a first node receiving a signal evaluating the image signal, and receiving an external control signal through a gate terminal; A first NMOS transistor having a drain terminal connected to the first node and receiving the external control signal through a gate terminal; A first inverter having an output terminal connected to a source terminal of the first NMOS transistor; A second inverter configured to form a latch circuit in such a manner that an input terminal is connected to the output terminal of the first inverter and fed back; And A second PMOS transistor connected to an external control signal through a gate terminal, a drain terminal connected to an input terminal of the first inverter, and a source terminal connected to an output terminal of the second inverter Low power LCD control device comprising a. Bringing the external control signal into a first logic state; Starting a line read; The first node is precharged for image signal evaluation; Bringing the external control signal into a second logic state; Terminating a parallel copy of the data and performing image signal evaluation; Checking through the state of the first node whether each pixel satisfies a predetermined condition; If each pixel satisfies a predetermined condition, enabling an image threshold signal; And Receiving the enabled image threshold signal, performing a line-related signal control and returning to an external control signal becoming a first logic state Low power LC control method comprising a. The method of claim 7, wherein If each pixel does not meet a predetermined condition, the image threshold signal is disabled; And Receiving the disabled image threshold signal, performing a general partial scan mode, and returning to an external control signal becoming a first logic state; Low power LC control method comprising a.