KR100433298B1 - Fabricating method of spot-size converter semiconductor optical amplifier - Google Patents

Abstract

The present invention describes a spot-size converter integrated semiconductor optical amplifier (SSC SOA) and a method of manufacturing the same, which are spotlighted as a core element of next-generation optical communication. In the method of manufacturing a semiconductor optical amplifier incorporating a spot size converter according to the present invention, (a) the thickness of the spot size conversion region at both edges is thinner as the cleaved surface is closer to the cleaved surface than the gain region at the center by using the selection region growth method on the semiconductor substrate. Growing the optical waveguide structure on the losing stripe to a predetermined width, but inclining at an angle with a vertical direction of the cleaved surface; (B) In the stripe optical waveguide structure grown in the step (a), the gain area is etched to the edge portion roughly grown on both sides in the width direction, and the spot size conversion area is etched to be narrower as it is closer to the cleavage surface. To form an optical waveguide on a stripe of a predetermined width; And (c) growing a current limiting layer on both sides of the optical waveguide on the stripe, depositing a window material between the cleaved surface and the end of the optical waveguide to form a window structure, and then forming the window structure on the optical waveguide and the current limiting layer. Forming an upper structure of the optical amplifier.

Description

Fabrication method of spot-size converter semiconductor optical amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spot-size converter integrated semiconductor optical amplifier (SSC SOA) and a method of manufacturing the same, which are spotlighted as core elements of next-generation optical communication.

A semiconductor optical amplifier (SOA) is an optical signal transmission amplifier that uses an optical amplification function due to gain characteristics of a semiconductor by forming a semiconductor medium in the form of a waveguide. That is, when the input light passes through the SOA, the output light is operated by a mechanism that is amplified by the gain of the medium, and the basic device structure is very similar to that of the semiconductor laser device. This SOA replaces traditional EDB (erbium doped fiber amplifiers), as well as optical signal processing and optical functions such as switching, modulation, demodulation, routing, and conversion. It can be used for control, and can be widely applied to functional devices such as wavelength converters and optical switching devices for WDM.

1A and 1B are views showing an active layer structure of a conventional semiconductor optical amplifier, respectively, FIG. 1A is a schematic plan view showing a planar structure of an active layer, and FIG. 1B is a cutaway view of the active layer cut along the line AA ′ of FIG. 1A. A cross section showing the cross-sectional structure. In the device having the active layer structure as shown in the drawing, when both cleaved surfaces have a constant reflectance, light feedback occurs, thereby deteriorating characteristics of the device. Therefore, in order to prevent this, unlike the semiconductor laser, the antireflection (AR) coating is applied to both ends of the cleaved surface to become the traveling wave SOA. However, even with this anti-reflective coating it is not possible to completely prevent reflection, so there is always a possibility of rasing. In order to scatter the reflected light so as not to return to the active layer, the reflective layer may be inclined at a predetermined angle to lower the reflectance or to lower the reflectivity by making the window area W near the cleaved surface.

In addition, in order for amplification to occur regardless of the polarization state of the input light, the gains of the TE polarization and the TM polarization must be equalized. The main attempts are to make the active layer a thick bulk material or to apply the strained multiple quantum wells to the active layer to achieve the same polarization gain.

When the active layer is made of a thick bulk material, polarization independence can be secured by making the ratio of the cross section of the gain region almost equal to the ratio of optical confinement in the TE and TM directions. On the other hand, the process is complicated and difficult because the formation of a sub-micron pattern is essential.

Therefore, when a small amount of tensile strain is applied to the bulk active layer, the TM gain is improved, and polarization-independent characteristics can be easily obtained even when the width of the gain region is maintained at about 1 μm.

In fact, after fabrication of the device is completed, the optical fiber (fiber) is coupled to both ends of the device is manufactured in the form of a module. In this case, a complex optical system must be used in order to obtain high coupling efficiency, which increases the cost and complexity of the process. In order to overcome this disadvantage, as shown in FIG. 2A, a tapered region SSC is usually formed in a predetermined region of the device, so that the wave-field angle (SSC) can be reduced by spot size conversion (SSC). It reduces the far-field angle and enables high efficiency fiber coupling without the need for additional optics. As an additional effect, the SSC increases the effect of lowering the reflectance by the inclined waveguide.

In this way, the combination of AR coating, window region, SSC, and four methods of giving oblique stripes can reduce the reflectance by as much as 5x10 ^-5 %.

SSCs utilize a Selective Area Growth (SAG) technique of Metal-Organic Vapor Phase Epitaxy (MOVPE), as shown in FIGS. 1A and 1B, for vertical tapering. The tapering method and two methods of forming by etching by giving lateral tapering as shown in FIGS. 2A and 2B are widely used.

In general, non-selective wet etching of Br-based or non-selective dry etching of CH ₄ / H ₂ and non-selective wet etching of non-selective wet etching in forming a stripe pattern Etching is performed by combining).

In addition, NSC's SSC-SOA uses a straight waveguide having a width of about 0.5 μm as shown in Figs. 3A and 3B. There is no separate horizontal tapering and there is a limit in lowering the reflectance, so the characteristics of the device are relatively inferior. In addition, such a straight waveguide forms a vertical taper by the SAG method of MOVPE. In this case, epitaxial growth is performed using the SAG mask 100 having a narrow interval of about 1 μm as shown in FIG. 4, and used as a waveguide as it is. In this method, the larger the width of the central mask, the greater the migration of grains during epitaxy growth, and the smaller the width of the masks at the edges. The fabrication of a device having a tapered structure is simplified, but due to the characteristics of selective growth, when the waveguide on the stripe is inclined or lateral taper as shown in FIG. The interface between the crystals is very rough, the waveguide characteristics are very bad and the loss is severe.

The present invention has been devised to improve the above problems, and forms a window area between the waveguide and the cleavage surface, and at the same time, inclines the waveguide on the stripe to scatter the light reflected from the cleavage surface so as not to return to the waveguide, and at the both edges of the waveguide. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor optical amplifier incorporating a spot size converter formed to have vertical and horizontal tapered structures at a portion thereof, and a fabrication method thereof.

1A and 1B are diagrams illustrating a waveguide structure of a conventional semiconductor optical amplifier, respectively.

1A is a schematic plan view showing a planar structure of a waveguide;

1B is a cross-sectional view illustrating a cross-sectional structure of a waveguide cut along the line AA ′ of FIG. 1A;

2A and 2B illustrate a waveguide structure of another conventional semiconductor optical amplifier, respectively.

2a is a schematic plan view showing a planar structure of a waveguide;

FIG. 2B is a cross-sectional view illustrating a cross-sectional structure of the waveguide cut along the line BB ′ of FIG. 2A;

3A and 3B show a waveguide structure of another conventional semiconductor optical amplifier (NEC), respectively.

3A is a schematic plan view showing a planar structure of a waveguide;

3B is a cross-sectional view illustrating a cross-sectional structure of a waveguide cut along the line CC ′ of FIG. 3A;

4 is a plan view illustrating a mask pattern for forming the waveguide shown in FIGS. 3A and 3B;

5A and 5B show the waveguide structure of the semiconductor optical amplifier according to the present invention, respectively.

5a is a schematic plan view showing a planar structure of a waveguide;

5B is a cross-sectional view illustrating a cross-sectional structure of the waveguide cut along the line BB ′ of FIG. 5A;

6 is a partially cutaway perspective view of the semiconductor optical amplifier shown in FIGS. 5A and 5B;

7A and 7B are cross-sectional views illustrating in detail the waveguide structure of the semiconductor optical amplifier of FIG. 6.

7A is a sectional view of a gain region of a waveguide;

7B is a cross-sectional view of the spot size conversion region of the waveguide;

8A to 13 are views illustrating a step-by-step process of fabricating a semiconductor optical amplifier incorporating a spot size converter according to the present invention, respectively.

8A and 8B are a plan view and a cross-sectional view showing the shape of a mask pattern for growing a selected region, respectively;

9A and 9B are plan views showing the structure of the epitaxy layer grown on the selected region, respectively, and FIG. 9B is a cross-sectional view showing a section cut along the line BB ′ of FIG. 9A;

10A and 10B are a cross-sectional view and a plan view showing a shape of a mask pattern for mesa etching formed on a selected region growth, respectively;

11 is a cross-sectional view showing the epitaxy layer etched in a mesa shape,

12 is a cross-sectional view showing a growth of a current blocking layer in an etched region;

FIG. 13 is a cross-sectional view illustrating a regrown cladding layer and a contact layer formed on a current blocking layer and an optical waveguide; FIG.

FIG. 14 is the horizontal and vertical far-field patterns of the SSC-SOA of FIG. 6 at 150 mA,

15 is a gain characteristic curve of the SSC-SOA of FIG. 6 at current at Pin = -20 dBm and at l = 1.55 mm,

16 is a Polarization resolved ASE spectra of SSC-SOA of FIG. 6 at 60, 100, and 200 mA.

<Description of Symbols for Main Parts of Drawings>

10.n-InP substrate 11.n-InP bottom cladding layer

12. InGaAsP bottom waveguide layer 13. InGaAsP active layer

14. InGaAsP top waveguide 15.p-InP first top clad layer

16. p-InGaAs (P) etch stop layer 17. p-InP second upper clad layer

18. p ⁺ -InGaAs contact layer 20. Mask for selective growth

21. Mask for mesa etching 30. Current limiting layer

In order to achieve the above object, in the semiconductor optical amplifier in which the spot size converter according to the present invention is integrated, an optical waveguide in which a lower clad layer, an active layer and an upper clad layer are sequentially stacked is formed on a semiconductor substrate. A window region is formed between both ends of the optical waveguide and the cleaved surface, and the cleaved surface is a semiconductor optical amplifier in which an anti-reflective coated spot size converter is integrated, wherein the optical waveguide is stacked in a mesa shape and formed into a stripe shape. The optical waveguide on the stripe is formed to be inclined at a predetermined angle with the vertical direction of the cleaved surface, and the center of the optical waveguide on the stripe is a selected region grown to be a gain region, and both edge portions are vertically and horizontally closer to the cleaved surface. Characterized in that it is formed of a spot size conversion area that becomes narrower. The.

In the present invention, the optical waveguide is formed by sequentially stacking an n-InP lower cladding layer, an InGaAsP lower waveguide layer, an InGaAsP active layer, an InGaAsP upper waveguide layer, and a p-InP upper cladding layer on an InP substrate. The lower cladding layer is 1 μm, the lower optical waveguide layer is 0.1 μm, the active layer is 0.2 μm to 0.25 μm, the upper optical waveguide layer is 0.1 μm, and the upper clad layer is formed to a thickness of 0.4 μm. Is formed in a width of about 15 ~ 25㎛, the optical waveguide on the stripe is formed to form a 7 to 10 ° in the direction perpendicular to the cleaved surface, the cleaved surface is preferably formed of SiO ₂ / TiO ₂ antireflective coating film. .

In addition, in order to achieve the above object, according to the present invention, a method for fabricating a semiconductor optical amplifier in which a spot size converter is integrated is provided. Growing the optical waveguide structure on the stripe which becomes thinner as the spot size conversion region becomes closer to the cleaved surface with a predetermined width, but inclined by a predetermined angle with respect to the vertical direction of the cleaved surface; (B) In the stripe optical waveguide structure grown in the step (a), the gain area is etched to the edge portion roughly grown on both sides in the width direction, and the spot size conversion area is etched to be narrower as it is closer to the cleavage surface. To form an optical waveguide on a stripe of a predetermined width; And (c) growing a current limiting layer on both sides of the optical waveguide on the stripe, depositing a window material between the cleaved surface and the end of the optical waveguide to form a window structure, and then forming the window structure on the optical waveguide and the current limiting layer. Forming an upper structure of the optical amplifier in the;

In the present invention, the n-InP substrate is used as the semiconductor substrate, and the step (a) includes (a-1) forming a dielectric film on the n-InP substrate; (A-2) sub-steps of patterning the dielectric film to form a mask for selective growth; And (A-3) a waveguide structure including a lower cladding layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper cladding layer, and an etch stop layer in the SAG method of a conventional MOVPE using the selective growth mask. A sub-step of growing; and in the sub-step (a-1), the dielectric film is formed by depositing SiO ₂ or Si ₃ N ₄ using PECVD or sputtering, and the (ga-2) sub-step. In the step, the dielectric film is patterned by photolithography, but the open area between the masks is formed to be about 15 μm and inclined at about 7 ° to 10 ° with respect to the vertical direction of the cleaved surface. In the step, the width of the selective growth mask is 150 µm as a value for determining the difference in growth rate and composition between the open area and the outer area of the mask between the masks, so that a thickness ratio of about 3: 1 can be obtained. In the step (ga-3), the lower cladding layer grows n-InP to 1 µm thick, the lower waveguide layer grows InGaAsP to 0.1 µm thick, and the active layer grows InGaAsP 0.2 µm to 0.25 Grow to a thickness of μm, the upper waveguide layer to grow InGaAsP to a thickness of 0.1 μm, the top clad layer to grow p-InP to 0.4 μm, and the etch stop layer to grow p-InGaAs (P) 0.05 It is preferable to grow to a thickness of 탆.

In addition, in the present invention, the step (B) may include (B-1) a sub-step of removing the etch stop layer after removing the mask for selective growth using the etch stop layer; (B-2) depositing a dielectric film; (B-3) a sub-step of patterning the dielectric film by a conventional lithography process to form a mesa etching mask by aligning the center film in parallel with the center of the selective growth region; And (b-4) forming an optical waveguide on the buried stripe having an almost vertical inclination by etching the waveguide structure on the stripe using the mesa etching mask. In the step, the dielectric film is formed by depositing SiO ₂ or Si ₃ N ₄ using plasma enhanced chemical vapor deposition or sputtering. In the sub-step (B-3), the mesa etching mask is formed by the optical waveguide. The shape and width of the gain grown waveguide structure are adjusted so that the width of the gain region is formed to be about 1 μm and the end of the optical waveguide is formed to be 0.2 μm or less, and in step (b-4), The optical waveguide on the buried stripe forms an inclination of about 7-10 ° with the vertical plane of the cleaved surface, and the width of the gain region is adjusted to about 1 μm and the end of the waveguide is 0.2 μm or less. It is preferable to use a conventional wet etching method or a reactive ion etching method of CH ₄ / H ₂ system so as to form a furnace.

Further, in the present invention, the step (c) comprises (c-1) regrowth on the substrate on the side of the optical waveguide on the stripe to form a current limiting layer between the end of the optical waveguide and the cleaved surface. Forming a window area; (C-2) removing the mesa etching mask; (C-3) a sub-step of regrowing the upper clad layer and the contact layer on the current limiting layer and the optical waveguide; wherein, in the (C-1) sub-step, the window area has a width of 15 to 25 μm. In the step (c-3), the current limiting layer is formed using p-InP / n-InP or semi-insulating InP, and the upper cladding layer is deposited with p-InP having a thickness of 2 μm. The contact layer is formed by depositing p ⁺ -InGaAs to a thickness of 0.1㎛, (C) after the step of performing a non-reflective coating with SiO ₂ / TiO ₂ on both sides of the cleaved (facet) to lower the reflectance; It is preferable to further include.

Hereinafter, a semiconductor optical amplifier incorporating a spot size converter and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

5A and 5B are a plan view and a vertical sectional view schematically showing the optical waveguide structure of the semiconductor optical amplifier in which the spot size converter is integrated according to the present invention, respectively. As shown, in the semiconductor optical amplifier in which the spot size converter is integrated according to the present invention, the active layer on the stripe forming the optical waveguide is formed to be inclined at about 7 ° to 10 ° with respect to the vertical direction of the cleaved surface as shown in FIG. 5A. It is characterized by having a tapered structure in which both edges thereof are horizontally narrowed, and also having a tapered structure in which both edges are narrowed vertically as shown in FIG. 5B. This tapered structure is shown in the partial cutaway perspective view of FIG. 6. As shown in FIG. 6, an embodiment of the semiconductor optical amplifier in which the spot size converter is integrated according to the present invention has a distance between the cleaved surface and the cleaved surface of about 1500 μm, and the width of the window area is about 20 μm. The length of the active layer 10 is about 1460 μm. About 430 micrometers of both edges except about 600 micrometers of the center of this 1460 micrometer active layer are formed in the taper structure narrowing in a horizontal and a vertical direction to a spot size conversion area | region. Both cleaved surfaces are formed of an SiO ₂ / TiO ₂ antireflective coating film. FIG. 7A is a cross-sectional view of the gain region in FIG. 6, and FIG. 7B is a cross-sectional view of the spot size conversion (SSC) region in FIG. 6. It can be seen that the cross section of the active layer is narrower in FIG. 7B than in FIG. 7A.

A semiconductor optical amplifier incorporating a spot size converter having such a structure is manufactured by using an angled selective area growth method.

First, as described above, the selective area growth (SAG) epitaxy growth of MOVPE is performed by using a SAG mask (see FIG. 4) having a narrow interval of about 1 μm, such as a semiconductor optical amplifier in which NEC's spot size converter is integrated. By forming a selective epitaxy growth layer having a vertical taper and then using it as a waveguide as described above, fabrication of the device is simplified. However, if the SAG mask is inclined in the vertical direction of the cleaved surface and the selective growth is performed using this method, the side of the epitaxial growth layer on the stripe does not coincide with the crystal direction and the growth rate is different so that the interface between the mask and the crystal is different. It is not possible to use it as it is so rough that the characteristics of the waveguide are very bad and the loss is severe. Therefore, in the exemplary embodiment of the present invention, the stripe SAG growth layer is grown at an angle with respect to the vertical direction of the cleaved surface, but the width thereof is increased to about 15 μm and the roughly grown edge portion is etched. In this way, since the side surface of the waveguide structure on the stripe is formed cleanly, it is possible to significantly improve the characteristics of the device by reducing the FFP angle and lowering the reflectance than the conventional method. The manufacturing process is described in detail as follows.

First, as shown in FIGS. 8A and 8B, a dielectric film, such as SiO ₂ or Si ₃ N ₄ , is deposited on the n-InP substrate 10 using conventional PECVD or sputtering. Lithography and etching form a mask 20 for selective growth. At this time, the opening area between the masks 20 should be about 15 占 퐉 so that the mask for forming stripe (see Fig. 10) can be easily mounted later, and the crystal direction (vertical direction of the cleavage surface) Tilt at about 7 ° to 10 °. The width of the mask 20 is an important value that determines the difference in growth rate and composition between the mask inside and the outside area of the mask. When the thickness is 150 μm, a thickness ratio of about 3: 1 is obtained. 1.3Q of material is grown, allowing the outside of the mask to act as a passive waveguide.

Next, as shown in FIG. 9A, a waveguide structure including a lower cladding layer, an active layer, and an upper cladding layer is grown in a SAG manner of a conventional MOVPE using a mask 20. In this way, although there are differences depending on the MOVPE growth conditions, it is possible to easily obtain a uniform region of about 5 to 10 μm in a conventional manner. In SAG, as shown in FIG. 9B, a 1 μm n-InP lower clad layer 11, a 0.1 μm 1.3Q InGaAsP waveguide layer 12, 0.2 μm to 0.25 μm 1.55Q -slightly tensile strained A bulk InGaAsP active layer 13, a 0.1 μm 1.3Q InGaAsP waveguide layer 14, a 0.4 μm p-InP top clad layer 15, and a 0.05 μm p-InGaAs (P) etch stop layer 16 are sequentially stacked. .

Next, the selective growth dielectric mask 20 is removed using the etch stop layer 16, the etch stop layer 16 is removed, and the above-described dielectric film is again deposited as shown in FIG. 10A. . In addition, a mesa etching mask 21 is formed by aligning in the center of the center in parallel with the selective growth region using a conventional lithography process. At this time, the shape of the waveguide, as shown in Figure 10b, gives an inclination of about 7 ~ 10 ° and a horizontal taper (lateral taper) in the predetermined area where the vertical taper (vertical taper) is formed to further strengthen the SSC At the end of the waveguide, a window area of about 15 to 25 μm is formed to lower the reflectance even further.

Using the mask 21 thus formed, as shown in FIG. 11, etching is performed in the form of a buried stripe through conventional wet etching or a reactive ion etching (RIE) process based on CH ₄ / H ₂ . To form a waveguide in such a way that it has a nearly vertical slope. At this time, as shown in FIG. 6, the width of the gain region is adjusted to about 1 μm and the end of the waveguide is 0.2 μm or less to enable single mode operation.

Next, through selective area regrowth, as shown in FIG. 12, the current limiting region 30 and the window region are formed, and then the mask 21 is removed, As shown in Fig. 13, regrowth is performed again to complete the device. At this time, either the p-InP / n-InP or semi-insulating InP may be used as the current limiting layer 30. In the case of regrowth, the upper cladding layer 17 of the 2 μm p-InP 17, The device is grown by growing in the order of 0.1 μm p ⁺ −InGaAs contact layer 18.

Next, as shown in FIG. 6, an electrode is formed in a predetermined region of the upper part of the device, the back surface of the substrate is polished and thinned, and then a back electrode is formed to complete the device.

The device is cleaved in the form of an array and then subjected to antireflective coating across the facet to lower the reflectance.

Next, the chip is separated, and then the module is completed by the normal packaging method.

The embodiment manufactured in this manner shows the characteristics as shown in FIGS. 14 to 16.

14 is a far field pattern of a semiconductor optical amplifier incorporating the spot size converter fabricated as described above. Where? Is the vertical far field pattern, and + is the horizontal far field pattern. FIG. 15 is a graph showing gain characteristics of the SOA device with increasing injection current, and FIG. 16 is a graph showing ASE power according to the wavelength of the SOA device.

The semiconductor optical amplifier integrated with the spot size converter fabricated in this way has the advantages of FFP reduction, reflectance reduction, gain characteristics, noise characteristics, ease of device fabrication due to reduced coating conditions, optical fiber coupling efficiency, and array devices. It has advantages such as improved uniformity when manufacturing furnace. In detail, these characteristics are as follows.

First, the angle of the far field pattern (FFP) is reduced.

Conventional semiconductor waveguides are very small in size and have a large difference in refractive index with the cladding layer, so that the spot-size is relatively small compared to the optical fiber. This small spot-size gives a large divergence angle when it comes out, and the FFP divergence angle of a typical waveguide is about 50 ° × 50 °, so that the coupling loss with the optical fiber is very large. Therefore, the spot-size conversion semiconductor optical amplifier according to the present invention simultaneously tapers in the horizontal direction and the vertical direction to maximize the SSC effect to obtain a very small divergence angle of about 10 ° × 10 °. It is possible to manufacture a device having a through it can significantly improve the coupling efficiency with the optical fiber. Increasing the coupling efficiency increases the module's fiber-to-fiber gain and improves noise characteristics. In addition, SSC enhances the effect of reducing the reflectivity due to the inclination of the waveguide, thereby lowering the reflectance and alleviating the conditions of the antireflective coating.

Second, it has a low reflectivity.

When the waveguide is inclined, the amount of light returned from the facet is relatively reduced, and thus the reflectance is reduced by about one order. The SSC effect reduces the reflectance by more than two orders. There is an advantage in that the conditions of the coating can be relaxed by about one order. In addition, since the window structure emits isotropically without guiding light, this effect can further reduce the reflectance.

Third, the production is easy.

The waveguide inclination, tapering, window, etc. are too large to be lost in the conventional method to fabricate a device having excellent characteristics, but in the present invention, a mask on a narrow stripe over a large SAG growth region is not possible. By the method of etching again by placing the can be easily formed without any waveguide of any type.

Claims (23)

delete delete delete delete delete delete (A) Using a selective area growth method on a semiconductor substrate, grow an optical waveguide structure on a stripe that becomes thinner as the thickness of the spot size conversion area at both edges is closer to the cleaved surface than the gain region at the center, but is perpendicular to the vertical direction of the cleaved surface. Growing inclined; (B) In the stripe optical waveguide structure grown in the step (a), the gain area is etched to the edge portion roughly grown on both sides in the width direction, and the spot size conversion area is etched to be narrower as it is closer to the cleavage surface. To form an optical waveguide on the stripe; And (C) growing a current limiting layer on both sides of the optical waveguide on the stripe, depositing a window material between the cleaved surface and the end of the optical waveguide to form a window structure, and then on the optical waveguide and the current limiting layer Forming an upper structure of the optical amplifier; A manufacturing method of a semiconductor optical amplifier with a spot size converter, characterized in that it comprises a. The method of claim 7, wherein An n-InP substrate is used as the semiconductor substrate, and the (a) step is (A-1) sub-step of forming a dielectric film on the n-InP substrate; (A-2) sub-steps of patterning the dielectric film to form a mask for selective growth; And (A-3) A waveguide structure including a lower cladding layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper cladding layer, and an etch stop layer is grown by the SAG method of a conventional MOVPE using the selective growth mask. Sub-steps A manufacturing method of a semiconductor optical amplifier with a spot size converter, characterized in that it comprises a. The method of claim 8, In the sub-step (A-1), the dielectric film is formed by depositing SiO ₂ or Si ₃ N ₄ by PECVD or sputtering. The method of claim 8, In the sub-step (A-2), the dielectric film is patterned by photolithography, wherein the open area between the masks is 15 μm, and is formed to be inclined at about 7 ° to 10 ° with respect to the vertical direction of the cleaved surface. A manufacturing method of a semiconductor optical amplifier in which a spot size converter is integrated. The method of claim 8, In the sub-step (A-2), the width of the selective growth mask is 150 μm that determines the difference in growth rate and composition between the open area and the outside area of the mask between the masks, and has a thickness ratio of about 3: 1. A method for fabricating a semiconductor optical amplifier incorporating a spot size converter, characterized in that it is possible to obtain. The method of claim 8, In the substep (A-3), the lower cladding layer grows n-InP to 1 μm thick, the lower waveguide layer grows InGaAsP to 0.1 μm thick, and the active layer has InGaAsP 0.2 μm to 0.25 Grow to a thickness of μm, the upper waveguide layer to grow InGaAsP to a thickness of 0.1 μm, the top clad layer to grow p-InP to 0.4 μm, and the etch stop layer to grow p-InGaAs (P) 0.05 A method for fabricating a semiconductor optical amplifier incorporating a spot size converter, characterized by growing to a thickness of 탆. The method according to claim 7 or 8, The (b) step, (B-1) removing the etch stop layer using the etch stop layer and then removing the etch stop layer; (B-2) depositing a dielectric film; (B-3) a sub-step of patterning the dielectric film by a conventional lithography process to form a mesa etching mask by aligning the center film in parallel with the center of the selective growth region; And (B-4) a sub-step of etching the waveguide structure on the stripe using the mesa etching mask to form an optical waveguide on the buried stripe having an almost vertical inclination; A manufacturing method of a semiconductor optical amplifier with a spot size converter, characterized in that it comprises a. The method of claim 13, In the sub-step (b-2), the dielectric film is formed by depositing SiO ₂ or Si ₃ N ₄ by plasma enhanced chemical vapor deposition or sputtering. How to make. The method of claim 13, In the (b-3) sub-step, the selective growth of the mesa etching mask is performed such that the width of the gain region of the optical waveguide is 1 μm and the end portion of the optical waveguide is not more than 0.2 μm wide. A method of manufacturing a spot size converter integrated semiconductor optical amplifier, characterized in that the shape and width are adjusted on the waveguide structure. The method of claim 13, And (b-4) the sub-step is etched using a conventional wet etching method or a reactive ion etching method of CH ₄ / H ₂ system. The method of claim 13, In the step (b-4), the optical waveguide on the buried stripe has a width of a gain region of 1 mu m and an end portion of the waveguide is formed not to exceed 0.2 mu m. How to make. The method of claim 13, In the step (b-4), the optical waveguide on the buried stripe forms an inclination of 7 to 10 ° with the vertical plane of the cleaved surface, the width of the gain region is adjusted to 1 μm, and the end of the waveguide is formed to be 0.2 μm or less. A manufacturing method of a semiconductor optical amplifier in which a spot size converter is integrated. The method of claim 8, The (c) step, (C-1) a substep of re-growing on the substrate on the side of the optical waveguide on the stripe to form a current confined layer and forming a window region between the end of the optical waveguide and the cleaved surface; (C-2) removing the mesa etching mask; And (C-3) sub-growing the upper clad layer and the contact layer on the current limiting layer and the optical waveguide; A manufacturing method of a semiconductor optical amplifier with a spot size converter, characterized in that it comprises a. The method of claim 19, In the sub-step (C-1), the window area has a width of 15 to 25 μm, and the spot size converter is integrated. The method of claim 19, In the step (c-3), the current limiting layer is formed using p-InP / n-InP or semi-insulating InP, and the upper clad layer is formed by depositing p-InP to a thickness of 2 μm, Wherein the contact layer is formed by depositing p ⁺ -InGaAs to a thickness of 0.1 μm. The method of claim 7, wherein And (b) applying anti-reflective coating to both ends of the facet after the step (c) to lower the reflectance. 2. The method of claim 22, The anti-reflective coating is SiO ₂ / TiO ₂ The manufacturing method of a semiconductor optical amplifier with a spot size converter integrated.