KR100431242B1 - Substrate for LCD and method for fabricating of the same - Google Patents

Abstract

The present invention relates to a method of measuring ΔV _P of an array substrate for a liquid crystal display device.

In the related art, since the ΔV _P value generated in each pixel constituting the array substrate could not be accurately measured, the flicker pattern generated by the ΔV _P value was floated, and then the common voltage was manually adjusted to remove the flicker pattern. The ΔV _P value was corrected by the method.

As described above, the common voltage adjusting method does not find an accurate ΔV _P value because the flicker pattern is checked by the human eye, and it takes a long time because it needs to be measured for each gray.

In order to solve this problem, the present invention adds a separate wiring contacting the pixel electrode of the array substrate, so that an accurate waveform of a signal flowing to each pixel can be measured through the wiring.

With this method, it is easy to correct the value ΔV _P it is possible to relatively accurately measure the value ΔV _P. Therefore, defects such as flicker or residual image due to ΔV _P can be prevented, and thus it is possible to manufacture a liquid crystal panel having a clearer image quality.

Description

Array substrate for liquid crystal display device and manufacturing method thereof {Substrate for LCD and method for fabricating of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device (LCD), and more particularly, to a configuration of a switching element formed on an array substrate, wherein the parasitic capacitance generated at the overlapping area of the gate electrode and the drain electrode constituting the switching element ( C _gd ) relates to an array substrate for a liquid crystal display device and a method of manufacturing the same for measuring an accurate value of ΔV _p , which is a direct current component generated in a pixel region.

1 is an exploded perspective view schematically illustrating a general liquid crystal display device.

As shown in the drawing, a general liquid crystal display device 11 includes a plurality of sub color filters 7, a black matrix 6 disposed between each sub color filter, and the sub color filter 7 and the black matrix 6. An upper substrate 5 having a transparent common electrode 18 deposited thereon, a pixel region P, a pixel electrode 17 formed on the pixel region, a switching element T, and a lower array array formed thereon. It consists of a substrate 22, the liquid crystal 14 is filled between the upper substrate 5 and the lower substrate 22.

The lower substrate 22 is also called an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 and the data wiring 15 passing through the plurality of thin film transistors cross each other. Is formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area as described above.

The pixel electrode 17 uses a transparent conductive metal having a relatively high transmittance of light, such as indium-tin-oxide (ITO).

The operation of the liquid crystal panel having the configuration as described above is due to the operating characteristics due to the electro-optical effect of the liquid crystal.

In detail, the liquid crystal (14 of FIG. 1) is a dielectric anisotropic material having spontaneous polarization characteristics, and when a voltage is applied, a dipole is formed by spontaneous polarization to change the arrangement direction of molecules according to an application direction of an electric field. .

Therefore, the optical characteristic is changed according to this arrangement state, thereby causing electrical light modulation.

The image is realized by a method of blocking or passing light by the light modulation phenomenon of the liquid crystal.

FIG. 2 is an enlarged plan view showing only some pixels in the configuration of FIG. 1.

The elements necessary for driving the liquid crystal 14 of the above-described configuration are connected to the gate wiring 13 and the data wiring 15 for transmitting signals, the gate wiring and the data wiring, respectively, and the gate wiring 13. And a thin film transistor T which is a switching element positioned at the intersection of the data line 15 and the pixel electrode 17 connected to the thin film transistor.

The thin film transistor T includes a gate electrode 31 connected to the gate wiring 13, a source electrode 33 and a drain formed on the gate electrode 31 to overlap a predetermined area with the gate electrode 31. Comprising an electrode 35, the source electrode and the drain electrode are formed spaced apart with the semiconductor layer 32 therebetween.

The semiconductor layer 32 is generally formed using amorphous silicon (a-Si: H), and may be formed of polysilicon in some cases.

In this case, the source electrode 33 is connected to the data line 15 intersecting the gate line 13, and the drain electrode 35 is the pixel electrode 17 positioned on the pixel area P. Connected with

A portion of the pixel electrode 17 extends to an upper portion of the gate line 13 defining the pixel area P to form a storage capacitor C _st and C together with the gate line.

In the above-described configuration, the liquid crystal panel applies a gate voltage (scan pulse) to the gate electrode 31 of the thin film transistor T connected to the gate wiring 13 to turn on the switching element, and the gate voltage When a pixel voltage (video signal pulse), which is amplitude-modulated from the drain electrode in synchronization with (scanning pulse), is transmitted to the pixel, the liquid crystal (14 in FIG. 1) distributed on the pixel electrode is polarized by the transmitted signal. Will rearrange.

If the gate wiring is not selected, the gate state is turned off, and the charge accumulated in the pixel through the thin film transistor continues to discharge to the thin film transistor and the liquid crystal in the off state.

The discharge phenomenon may cause the charges charged in the pixel to be discharged quickly even when the off resistance of the thin film transistor is large or the area of the pixel is small to increase the resolution.

In order to prevent this phenomenon, the storage capacitor C _st is connected to the pixel electrode in parallel, and the storage capacitor serves to maintain the pixel voltage by supplementing the discharged charge. .

In this case, the input pixel voltage is affected by the parasitic capacitance between the terminals of the thin film transistor.

The parasitic capacitance component between the terminals of the thin film transistor T is generated in a portion where the gate electrode 31 and the source electrode 33 overlap and a portion where the gate electrode 31 and the drain electrode 35 overlap. In addition, the parasitic capacitance generated at the portion where the gate electrode 31 and the drain electrode 35 overlap (hatched region of FIG. 2) is referred to as C _gd , and the drain electrode 35 and the gate electrode 31 The parasitic capacitance due to the overlapping area affects the arrangement characteristics of the liquid crystal (14 in FIG. 1) positioned on the pixel electrode 17.

Variation in the parasitic capacitance configured as described above causes flicker and display unevenness to be increased.

3 is a waveform predicting a voltage waveform according to a gate signal flowing through the gate wiring.

As shown, the pixel voltage (video signal pulse) 23 transferred through the data wiring in the gate voltage (scan pulse) 21 is turned on (21a) through the liquid crystal capacitor and the drain electrode of the thin film transistor. Applied to the storage capacitor.

At this time, the pixel voltage (image signal pulse) 23 applied together with the gate voltage (scan pulse) 21 is maintained even after the gate voltage is turned off.

However, due to the parasitic capacitance C _gd between the gate electrode and the drain electrode, the pixel voltage 23 ′ generates a voltage shift by ΔV _p (25).

This is generally referred to as a level shift voltage or kickback voltage.

Such kickback voltage ΔV _p 25 is a DC voltage offset ΔV generated at the pixel voltage V _{p (t)} 23 ′ driven by parasitic capacitance as shown in FIG. 3.

This offset can be expressed by the following equation (1).

-------- (One)

Where ΔV _g represents the pulse width change of the gate signal, C _lc represents the capacitor capacitance of the liquid crystal, C _st represents the storage capacitance, and C _gd represents the parasitic capacitance generated at the overlapping area of the gate electrode and the drain electrode. .

This kickback voltage is a value that cannot be removed due to the structure of the liquid crystal panel.

Therefore, a method of correcting the ΔV _P value using a common voltage is used.

The ΔV _P value is a value that cannot be measured directly by using a device, and a method of indirectly measuring a waveform of a data signal flowing through a pixel may be used.

However, there is no method of directly measuring the waveform flowing in each pixel of the array substrate, and after predicting the ΔV _P value by substituting the equation (1) using the approximate peripheral values, the reference value is referred to. Using the method to correct the ΔV _P value.

However, as described above, the calculated ΔV _P value is not an accurate method because many errors occur with actual values.

In addition, as another method for correcting ΔV _P , a flicker pattern is displayed by using a computing device (computer) using a separate program, and the observer directly applies a common voltage until the flicker pattern is almost removed. There is a method to adjust the ΔV _P value by adjusting it.

The method of floating the flicker pattern is to apply the voltage of the panel in the operation unit so that only the pixel to which the positive voltage is applied is turned on and the pixel to which the negative voltage is applied is turned off. Adjust the condition.

In this case, when the positive voltage and the negative voltage are different, the luminance varies between the frames and flickering flickers are observed in the observer's eyes.

In this case, the common voltage may be adjusted by using a variable resistor.

This common voltage adjustment method not only finds the exact value of ΔV _P because the observer's eye checks the removal of flicker, but also needs to measure the value of ΔV _P for each gray as a way to access the correct value. The disadvantage is that it takes a long time.

The present invention has been proposed for the purpose of solving such a problem, and the present invention aims to measure the correct ΔV _P by directly measuring the pixel voltage waveform input to the plurality of pixels of the array substrate.

1 is an exploded perspective view of a general liquid crystal display device;

2 is an enlarged plan view showing a single pixel of an array substrate for a liquid crystal display device;

3 is a diagram showing waveforms of signals applied to a general array substrate for a liquid crystal display device;

4 is a plan view schematically showing a part of an array substrate for a liquid crystal display device according to the present invention;

5A to 5D are process cross-sectional views cut along the line VV of FIG. 4 and according to a process sequence;

6 is a schematic plan view of an array substrate.

<Brief description of the main parts of the drawing>

101: array substrate 102: gate wiring

104: gate electrode 108: active layer

112: data wiring 114: source electrode

116: drain electrode 120: pixel electrode

An array substrate for a liquid crystal display device according to the present invention for achieving the above object is a substrate; Gate wiring and data wiring crossing the first insulating film on the substrate to define a pixel region; A switching element configured at an intersection point of the gate wiring and the data wiring and including a first electrode, a second electrode, a third electrode, and an active layer; A second insulating film formed over the switching element and exposing a part of the third electrode; A transparent pixel electrode formed on the pixel area while in contact with the exposed first electrode; A third insulating film formed over the transparent pixel electrode and exposing a portion of the transparent pixel electrode; And a low resistance wiring extending over the gate wiring or the data wiring while contacting the exposed pixel electrode.

The first electrode is a gate electrode connected to the gate wiring, the second electrode is a source electrode connected to the data wiring, and the third electrode is a drain electrode spaced apart from the source electrode by a predetermined distance.

The low resistance wiring is formed of one selected from the group of low resistance metals including gold (Au), platinum (Pt), and silver (Ag).

An array substrate manufacturing method for a liquid crystal display device according to an aspect of the present invention includes the steps of preparing a substrate; Forming a plurality of gate wirings and data wirings on the substrate to intersect with each other via a first insulating film to define a pixel region; Forming a switching device including first, second and third electrodes and an active layer at an intersection point of the gate wiring and the data wiring; Coating a second insulating film on the entire surface of the substrate on which the switching device is formed, to form a protective film exposing a portion of the third electrode of the switching device; Forming a transparent pixel electrode on the pixel area while contacting a portion of the exposed third electrode; Forming a third insulating film on the entire surface of the substrate on which the pixel electrode is formed, and then exposing a portion of the pixel electrode; Forming a low resistance wiring formed on the gate wiring or the data wiring while being in contact with the exposed pixel electrode.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

A characteristic of the present invention is to measure the kickback voltage (ΔVp) generated in each pixel, by connecting a low resistance wiring to a plurality of pixel electrodes configured on the array substrate, and measuring the pixel voltage waveform through the low resistance wiring to accurate kickback Characterized in that the voltage value can be measured.

4 is a plan view schematically illustrating a part of an array substrate for a liquid crystal display according to the present invention.

As shown, a plurality of gate wirings 102 and data wirings 112 intersect on a substrate to define a pixel region P, and at the intersections of the two wirings, a gate electrode 104 and a source electrode ( 114 and a thin film transistor T including a drain electrode 116 and an active layer 108 spaced apart from each other by a predetermined distance.

The gate wiring 102 is in electrical contact with the gate electrode 104 to transmit a gate voltage, and the data wiring 112 is in electrical contact with the source electrode 114 to provide a data voltage. function to deliver voltage).

In the pixel region P, a transparent pixel electrode 120 in contact with the drain electrode 116 is formed, and a low resistance wiring 124 in electrical contact with the pixel electrode 120 is separately formed. do.

The low resistance wiring 124 is formed on the pixel electrode 120 configured to be adjacent to the peripheral region of the array substrate 101, and is formed to extend to the upper portion of the gate wiring 102 or the data wiring 112. Withdraw to the outside of 101).

Through the configuration of the array substrate as described above, the waveform of the pixel voltage input to each pixel region P can be measured using the wiring drawn to the outer portion of the array substrate 101.

Hereinafter, a manufacturing process of an array substrate for a liquid crystal display device according to the present invention will be described with reference to the drawings.

5A through 5D are cross-sectional views taken along the line V-V of FIG. 4 according to a process sequence (see plan view of FIG. 4).

First, as shown in FIG. 5A, a conductive metal is deposited and patterned on the substrate 100 to form a gate wiring (102 of FIG. 4) and a gate electrode 104 protruding from the gate wiring 102 in a planar manner. Form.

The conductive metal is selected from conductive metal groups including aluminum (Al), aluminum alloy, copper (Cu), tungsten (W), molybdenum (Mo), antimony (Sb), chromium (Cr) and the like.

Next, silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate 100 on which the gate electrode 104 or the like is formed to form a gate insulating layer 106 as a first insulating layer.

Next, as shown in FIG. 5B, pure silicon (a-Si: H) and amorphous silicon (p + or n + a-Si) containing impurities are formed on the entire surface of the substrate 100 on which the gate insulating layer 106 is formed. : H) is deposited and patterned to form the active layer 108 and the ohmic contact layer 110.

Next, the conductive metal as described above is deposited and patterned on the entire surface of the substrate 100 on which the active layer 108 and the ohmic contact layer 110 are formed, and intersect with the gate wiring (102 in FIG. 4) to form a pixel region. And a data electrode 112 defining a data line, a source electrode 114 protruding in a plane from the data line 112, and a drain electrode 116 spaced a predetermined distance from the data line 112.

Next, as shown in FIG. 5C, an organic material including benzocyclobutene (BCB) and an acrylic resin (Resin), etc., is formed on the entire surface of the substrate 100 on which the source and drain electrodes 114 and 116 are formed. One of the insulating material groups is coated to form a protective film 118 that is a second insulating film.

Subsequently, the passivation layer 118 is patterned to form a first contact hole K1 exposing a part of the drain electrode 116.

Next, one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited and patterned to contact the exposed drain electrode 116 and the pixel region. The transparent pixel electrode 120 is formed to be positioned at (P).

Next, as shown in FIG. 5D, a third insulating layer 122 is formed by depositing or coating an insulating material on the entire surface of the substrate 100 on which the pixel electrode 120 is formed.

Subsequently, the third insulating layer 122 is patterned to form a second contact hole K2 through which a portion of the pixel electrode 120 is exposed.

Next, a low resistance metal such as gold (Au), platinum (Pt), and silver (Ag) is selectively deposited and patterned on the entire surface of the substrate 100 on which the third insulating layer 122 is formed, thereby exposing the exposed pixel electrode. The low resistance wiring 124 is formed along the data wiring 112 to the outside of the substrate while being in contact with the 120.

As described above, the liquid crystal display array substrate 101 according to the present invention can be manufactured.

The low resistance wiring is used to measure the pixel voltage waveform of each pixel after completing the liquid crystal panel.

Therefore, even after completing the liquid crystal panel, a region where the low resistance wiring 124 is separately exposed for measurement should be secured. A description with reference to FIG. 6 is as follows.

6 is a plan view schematically showing an array substrate according to the present invention.

As shown, most of the array substrate 101 is used as an image display area L, but in order to receive an image signal and a gate signal, a peripheral portion of one side of the array substrate 101 and the other side not parallel to the array substrate 101 is used. The area is used as the drive area M.

The driving region M is a region where TCP, etc., on which a driving element is mounted, contacts one end of each of the wirings.

Accordingly, the low resistance wiring of the array substrate 101 may include a region N including one side of the array substrate 101 to be used as the driving region M and the other side not parallel thereto. Withdraw).

Thereafter, after the liquid crystal panel is completed, the waveform of the pixel voltage generated in each pixel may be measured through the extracted low resistance wiring.

Therefore, ΔV _P may be measured by comparing the pixel voltage waveform and the initially input data signal waveform.

When the ΔV _P value is measured, the input unit for inputting the data signal is controlled to input a data signal that compensates for the ΔV _P value from the beginning.

In this way, poor image quality such as flickering of the screen or image steaking can be improved.

Therefore, when the array substrate for the liquid crystal display device is manufactured according to the present invention, the waveform of the data signal can be accurately measured through the low resistance wiring.

Therefore, it is possible to accurately correct the ΔV _P value, which has the effect of producing a high-quality liquid crystal panel.

Claims (6)

A substrate; Gate wiring and data wiring intersecting the first insulating film on the substrate to define a pixel region; A switching element configured at an intersection point of the gate wiring and the data wiring and including a first electrode, a second electrode, a third electrode, and an active layer; A second insulating film formed over the switching element and exposing the third electrode; A transparent pixel electrode formed on the pixel area while in contact with the exposed third electrode; A third insulating film formed over the transparent pixel electrode and exposing the transparent pixel electrode; A low resistance wiring extending over the gate wiring or the data wiring while being in contact with the exposed pixel electrode Array substrate for a liquid crystal display device comprising a. The method of claim 1. And the first electrode is a gate electrode connected to the gate wiring, the second electrode is a source electrode connected to the data wiring, and the third electrode is a drain electrode spaced apart from the source electrode. The method of claim 1, And the low resistance wiring is formed of one selected from a group of low resistance metals including gold (Au), platinum (Pt), and silver (Ag). Preparing a substrate; Forming a plurality of gate wirings and data wirings on the substrate to intersect with each other via a first insulating film to define a pixel region; Forming a switching device including first, second and third electrodes and an active layer at an intersection point of the gate wiring and the data wiring; Coating a second insulating film on the entire surface of the substrate on which the switching element is formed, to form a protective film exposing a portion of the third electrode of the switching element; Forming a transparent pixel electrode on the pixel region while contacting a portion of the exposed third electrode; Forming a third insulating film on the entire surface of the substrate including the pixel electrode, and then exposing the pixel electrode; Forming a low resistance wiring formed on the gate wiring or the data wiring while being in contact with the exposed pixel electrode; Array substrate manufacturing method for a liquid crystal display comprising a. The method of claim 4. The first electrode is a gate electrode connected to the gate wiring, the second electrode is a source electrode connected to the data wiring, and the third electrode is a drain electrode spaced apart from the source electrode. The method of claim 4, wherein And the low resistance wiring is formed of one selected from a group of low resistance metals including gold (Au), platinum (Pt), and silver (Ag).