KR100428617B1 - A scan electrode driving device of an ac plasma display panel which is reduced the number of a driving switch - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan electrode driving apparatus of an AC plasma display panel having a reduced number of driving switches.

The present invention provides a reset period for initializing the state of each discharge cell, a scan period for determining and addressing the discharge cells on and off, a sustain period for discharging the addressed cells, and applying a predetermined erase pulse to stop the sustain discharge. An apparatus for driving an alternating current plasma display panel including an erasing period, the apparatus comprising: separating a power transfer path delivered to the discharge cell to cause a reset discharge and an incoming power transfer path from the discharge cell; By simplifying the configuration of the scan electrode driver and reducing the manufacturing cost by eliminating the switch present in the supply and intake paths of the driving power for the reset discharge, the scan pulse waveform is changed by changing the current path according to the removal of the switch. The generation can be performed effectively.

Description

A SCAN ELECTRODE DRIVING DEVICE OF AN AC PLASMA DISPLAY PANEL WHICH IS REDUCED THE NUMBER OF A DRIVING SWITCH}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC plasma display panel, and more particularly, to a scan electrode driving apparatus of an AC plasma display panel capable of setting a power flow path between a plasma display panel and a driving circuit by reducing the number of driving switches in the scan (Y) electrode driving circuit. It is about.

In general, a plasma display panel (PDP) is a flat panel display device that displays characters or images by using plasma generated by gas discharge, and a matrix of tens to millions or more of pixels is matrixed according to its size. It is arranged in (matrix) form. The plasma display panel is classified into a direct current type (DC type) and an alternating current type (AC type) according to the shape of the driving voltage waveform applied and the structure of the discharge cell.

The structural difference between the direct current type and the direct current type is that in the direct current type, the electrode is exposed to the discharge space as it is, so that the current flows in the discharge space while the voltage is applied. Therefore, there is a disadvantage in that the resistance for current limitation must be made externally. On the other hand, in the case of the AC type, the dielectric layer covers the electrode so that the current is limited by the natural capacitive formation, and the life is longer than that of the DC type because the electrode is protected from the impact of ions during discharge. The memory characteristic, which is one of the important characteristics of the AC plasma display panel, also comes from the capacitive property of the dielectric layer covering the electrode.

In the light emission principle of the AC plasma display panel, a pulse type potential difference is formed between the common electrode (or X electrode, hereinafter referred to as X electrode) and the scan electrode (or Y electrode, hereinafter referred to as Y electrode) to generate a discharge. In this case, the vacuum ultraviolet rays generated in the discharge process are excited to the red (R), green (G), and blue (B) phosphors, and each phosphor emits light by light combination. These discharges are affected by various parameters, but they are largely related to the discharge gas type and pressure inside the plasma display panel, and the secondary electron emission characteristics of the magnesium oxide (MgO) protective film. It depends a lot.

The AC plasma display panel has a capacitance for the common electrode and the scan electrode because the common electrode and the scan electrode act as capacitive loads, and in order to apply a waveform for the sustain discharge, in addition to the power for the discharge. Reactive power is needed. A circuit for recovering and reusing such reactive power is called a sustain discharge circuit (or a power recovery circuit).

1 is an electrode arrangement diagram of a typical plasma display panel.

The electrodes have a matrix configuration of m columns X n rows. Address electrodes A1 to Am are arranged in the column direction, and n rows of scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn are arranged in the row direction. The discharge space at the intersection of the address electrode, the paired scan electrode, and the sustain electrode forms a discharge cell.

Fig. 2 is a circuit diagram showing a conventional Y electrode driving circuit.

As shown in FIG. 2, the conventional Y electrode driving circuit includes a power recovery unit 10, a reset pulse supply unit 20, a scan pulse supply unit 30, and a scan buffer IC 40.

The power recovery unit 10 includes switches Yr, Ys, Yf, and Yg, power recovery capacitors Css, diodes D1 and D2, and an inductor L, and switches Yr and Ys according to an operation sequence. Power is supplied to the panel Cp according to the switching operation of, Yf, Yg, and the power is recovered again after the discharge is performed. The reset discharge unit 20 includes a switch (Yrr, Yfr) for supplying a reset pulse waveform, a switch (Yp) for separating the power recovery unit 10 and the scan pulse supply unit 30 when a reset waveform is generated, and a reset. It comprises a switch (Ysp), a diode (D3), a capacitor (C1) for lowering the ramp waveform of the period from the voltage (Vset) to the voltage (Vs), and generates a reset pulse to initialize the state of each discharge cell. The scan pulse supply unit 30 includes a switch (Ysc) and a diode (D4) for supplying a scan pulse waveform. The scan pulse supply unit 30 selects each discharge cell and selects and discharges a discharge cell to be turned on and a discharge cell not to be turned on. do. The scan buffer IC 40 supplies a sustain waveform to the discharge cells through an internal diode (not shown) to cause sustain discharge.

In the above panel driving method by the Y electrode driving circuit, one frame is composed of n subfields, and one subfield is composed of a reset period, a scan period, a sustain period, and an erase period.

In the reset period, all address electrodes A1 to Am and all sustain electrodes SUS1 to SUSn are held at 0 V in the first half, and voltages which are equal to or lower than the discharge start voltage with respect to the sustain electrodes in all scan electrodes SCN1 to SCNn. The ramp voltage that rises smoothly toward the voltage exceeding the discharge start voltage from is applied to the switch Yrr. In the second half of the reset period, all of the scan electrodes are applied to the switch Yfr with a ramp voltage which gradually falls from 0 volts below the discharge start voltage to 0 V over the discharge start voltage with respect to the sustain electrode.

During the scan period, all the Y electrodes are held at the voltage Vsc, and a positive scan pulse voltage is applied to the address electrodes corresponding to the discharge cells to be displayed on the first row of the addressing electrodes, and the scan pulse voltage (0 V) to the Y electrodes of the first row. Are simultaneously applied to allow wall charge to accumulate. In the sustain (or sustain) period, a predetermined sustain pulse is applied to all the Y electrodes and the X electrodes to cause the sustain discharge to occur at a gradation to be expressed in the discharge cells, and a predetermined erase pulse is applied to all the X electrodes in the erase period. Is applied to stop the sustain discharge.

In the driving circuit to which the panel driving method is applied, a plurality of switches Yp exist in the reset discharge portion 20 of the Y electrode driving circuit 1 which generates the ramp waveform applied in the reset period. The switch Yp serves as a path for the current flowing between the driving circuit and the panel, and separates the power recovery unit 10 and the scan pulse supply unit 30 when a reset waveform is generated. The switch Ysp Is a function of lowering the ramp waveform of the reset period from the voltage Vset to the voltage Vs.

However, in the above-described conventional Y electrode driving circuit, the switch Ysp occupies a large portion in the circuit configuration, and there is a disadvantage in terms of the manufacturing cost of the driving circuit due to the use of the switch. There is a problem.

In addition, since the switch Ysp is located at the position of the large current path in the current path, there is a problem in that the output characteristic of the drive circuit is undesirable.

In order to solve this problem, a technical problem of the present invention is to remove the switch present in the main path through which the current flows, and to change the position of a specific switch to isolate the current transfer path.

In addition, by changing the current path following removal of the switch, another object is to improve the heat loss of the switch due to current conduction and to generate a sustain pulse.

In addition, it is another object to simplify the configuration of the scan electrode driving device and to provide an advantageous driving device in manufacturing cost.

1 is an electrode arrangement diagram of a typical plasma display panel.

Fig. 2 is a circuit diagram showing a conventional Y electrode driving circuit.

3 is a circuit diagram illustrating a scan electrode driving circuit of an AC plasma display panel according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a driving waveform according to an exemplary embodiment of the present invention.

5A to 5C are diagrams showing experimental results of a scan electrode driving circuit according to an exemplary embodiment of the present invention.

6 is a block diagram illustrating a plasma display panel including a Y electrode driving circuit according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

A1 to Am: address electrode SCN1 to SCNn: scan electrode SUS1 to SUSn: common electrode

Reference Signs List 10 power recovery section 20 reset pulse supply section 30 scan buffer IC

40: Scan pulse supply part Yr, Ys, Yf, Yg, Yrr, Yfr, Yp, Ysp, Yspl, Ysc: switch

Cp: Panel Capacitor Css: Power Recovery Capacitor

Vs: Externally Applied Voltage Vset: Reset Pulse Voltage Vsc: Scan Voltage

D1 ~ D4, Ds: Diode

100: power recovery unit 200: reset pulse generator 300: switching unit

400: scan pulse generator 500: scan buffer IC

1000: frame memory 2000: frame generator 3000: timing controller

4000: scanning circuit 5000: X electrode driver 6000: Y electrode driver

7000: Panel

4100: reset pulse generator 4200: recording pulse generator 4300: sustain pulse generator

4400: erase pulse generator

In order to achieve the above object, a scan electrode driving apparatus of an AC plasma display panel having a reduced number of driving switches according to an aspect of the present invention is provided.

A reset period for initializing the state of each discharge cell, a scan period for determining and addressing the discharge cells on and off, a sustain period for discharging the addressed cells, and an erase period for stopping the sustain discharge by applying a predetermined erase pulse An apparatus for driving an alternating current plasma display panel comprising:

And separating a power transfer path that is delivered to the discharge cell to cause a reset discharge and an incoming power transfer path from the discharge cell.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram illustrating a Y electrode driving apparatus of an AC plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the Y electrode driving apparatus of the AC plasma display panel according to an exemplary embodiment of the present invention may include a power recovery unit 100, a reset pulse generator 200, a switching unit 300, and a scan pulse generator. 400 and a scan buffer 500.

The power recovery unit 100 includes a switch Yr, Ys, Yf, and Yg, a power recovery capacitor Css, a diode D1 and D2, and an inductor L1 existing in a first path delivered to the panel in current flow. ), An inductor L2 existing in the second path recovered from the panel, and supplies power to the panel Cp to apply a waveform for sustain discharge, and recovers and reuses the supplied power.

The reset pulse generator 200 includes a switch (Yrr, Yfr), a diode (D3) for supplying a ramp type reset pulse waveform, and a capacitor (C1) for storing the driving voltage as much as the reset pulse voltage (Vset), the power Based on the power supplied from the recovery unit 100, a pulse for initializing the state of each discharge cell is supplied to the discharge cell so that an addressing operation is smoothly performed.

The switching unit 300 includes a switch Yspl and an internal diode Db that blocks a path of a current flowing from a current path supplied to the panel to a current path drawn from the panel, and is reset by the reset pulse generator 200. The rising reset voltage Vset among the ramp waveforms of the generated reset period is lowered to the externally applied voltage Vs.

The scan pulse generator 400 includes a switch Ysc and a diode D4 for supplying a scan pulse waveform, and accumulates wall charges in the addressed discharge cells.

The scan buffer 500 includes switches Yb1 and Yb2 and internal diodes (not shown). The scan buffer unit 500 includes a reset signal for initializing a state of each discharge cell and a scan signal for accumulating wall charges in the discharge cells. And stores the outputted signal at a predetermined timing, and supplies a sustain pulse during the sustain period through the internal diode.

Hereinafter, the operation of the Y electrode driving apparatus of the AC plasma display panel according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a driving waveform according to an exemplary embodiment of the present invention.

As shown in Fig. 4, in the initial state, the switch Yg is turned on just before the switch Yr is turned on, so that the voltage across the panel Cp is maintained at 0V. At this time, the power recovery capacitor Css is precharged by a voltage Vs / 2 equal to 1/2 of the externally applied voltage Vs so that an inrush current does not occur at the start of sustain discharge. When the voltage of both ends of the panel Cp is maintained at 0 V, when the switch Yr is turned on and the switches Ys, Yg, and Yf are turned off, the power recovery capacitor ( The LC resonant circuit is formed due to the path of Css, the switch Yr, the diode D1, the inductor L1, and the panel capacitor Cp. In the next operation, the switches Yr and Ys are turned on and the switches Yf and Yg are turned off, and the externally applied voltage Vs is applied to the panel capacitor Cp by the on operation of the switch Ys.

The switch Yrr is turned on to supply the rising ramp waveform, the switch Yrr is turned on, and the switch Yrr is turned on while the ramp waveform is supplied so that the voltage transferred from the Y electrode driving circuit to the panel Cp is shown in FIG. As described above, the voltage rises to the voltage to which the reset pulse voltage Vset is added to the externally applied voltage Vs. Accordingly, when the total voltage is calculated, the external applied voltage (Vs) + reset pulse voltage (Vset). At this time, a low level signal is applied to the gates of the switches Yspl and Yfr so that the voltage is increased to the voltage Vs + voltage Vset while the switches Yspl and Yfr are turned off. In an embodiment of the present invention, the external applied voltage (Vs) is driven at 160V, the reset pulse voltage (Vset) is driven at 220V so that the final rise voltage is 160V + 220V = 360V, but the present invention It is not limited only to the Example.

Next, when a high level signal is applied to the gate of the switch Yspl to start the operation, the switch Yspl is turned on and the driving voltage which has risen to the reset pulse voltage Vset is reduced to the externally applied voltage Vs. . That is, the conventional switch Ysp operates in a path having a large magnitude of current by being located in a path of current flowing from the panel Cp to the driving circuit, but the switch Yspl according to an embodiment of the present invention is a path for transferring current. Since it is not a path of large current in, only one FET (Field Effect Transistor) may be used. In addition, the switch Yspl performs a function of reducing the driving voltage, which has risen to the sum of the reset pulse voltage Vset and the externally applied voltage Vs, to the externally applied voltage Vs.

When the scan period starts, the high level signal is maintained at the gate of the switch Yfr while applying a scan pulse that operates during the scan period to the switch Ysc. Conventionally, the switch Yfr is turned off by the low level while the scan pulse is applied, but in the embodiment of the present invention, the switch Yfr remains on to the high level. For this reason, since the switch Yfr plays a role of applying ground bias to the low side during the scan period, the switch Yfr must be turned on during the scan period. As described above, since the scan period starts immediately after the polling ramp waveform ends, biasing the ground bias using the switch Yfr helps the characteristic of the scan waveform without passing through the switch Yp in FIG. 2.

When the sustain period starts, a sustain pulse is applied to a discharge cell by a sustain pulse supplied through an internal diode (not shown) of the scan buffer unit 500 so that sustain discharge occurs at a gray scale to be expressed. General description of the power recovery during the sustaining period is omitted below.

5A to 5C are diagrams showing experimental results of a scan electrode driving circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 5A, the sustain pulse after the switches Yp and Ysp are removed has a sustain pulse waveform through the internal diode (not shown) of the switch Yp as in the prior art when rising and polling. Since the noise is not generated in the pulse by the internal diode and the sustain pulse waveform passes through the diode Ds as in the embodiment of the present invention, it can be seen that the waveform at the time of rising and falling of the sustain waveform is cleaner. In addition, as shown in FIG. 6B, the waveform of the reset period according to the embodiment of the present invention is replaced with the diode Ds by eliminating the switch Yp, thereby generating a similar reset pulse waveform as in the waveform of the conventional reset period. Able to know. In addition, as shown in FIG. 5C, a portion falling from the voltage Vset to the voltage Vs among the waveforms of the reset period according to the embodiment of the present invention is the same as the conventional waveform by the operation of the switch Yspl. You can see that it is created.

6 is a block diagram of a plasma display panel including a Y electrode driving apparatus according to an exemplary embodiment of the present invention.

The analog image signal to be displayed on the panel 7000 is converted into digital data and recorded in the frame memory 1000. The frame generator 2000 divides digital data stored in the frame memory 1000 as necessary and outputs the divided digital data to the scanning circuit 4000. For example, in order to display gradations on the panel 7000, one frame of pixel data stored in the frame memory 1000 is divided into a plurality of subfields according to the gradation level, and the data of each subfield is output.

The scanning circuit 4000 scans the Y electrode driver 6000 and the X electrode driver 5000 of the panel 7000 and generates a signal waveform to be applied to each electrode in the reset period, the scan period, the sustain period, and the erase period. A reset pulse generator 4100, a scan pulse generator 4200, a sustain pulse generator 4300, and an erase pulse generator 4400. That is, the reset pulse generator 4100 generates a reset signal for initializing the state of each discharge cell, the scan pulse generator 4200 generates an address signal for selecting and addressing discharge cells that are turned on and discharge cells that are not turned on, The sustain pulse generator 4300 generates a sustain signal for discharging the cells addressed by the scan pulse generator 4200, and the erase pulse generator 4400 receives an erase signal for erasing wall charges accumulated on the electrodes by the sustain discharge. Generate. It also includes a synthesis circuit 4500 for synthesizing these signals and supplying the signals to each electrode. The timing controller 3000 generates various timing signals necessary for the operation of the frame generator 2000 and the scanning circuit 4000.

The embodiment of the present invention is only one embodiment, and many variations and modifications are possible in the configuration of the driving circuit within the scope not departing from the gist of the present invention, as well as the switches Yr and Ys of the embodiment of the present invention. , Yf, Yg, Yrr, Yfr, Yspl, Ysc, Ysb1, Ysb2) use a FET, but can be replaced with a switch that can perform the same function of the switch in addition to the embodiment of the present invention. It is not limited only to.

As described above, the scan electrode driving apparatus of the AC plasma display panel which reduces the number of driving switches of the present invention simplifies the configuration of the scan electrode driving apparatus and eliminates the switch existing in the main path through which the current flows. Provides an advantageous drive.

In addition, since the switch Yfr performs the ground bias in the scan period by changing the current path according to the removal of the switch Ysp, it helps the scan pulse waveform.

Claims (11)

An apparatus for driving a scan electrode of an AC plasma display panel including a plurality of scan electrodes and a common electrode, A first switch having one end electrically connected to a first power source that substantially supplies the first voltage, A second switch having one end electrically connected to a second power supply for supplying a second voltage, A first path electrically connected between the other end of the first switch and the scan electrode, A third switch electrically connected between the scan electrode and the other end of the first switch through a second path different from the first path, and A lamp voltage supply electrically connected to the first path and having a fourth switch; The fourth switch is turned on while the first switch is turned on and the first voltage is supplied to the scan electrode to increase the voltage of the scan electrode to the second voltage, and the third switch is turned on to scan the scan electrode. The voltage of the electrode decreases to the first voltage through the first switch, And the second path is electrically connected to the other end of the second switch. The method of claim 1, The lamp voltage supply unit further includes a capacitor having one end electrically connected to the other end of the first switch and substantially charging a voltage corresponding to a difference between the second voltage and the first voltage. And the fourth switch is electrically connected between the other end of the capacitor and the scan electrode. The method of claim 2, The first path may further include a first diode having an anode connected to one end of the capacitor and a cathode connected to the fourth switch. The method according to any one of claims 1 to 3, And a fifth switch connected to the first path to reduce the voltage of the scan electrode from the first voltage to a third voltage in the form of a lamp. The method according to any one of claims 1 to 3, A scan buffer unit for applying a scan signal to the scan electrode during an address period; A scan buffer unit for applying a scan signal to the scan electrode during an address period; The first path is electrically connected to the scan electrode through one end of the scan buffer unit, And a second path is electrically connected to the scan electrode through the other end of the scan buffer unit. The method according to any one of claims 1 to 3, And a second diode having an anode on the second path and a cathode on the scan electrode. An apparatus for driving a scan electrode of an AC plasma display panel including a plurality of scan electrodes and a common electrode, A first switch having one end electrically connected to a first power source that substantially supplies the first voltage, A second switch having one end electrically connected to a second power supply that substantially supplies a second voltage and the other end electrically connected to the scan electrode; A first capacitor having one end electrically connected to the other end of the first switch and charging a third voltage; A third switch having one end electrically connected to the other end of the first capacitor and the other end electrically connected to the scan electrode such that a ramp waveform is applied to the scan electrode; A diode having an anode electrically connected to one end of the capacitor and a cathode electrically connected to the other end of the second switch, and And a fourth switch electrically connected between the other end of the first switch and the scan electrode. The method of claim 7, wherein A second capacitor that is substantially charging a fourth voltage, A fifth switch and a first inductor electrically connected in series between one end of the second capacitor and the other end of the first switch, and And a sixth switch and a second inductor electrically connected in series between one end of the second capacitor and the contact point of the third switch and the scan electrode. The method according to claim 7 or 8, During the reset period, Turn on the first switch to apply the first voltage to the scan electrode; The third switch is turned on while the first switch is turned on to increase the voltage of the scan electrode to a voltage corresponding to the sum of the first voltage and the third voltage in the form of a lamp. And a third switch is turned off and the fourth switch is turned on to reduce the voltage of the scan electrode to the first voltage. The method of claim 9, And a seventh switch electrically connected between the scan electrode and a third power supply for supplying a fifth voltage, the seventh switch operative to reduce the voltage of the scan electrode from the first voltage into a lamp shape. Scanning electrode drive device. The method according to claim 7 or 8, A scan buffer unit for applying a scan signal to the scan electrode during an address period; The third switch and the diode are electrically connected to the scan electrode through one end of the scan buffer unit, And the second switch and the fourth switch are electrically connected to the scan electrode through the other end of the scan buffer unit.