KR100425588B1 - Method for manufacturing optical intergrated circuit - Google Patents

Abstract

The present invention discloses a method of manufacturing a light integrated circuit. The disclosed invention provides a compound substrate in which an active element region and a passive element region are defined and a core layer and a first clad layer are sequentially stacked. An etch stopper is formed on the first cladding layer of the passive element region, and a mask pattern is formed to form respective waveguides in the active element region and the passive element region. A first passivation layer is formed to cover the passive element region, and an active waveguide is formed by etching a predetermined thickness of the first cladding layer, the core layer, and the compound substrate using a mask pattern of the exposed active element region. After that, the first protective film is removed. Thereafter, a second cladding layer is formed on the compound substrate resultant, a second passivation layer is formed to cover the active device region, and the second cladding layer is wet etched to expose the etch stopper of the passive device region. Let's do it. Thereafter, the etch stopper is wet-etched in the form of a mask pattern of the passive element region, and a predetermined thickness of the first cladding layer, the core layer, and the compound substrate is dry-etched in the form of a mask pattern of the passive element region, thereby forming an active element waveguide. Forming a step.

Description

Method for manufacturing optical intergrated circuit

The present invention relates to a method for manufacturing a light integrated circuit, and more particularly, to a method for manufacturing a light integrated circuit in which an active device and a passive device are integrated at the same time.

Generally, an integrated circuit is a circuit in which several optical elements having different configurations and functions, such as active elements and passive elements, active elements and active elements, or passive elements and passive elements, are optically coupled in one substrate. Say.

As such an optical integrated circuit, a form of integrating a buried ridge stripe (BRS) type active element and a ridge type passive element is used. An optical integrated circuit having such a configuration will be described with reference to FIGS. 1A to 1E. Do it.

First, referring to FIG. 1A, an optical element substrate 1 in which an active element region A and a passive element region B are defined is provided. Core layers 2 and 3 that guide light are formed on the substrate 1. The core layer 2 of the active element region A is preferably formed thinner than the core layer 3 of the passive element region B. FIG. After forming a first clad layer 4 on the core layers 2 and 3, a first mask pattern 10 is formed on the first clad layer 4. The first mask pattern 10 is a mask for defining a waveguide of the active element, and the active element region A is formed in a stripe shape while the passive element region B is shielded.

Next, as shown in FIG. 1B, by using the first mask pattern 10, a predetermined depth of the first cladding layer 4, the core layer 2, and the substrate 1 is etched to form an active element region. A ridge type active element waveguide 20 is formed in (A). In this case, the first mask pattern 10 is removed after etching the limiting layer 4, the core layer 2, and the substrate 1.

As shown in FIG. 1C, the second cladding layer 5 is formed on the result of the optical device substrate 1 on which the active device waveguide is formed. Accordingly, the active element waveguide 20 is covered by the second cladding layer 5 with the top and both sidewalls thereof.

Subsequently, as illustrated in FIG. 1D, a second mask pattern 11 is formed on the second clad layer 5 to define the waveguide of the passive element. At this time, the second mask pattern 11 is shielded from the active element region A, and has a stripe shape in the passive element region B. FIG. At this time, the line width of the second mask pattern 11 on the passive element region B is larger than the line width of the active element waveguide 20.

Thereafter, as shown in FIG. 1E, the second cladding layer 5, the first cladding layer 4, the core layer 3, and the substrate 1 of the passive element region using the second mask pattern 11. Dry etching a predetermined thickness of the ridge-type passive element waveguide 30 is formed.

However, when integrating an active element and a passive element as in the prior art, there are the following problems.

As described above, since the waveguide of the passive element is formed after the second cladding layer 5 is formed, a very thick film must be dry-etched during the etching process for forming the waveguide of the passive element. As a result, it takes a longer time than when forming the waveguide of the active element, and a large amount of etching by-products such as polymers are generated during dry etching. In addition, since the height of the passive element waveguide is relatively higher than the height of the active element waveguide, it is fragile and difficult to cleave. Therefore, the probability of damage is also high and it is difficult to couple to the optical fiber.

On the other hand, in the optical integrated circuit, since a mask pattern for forming a waveguide of an active element and a mask pattern for forming a waveguide of a passive element are formed separately, it is difficult to accurately align these two masks.

Accordingly, an object of the present invention is to provide a method of manufacturing an optical integrated circuit capable of reducing the amount of dry etching by forming a waveguide of a passive element and reducing process time, and at the same time reducing the generation of etching byproducts.

Another object of the present invention is to provide a method of manufacturing an optical integrated circuit capable of preventing misalignment by forming a waveguide of an active element and a waveguide of a passive element as one mask.

1A to 1E are cross-sectional views of respective processes for explaining a method of manufacturing a conventional optical integrated circuit.

2A to 2G are cross-sectional views of respective processes for explaining a method of manufacturing an optical integrated circuit according to the present invention.

(Explanation of symbols for the main parts of the drawing)

100 substrate 105a, 105b core layer

110: first cladding layer 115: etch stopper

120a and 120b: mask pattern 125: first protective film

130: active element waveguide 135: second clad layer

140: second protective film 145: passive element waveguide

Other objects and novel features thereof, together with the objects of the present invention, will be apparent from the description and the accompanying drawings.

Among the inventions disclosed herein, an outline of representative features is briefly described as follows.

First, an active element region and a passive element region are defined, and a compound substrate in which a core layer and a first clad layer are sequentially stacked is provided. An etch stopper is formed on the first cladding layer of the passive element region, and a mask pattern is formed to form respective waveguides in the active element region and the passive element region. A first passivation layer is formed to cover the passive element region, and an active waveguide is formed by etching a predetermined thickness of the first cladding layer, the core layer, and the compound substrate using a mask pattern of the exposed active element region. After that, the first protective film is removed. Then, a second cladding layer is formed on the compound substrate resultant, a second passivation layer is formed to cover the active device region, and the second cladding layer is wet etched to expose the mask pattern of the passive device region. Let's do it. Thereafter, wet etching is performed to the etch stopper in the form of a mask pattern of the passive element region, and dry etching of a predetermined thickness of the first cladding layer, the core layer and the compound substrate in the form of a mask pattern of the passive element region, thereby Forming a step.

Here, the core layer of the active element region is formed relatively thinner than the core layer of the passive element region. In addition, the mask pattern is formed of a material having a different etching selectivity from the first or second cladding layer.

The first and second passivation layers may be formed of a material having a different etching selectivity from the mask pattern, and the first and second passivation layers may be formed of a photoresist layer.

In addition, the first and second passivation layers may be formed of the same insulating layer as the mask pattern. In this case, the thickness of the first and second passivation layers may be smaller than that of the mask pattern.

After forming the passive element waveguide, the second passivation layer and the mask pattern may be further removed.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, a layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. Can be done.

2A to 2G are perspective views of respective processes for explaining a method of manufacturing an optical integrated circuit according to the present invention.

First, referring to FIG. 2A, an optical device substrate 100 in which an active device region C and a passive device region D are defined is provided. In this case, the optical device substrate 100 may be a compound semiconductor substrate. In addition, a multi-layer compound semiconductor layer, for example, a multi-layered InP layer may be deposited on the optical device substrate 100. Core layers 105a and 105b for guiding light are formed on the optical device substrate 100. At this time, the core layer 105a (hereinafter referred to as the first core layer) of the active element region C is formed relatively thinner than the core layer 105b (hereinafter referred to as the second core layer) of the passive element region D. The two core layers 105a and 105b may be formed of, for example, InGaAsP material. Next, a first cladding layer 110 that primarily constrains light is formed on the first and second core layers 105a and 105b to a predetermined thickness. In this case, the first clad layer 110 may be formed of an InP material. Then, the etch stopper 115 is formed only on the first cladding layer 110 in the passive element region D. FIG. At this time, the etch stopper 115 is formed of a material different in etching selectivity from the lower first cladding layer 110, as the name implies. Thereafter, a mask pattern 120 is formed on the optical device substrate 100 to simultaneously define the waveguides of the active element and the passive element. In this case, the mask patterns 120a and 120b formed in the active element region C and the passive element region D are each formed in a stripe shape, but the mask pattern 120b formed in the passive element region D is an active element. The line width of the mask pattern 120a of the region C is wider than that of the mask pattern 120a. In this case, the mask pattern 120 has an etching selectivity different from that of the first cladding layer 110, and the mask pattern 120 may be formed of, for example, an insulating film such as a silicon nitride film or a silicon oxide film.

Next, as shown in FIG. 2B, a first passivation layer 125 is formed on the passive element region D to protect the passive element region from the etching medium. The first passivation layer 125 may be formed of a material having an etching selectivity different from that of the material forming the mask pattern 120, for example, a photoresist film, and may be formed on the mask pattern 120b on the passive device region D. And the etch stopper 115. In this case, the first passivation layer 125 may be formed of the same material as the mask pattern 120 in some cases. As such, only the active element region C is exposed by the formation of the first passivation layer 125.

Referring to FIG. 2C, a predetermined thickness of the first cladding layer 110, the first core layer 105a and the substrate 100 in the form of a mask pattern 120a of the exposed active device region C is etched. Thus, the active element waveguide 130 is formed. In this case, after etching the first cladding layer 110, the first core layer 105a, and the substrate 100, the mask pattern 102a of the active device region C is removed.

As shown in FIG. 2D, the first passivation layer 125 of the passive element region D is removed by a known etching method. Accordingly, the mask pattern 120b and the etch stopper 115 of the passive element region D are exposed.

Next, as shown in FIG. 2E, a second clad layer 135 for secondly confining light is formed on the optical device substrate 100 by a predetermined thickness. In this case, the second clad layer 135 may also be formed of an InP layer. The active device waveguide 130 and the passive device region D are covered by the second cladding layer 135.

Referring to FIG. 2F, the second passivation layer 140 is formed to expose the passive element region D. Referring to FIG. In this case, the second passivation layer 140 may be formed of a material having a different etching selectivity from the mask pattern 120b or a thinner thickness than the mask 120b when it is to be formed of the same material as the mask 120b.

Then, as shown in FIG. 2G, the second cladding layer 130 of the passive element region D is removed by wet etching using the second passivation layer 140 as a mask. Then, the mask pattern 120b of the passive element region D is exposed, and wet etching is performed to the etch stopper 115 in the form of the mask pattern 120b. Thereafter, dry etching is performed by a predetermined depth of the first clad layer 110, the second core layer 105b, and the substrate 100 to form a passive element waveguide 145. In this case, since only the first cladding layer 110, the second core layer 105b, and the substrate 100 are etched by the dry etching process, the dry etching amount is reduced as compared with the related art.

Thereafter, the remaining mask pattern 120b and the second passivation layer 140 are removed in a known manner. In this case, the mask pattern 120b and the second passivation layer are etched after the dry etching process. In this way, a light integrated circuit in which an active element and a passive element are integrated is completed.

In the optical integrated circuit, as shown in FIG. 2G, the active element 130 is covered by the cladding layer, and the sidewall of the passive element 145 is exposed to the outside.

In addition, in the optical integrated circuit of the present invention, since the active element waveguide 130 and the passive element waveguide 145 are defined by one mask, automatic alignment may be achieved.

As described in detail above, according to the present invention, when the waveguide of the passive element is formed, the second cladding layer is selectively wet-etched, and then the dry etching amount is reduced by dry etching the first cladding layer, the core layer, and the substrate. You can. Accordingly, the etching time may be reduced, the amount of etching by-products may be reduced, and incomplete cleaving may be prevented.

In addition, the misalignment of the active element portion and the passive element portion can be prevented by defining the waveguide of the active element and the waveguide of the passive element by one mask.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (6)

Providing a compound substrate in which an active device region and a passive device region are defined, wherein a core layer and a first clad layer are sequentially stacked; Forming an etch stopper on the first clad layer in the passive element region; Forming a mask pattern for forming each waveguide in the active element region and the passive element region; Forming a first passivation layer to cover the passive element region; Forming an active waveguide by etching a predetermined thickness of the first cladding layer, the core layer, and the compound substrate using the mask pattern of the exposed active device region; Removing the first passivation layer; Forming a second clad layer on the compound substrate resultant; Forming a second passivation layer to cover the active element region; Wet etching the second clad layer to expose a mask pattern of a passive device region; Wet etching the etch stopper in the form of a mask pattern of the passive element region; And And dry-etching a predetermined thickness of the first cladding layer, the core layer, and the compound substrate in the form of a mask pattern of the passive element region, thereby forming an active element waveguide. The method of claim 1, The mask pattern may be formed of a material having a different etching selectivity from the first or second cladding layer. The method of claim 2, The first and second passivation layers may be formed of a material having a different etching selectivity from the mask pattern. The method of claim 3, wherein And the first and second protective films are formed of a photoresist film. The method of claim 3, wherein The first and second passivation layers are formed of the same insulating layer as the mask pattern, and have a thickness smaller than that of the mask pattern. The method of claim 1, And after the forming of the active device waveguide, removing the second passivation layer and the mask pattern.