KR100422581B1 - Delay Locked Loop - Google Patents

Abstract

The present invention is to provide a delay lock loop having a low phase change of the phase-locked clock even in the environment of voltage, temperature, etc. in the memory device, the present invention is to actually receive the internal clock until the data is output A delay model for monitoring the delay time of the circuit; A delay line receiving the external clock and delaying the external clock for a predetermined time; A shift register for adjusting a delay time of the delay line; A reference clock is applied to the external clock and a comparison clock output from the delay model is input to output a phase locking signal when the phase difference between the reference clock and the comparison clock is substantially the same, and output a phase decrement signal when the reference clock is different. Phase comparator; And store the phase shift signal using the external clock as an operation clock, shift the phase of the comparison clock according to the stored phase ramp signal, and output the result to the phase comparator. A delay locked loop including a fine delay adjuster for controlling the shift register by comparing the phase deceleration signal output from the phase comparator with the stored phase deceleration signal in an operation clock is provided.

Description

Delay Locked Loop

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay locked loop used in a synchronous semiconductor device, and more particularly to a delay locked loop which prevents a phase locked clock from changing unnecessarily due to noise.

In general, a synchronous semiconductor device employs a clock buffer that receives a system clock supplied from the outside to generate a clock required in a chip in order to perform a high speed operation. By employing such a clock buffer, a phase difference inevitably occurs in each device in the chip that receives the output of the clock buffer.

Due to this phase difference, the operation inside the chip is always delayed by a predetermined phase difference when the external clock is applied. Therefore, there is a need for a circuit that serves to generate an internal clock having the same output phase as the clock supplied from the outside. The circuit used at this time is a delay locked loop.

Hereinafter, a delay lock loop according to the related art will be described with reference to the accompanying drawings.

1 is a view showing a conventional delay lock loop.

Referring to FIG. 1, the delay lock loop may include a clock buffer 10 receiving an external clock CLK, a first delay line 11 receiving an output of the clock buffer 10, and a first delay. The clock driver 13 receives the output of the line 11 and outputs the internal clock CLK_DLL synchronized with the external clock CLK, and divides the output of the clock buffer 10 to the second delay line 12. A clock divider 17 for outputting to the phase comparator 15, a second delay line 12 for receiving and delaying the output of the clock divider 17, and an output of the second delay line 12 as inputs. A delay model 14 for receiving and monitoring the delay time, a phase comparator 15 for receiving the output of the delay model 14 and the output of the clock divider 18 and comparing the phases, and a phase; A shift register (shi) that receives the output of the comparator 15 and adjusts the delay time of the first delay line 11 and the second delay line 12 as its output. ft register).

FIG. 2 is a view showing waveforms when the phase locked loop of FIG. 1 is phase locked. Hereinafter, an operation of a conventional delay lock loop will be described with reference to FIGS. 1 and 2.

The external clock CLK is buffered in the clock buffer 10, divided by the clock divider 18, and then input to the second delay line 12 to generate a delay clock in which a predetermined time is delayed, and the delay model 14. The delay time is monitored at. In general, the delay model 14 is designed by monitoring the delay time of the delay path generated by the internal clock through the external clock such as the clock buffer 10 and the clock driver 13.

On the other hand, the signal output from the delay model 14 and the signal output from the clock divider 18 is input to the phase comparator 15, the comparison result is input to the shift controller 16 to the first delay line 11 And delay time of the second delay line (12). Thereafter, the above process is repeated until the signal output from the delay model 14 input to the phase comparator 15 and the signal output from the clock divider 18 are phase locked, and the clock driver after phase locking is performed. The internal clock output from 13) becomes the clock synchronized with the external clock.

FIG. 2 is a view showing waveforms when the phase locked loop of FIG. 1 is phase locked.

Referring to FIG. 2, the phase-locking operation is described in detail. The phase comparator 15 includes a signal A output to the clock divider 17, an output signal B of the delay model 14, and a delay model 14. The output signal B is inverted by the unit delay time of the delay lines 11 and 12 to compare the rising edges of the delayed signal / B to detect the locking. That is, the rising edge of the signal A output to the clock divider 17 is delayed by the unit delay time of the output signal B of the delay model 14 and the delay lines 1 and 12 of the signal / B. If it is between the rising edges, the phase comparator 17 senses that it is phase locked.

In the cases (1) and (2) shown in FIG. 2, the phase locking is not yet performed, and (3), the rising edge of the signal A output to the clock divider 17 is the output of the delay model 14. This is the case where it is detected as being phase locked because it is between the signal B and the rising ash of the signal / B delayed by the unit delay time of the delay lines 11 and 12.

On the other hand, the phase-locked clock output from the delay locked loop is used during a read operation of the memory device, which consumes a lot of current during the read operation. As a result, the internal operation voltage of the delay lock loop is lowered, and thus the delay of the delay lines 11 and 12 is increased, thereby changing the phase of the signal B input to the phase comparator 15. The degree to which the phase of the signal B input to the phase comparator 15 changes is as small as the unit delay time of the delay lines 11 and 12, but may be changed by more delay time depending on the magnitude of the voltage being changed. have.

At this time, the delay lock loop performs the phase lock operation again. In this case, an additional delay time occurs until the phase lock occurs, and the current consumption increases. In addition, when the phase locked state is changed due to temperature change while the delay lock loop is phase locked, the phase lock operation is performed again, which consumes a lot of time and current. Therefore, it is wasteful in terms of time and current to execute the phase locking operation every time the phase locking state is released due to a temporary voltage decrease (or temperature change) or the like.

This results in a problem that the data access (tAC) time of the semiconductor device is increased.

It is an object of the present invention to provide a delayed fixed loop insensitive to changes in the environment such as voltage and temperature in a semiconductor device.

1 is a view showing a conventional delayed fixed loop.

FIG. 2 shows waveforms when the phase locked loop of FIG. 1 is phase locked. FIG.

Figure 3 shows a delayed fixed loop according to a preferred embodiment of the present invention.

4A and 4B show the microdelay controller of FIG.

FIG. 5 is a state transition diagram showing an operating state of the fine delay controller of FIG.

* Explanation of symbols for main parts of the drawings

100: fine delay adjuster

200: delay model

300: phase comparator

400: shift register

500: clock divide

600: second delay line

700: first delay line

800: clock buffer

900: Clock Driver

The present invention for achieving the above object is a delay model for monitoring the delay time of the actual internal circuit until the data is output by receiving the external clock; A delay line receiving the external clock and delaying the external clock for a predetermined time; A shift register for adjusting a delay time of the delay line; A reference clock is applied to the external clock and a comparison clock output from the delay model is input to output a phase locking signal when the phase difference between the reference clock and the comparison clock is substantially the same, and output a phase decrement signal when the reference clock is different. Phase comparator; And store the phase shift signal using the external clock as an operation clock, shift the phase of the comparison clock according to the stored phase ramp signal, and output the result to the phase comparator. A delay locked loop including a fine delay adjuster for controlling the shift register by comparing the phase deceleration signal output from the phase comparator with the stored phase deceleration signal in an operation clock is provided.

The present invention is a phase comparator even when the phase of the phase locked clock changes due to noise and a large current consumption in a state where the delay lock loop is phase locked (for example, a phase change due to a delay time change of a delay line). The present invention relates to a delay locked loop in which phase comparison is performed by using a fine delay controller without operating a signal, and the phase lock operation is performed again by a phase comparator when the clock phase is changed in the same direction in the next clock. .

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

3 is a diagram illustrating a delay locked loop according to a preferred embodiment of the present invention.

Referring to FIG. 3, the delay lock loop includes a clock buffer 800 that receives an external clock CLK, a first delay line 700 that receives an output of the clock buffer 800, and a first delay. The clock driver 900 receives the output of the line 700 and outputs the internal clock CLK_DLL synchronized with the external clock CLK, and divides the output of the clock buffer 800 to the second delay line 600. A clock divider 500 that outputs to the phase comparator 300, a second delay line 600 that receives and delays the output of the clock divider 500, and an output of the second delay line 600 as an input. A delay model 200 for receiving and monitoring a delay time, a phase comparator 300 for receiving the output of the delay model 200 and the output of the clock divider 500 and comparing the phases, and a phase comparator 300. A shift register for receiving the output of and adjusting the delay time of the first delay line 700 and the second delay line 600 to the output (s) hift register 400 and a phase locking signal (lock) output from the phase comparator are input to finely adjust the delay time of the signal (cmp_in) output from the delay model 200 to output to the phase comparator 300 It is composed of a delay fine adjuster (100).

4A is a diagram illustrating the fine delay adjustment unit of FIG. 3.

Referring to FIG. 4A, the fine delay adjustment unit receives the information on the phase locking change from the phase comparator 300 to generate the first and second control signals cap1 and cap2 and the control unit. Phase adjustment output unit 120 for outputting information signals (Shift_right, Shift_left) relating to the phase adjustment to the shift register 400 in accordance with the output of the signal generator 110, and the phase is fine according to the first and second control signals The fine delay output unit 130 outputs the adjusted signal to the phase comparator.

The control signal generator 110 locks the delay increase signal Add_delay and the delay decrease signal Sub_delay and the second flip-flop 112 inputted from the phase comparator 300 after the phase lock is performed by the phase comparator. To receive and output the three-input first NOR gate NOR1, the inverted delay reduction signal Sub_delay input from the phase comparator, and the positive output Q of the first and second flip-flops 111. Two inputs for receiving the third input second NOR gate NOR2 and the output signals of the first NOR gate NOR1 and the second NOR gate NOR2 and outputting the input signals D of the first flip-flop 111. The first NAND gate NAND1 and the phase locking signal lock output from the phase comparator are input as the reset signal, and the clock signal Div_clk output from the clock divider 500 is input as the input clock clk. The output signal of the NAND gate NAND1 is input as the data signal D, and the first control signal cap1 is output with the positive output Q. The first flip-flop 111 outputting the high sub output QB to the phase adjusting output unit 120, the delay increase signal Add_delay, the delay decrease signal Sub_delay, and the first input from the phase comparator 300. The third input third NOR gate NOR3 that receives and outputs the sub output QB of the flip-flop 112, the inverted delay increase signal Add_delay and the first and second flip-flops 111 input from the phase comparator. The second flip-flop 112 receives the third input fourth NOR gate NOR4 and the output signals of the third NOR3 NOR3 and the fourth NOR gate NOR4 to receive and output the positive output Q of FIG. The second input NAND gate NAND2 output as the input signal D and the phase locking signal lock output from the phase comparator are received as a reset signal and the clock signal Div_clk is output from the clock divider 500. Is inputted to the input clock clk, the output signal of the second NAND gate NAND2 is inputted to the data signal D, and the positive output Q is received as the second north gate. A second flip-flop 112 output to the NOR2 and the NOR gate NOR4 and an inverted delay reduction signal Sub_delay input from the positive output Q and the phase comparator 300 of the first flip-flop 111. ), The second input third NAND gate N3 receives and outputs the inverted delay increase signal Add_delay and the inverted delay decrease signal Sub_delay, which are input from the phase comparator, and the sub-output of the first flip-flop 111. A third input fifth NOR gate NOR5 that receives and outputs QB and an output of the third NAND gate NAND3 and the fifth NOR gate NOR5, and outputs a second control signal cap2. It consists of 4 NAND gates.

The phase adjusting output unit 120 receives the sub-output QB of the second flip-flop 112 and the inverted delay reduction signal Sub_delay and outputs the shift information signal Shift_right to the shift register 400. The first gate outputs the shift information signal Shift_left to the shift register 400 by receiving the NOR gate NOR6, the sub output QB of the first flip-flop 111, and the inverted delayed delay increase signal Add_delay. It consists of 7 NOR gates (NOR7). The shift register information signals Shift_right and Shift_left are control signals for adjusting delay times of the sheet registers.

On the other hand, the fine delay output unit 130 is the first and second transistors (MN1, MN2) and the first and second transistors that are turned on and off according to the first and second control signals (cap, 1, cap2) input to the gate, First and second capacitors C1 and C2 adjust fine delay times of the phase comparison signal cmp_in output from the delay model 200 according to on-off of the transistors MN1 and MN2. do. The capacitance of the first and second capacitors C1 and C2 is configured to be less than the unit delay time of the first and second delay lines 600 and 700.

4B is a circuit diagram illustrating the flip-flops 111 and 112 of FIG. 4A.

Referring to FIG. 4B, the flip-flop of the first inverter I1 receives the data signal D and inverts the clock signal clk and the inverted signal clkb. A first transmission gate TG1 connecting the output to the node N1, a second inverter I2 inverting the signal of the node N1 and outputting the signal to the node N2, a reset signal and a node ( The second input fourth NAND gate NAND4 which receives the signal of N2) and outputs it to the second transfer gate TG2, and the fourth NAND gate NAND4 according to the clock signal clk and its inverted signal clkb. A second transfer gate TG2 connecting the output to the node N1 and a third transfer gate TG3 connecting the node N2 and the node N3 according to the clock signal clk and its inverted signal clkb. ), A second input fifth NAND gate NAND5 that receives the reset signal and the signal of the node N2 and outputs the signal to the node N4, and a third inverter I3 that inverts and outputs the output of the node N4. Wow, clock scene The fourth transfer gate TG2 connecting the output of the third inverter I3 to the node N3 and the output of the fifth NAND gate NAND5 are inverted according to the clk and the inverted signal clkb. 4th inverter I4 which outputs to output Q is comprised. The flip-flop sub-output QB outputs the signal of the node N4.

3 to 4, the operation of the delay lock loop according to the present invention will be described.

The phase lock operation of the delay locked loop is as described above, and when the phase lock is performed, the fine delay adjuster 100 is operated by a phase locking signal (lock) output from the phase comparator 300. After the phase-locked clock changes due to noise or a large current consumption, the phase comparator 300 outputs the delay increase signal Add_delay and the delay decrease signal Sub_delay to the fine delay controller 100 according to the clock change state. .

In the conventional delay lock loop, the delay time of the delay line is changed according to the delay increase signal Add_delay and the delay decrease signal Sub_delay which are output to the phase comparator. However, in the present invention, the phase locking operation is not performed immediately, but the fine delay controller 100 stores the output (Add_delay, Sub_delay) state of the phase comparator and checks the output of the phase comparator (Add_delay, Sub_delay) again at the next clock. When the phase difference of the clock is detected in the same state, only the delay time of the first and second delay lines is adjusted through the shift register.

By doing so, the shift register 400 and the first and second delay lines 600 and 700 are unnecessarily operated for the instantaneous movement of the phase clock. Here, the fine delay adjuster 100 is configured to output the first and second control signals according to the clock Div_clk output to the clock divider 500.

5 is a state diagram showing an operating state of the fine delay adjuster 100. Hereinafter, with reference to Figure 5, it will be described in detail according to the operating state of the fine delay adjuster.

When the phase lock signal (lock) is first outputted and the phase lock signal (lock) is output, the fine delay adjuster is in the basic state SO, and the first and second control signals cap1 and cap2 are low and high, respectively. Then, the phase of the output signal cmp_in of the delay model 200 input through the clock divider output signal cmp_ref and the fine delay adjuster 100 is input due to a change in operating voltage. If there is a difference, the delay decrease signal Sub_delay or the delay increase signal Add_delay is output to the fine delay adjuster 100 according to the state.

At this time, if the delay increase signal Add_delay is output (A0), the state of the fine delay adjuster becomes the delay add state S1. At this time, the first and second control signals cap1 and cap2 are output high, Accordingly, both of the first and second transistors MN1 and MN2 are turned on and the signal cmp_in output from the delay model 200 is increased in delay and output to the phase comparator 300.

Subsequently, when the next clock signal Div_clk, the operation voltage and the like are maintained at the original level, and the delay increase signal ADD_delay is no longer output from the phase comparator 300, no signal is output to the shift register 400. Without input, the delay fine adjuster 100 is set back to the basic state S0 (A1).

However, if two input signals cmp_in and cmp_ref of the phase comparator continue to be out of the phase locking state, and the delay increase signal Add_delay is output from the phase comparator 300 again, the phase shift information is output to the shift register 400 at this time. Outputs the signal Shift_right to perform phase locking again. (A2)

On the other hand, in the state in which the delay lock loop performs the phase locking operation and the phase lock signal is output, the two input signals of the phase comparator are out of phase lock state due to the voltage fluctuation and the like, and the delay is reduced to the fine delay controller 100. When the signal Sub_delay is output (B0), the state of the fine delay adjuster 100 at this time is changed from the basic state S0 to the delay reduction state S2. At this time, the first and second control signals cap1 and cap2 ) Is outputted low, and accordingly, the first and second transistors MN1 and MN2 are both turned off and the signal cmp_in output from the delay model 200 is reduced in delay time to the phase comparator 300. Is output.

Subsequently, when the delay decrease signal Sub_delay is no longer output from the phase comparator 300 at the next clock signal Div_clk, no delay is input to the shift register 400, and the delay fine regulator 100 is returned to the basic state S0. (B1). However, when the delay reduction signal Sub_delay is output from the phase comparator 300, the phase shifting information signal Shift_left is output to the shift register 400 to perform the phase locking operation again (B2).

In conclusion, when the delay lock loop tries to get out of the phase lock state after the phase lock state, the phase lock operation is not performed again immediately, but the information of the phase lock state is stored in the micro delay controller first, and then the phase comparator By comparing the output with the stored information, if the phase lock state continues to be out of phase, then the phase lock operation is performed. This operation makes it possible to make the change of the phase locked clock of the delay locked loop insensitive to the change of the voltage and to reduce the current consumption.

This makes it possible to shift the position of the clock outputted from the delay lock loop less during read operations of memory devices with a large voltage change, thereby reducing the variation of the output data, thereby reducing the memory access time (tAC). ) Can be improved.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

When the delay locked loop is implemented according to the present invention, it is possible to improve the data access (tAC) time by reducing the variation of the data output from the semiconductor device.

Claims (5)

A delay model for monitoring an actual internal circuit delay time until an external clock is input and data is output; A delay line receiving the external clock and delaying the external clock for a predetermined time; A shift register for adjusting a delay time of the delay line; A reference clock is applied to the external clock and a comparison clock output from the delay model is input to output a phase locking signal when the phase difference between the reference clock and the comparison clock is substantially the same, and output a phase decrement signal when the reference clock is different. Phase comparator; And It is enabled according to the phase locking signal and stores the phase decrement signal using the external clock as an operation clock, and shifts the phase of the comparison clock according to the stored phase decrement signal to output to the phase comparator. A fine delay adjuster for controlling the shift register by comparing the phase deceleration signal output from the phase comparator with the stored phase deceleration signal in a clock. Delay fixed loop having a. The method of claim 1, The fine delay adjuster, A control signal generator which receives the phase shift signal from the phase comparator and generates a first control signal for controlling the phase increase of the comparison clock and a second control signal for controlling the phase reduction of the comparison clock; A fine delay output unit configured to increase or decrease a phase of the comparison clock according to the first and second control signals; And a phase adjusting output unit configured to control the shift register when the stored phase decrease signal and the increase / decrease direction of the comparison clock coincide with each other by receiving the phase decrease signal output from the phase comparator at a next clock of the operation clock. Delayed fixed loop characterized by. The method of claim 2, The fine delay output unit, A first capacitor; A first switch connecting the first capacitor to a line through which the comparison clock passes so as to delay the phase comparison clock for a predetermined time according to the first control signal; A second capacitor; And And a second switch that insulates the second capacitor from the line through which the comparison clock passes so as to advance the phase comparison clock according to the second control signal for a predetermined time. The method of claim 3, wherein And the first and second capacitors have a delay value less than the unit delay time of the delay line. The method of claim 3, wherein The first and the second capacitor is a delay locked loop, characterized in that using the MOS transistor.