KR100857873B1 - Semiconductor memory device and the method for operating the same - Google Patents

Abstract

A semiconductor memory device and a method for operating the same are provided to control an operation mode properly according to an operation frequency of a delay locked loop. A phase comparator(800) compares phase difference between a reference clock and a feedback clock. A delay part controls a delay value of the reference clock in correspondence to the result of the phase comparator, and controls a unit delay according to an operation mode outputted from the phase comparator. A clock period sensing part(1000) controls the operation mode of the phase comparator by sensing the period of the reference clock.

Description

Semiconductor memory device and its driving method {SEMICONDUCTOR MEMORY DEVICE AND THE METHOD FOR OPERATING THE SAME}

1 is a block diagram of a semiconductor memory device.

2 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: clock buffer unit 200A: buffer control unit

200B: DLL operation control unit 200C: control clock generation unit

300: delay line control unit 400: delay line

500: fine delay unit 600: clock driver

700: mode control unit 800: phase comparator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a delay locked loop (DLL) circuit of a semiconductor memory device.

In a system having a plurality of semiconductor devices operating various functions, the semiconductor memory device is a device for storing data. The semiconductor memory device outputs data corresponding to an address input from a data processing device, for example, a central processing unit, to a data requesting device, or transmits data transferred from the data processing device to a data input device in correspondence with the address inputted with the data. Store in the unit cell of the device.

As the operating speed of a system increases, the data input / output speed required of the semiconductor memory device in the data processing apparatus included in the system also increases. However, until recently, in the process of technology development of semiconductor integrated circuits, the operation speed of the data processing device is getting faster and faster. The data input / output speed of the semiconductor memory device that exchanges data with the data processing device does not depend on the speed of the data processing device. have.

Various types of semiconductor memory devices have been developed to increase the data input / output speed of the semiconductor memory device to a level required by the data processing device. Until recently, the most widely used semiconductor memory device has been proposed a synchronous memory device for outputting data every cycle of a system clock equipped with a data processing device. The synchronous memory device receives a system clock and outputs data to a data processing device in response to a cycle of the input system clock, or receives data from the data processing device every cycle of the system clock. However, even as a synchronous memory device does not match the operation speed of the data processing device, a DDR synchronous memory device has been developed. DDR synchronous memory devices output or receive data at every transition of the system clock. That is, data is input or output in synchronization with the rising and falling transitions of the system clock, respectively.

However, the system clock input to the memory device inevitably arrives at the data output circuit with a delay time by a clock input buffer disposed in the semiconductor memory device, a transmission line for transmitting a clock signal, and the like. Therefore, when the data output circuit outputs data in synchronization with the system clock that has already passed the delay time, the external device receiving the output data of the semiconductor memory device receives data that is not synchronized with the rising and falling edges of the system clock. You will be delivered.

In order to solve this problem, the semiconductor memory device includes a delay lock loop circuit which fixes a delay of a clock signal. The delay locked loop circuit is a circuit for correcting a value delayed by an internal circuit of the memory device until the system clock is input to the memory device and transferred to the data output circuit. The delay locked loop circuit finds a time at which the system clock is delayed by the clock input buffer and the clock signal transmission line of the semiconductor memory device, and delays the system clock in response to the found value to output the data to the data output circuit. That is, the system clock input to the memory device is transmitted to the data output circuit with the delay value fixed by the delay lock loop circuit. The data output circuit outputs data in synchronization with a delayed clock, and externally determines that data is output in synchronization with the system clock.

In the actual operation, at a determined point before the data should be output, the delay lock clock output from the delay lock loop circuit is transferred to the output buffer, and the data is output in synchronization with the delay lock clock. Therefore, the system clock outputs data faster than the delay of the internal circuit of the memory device. By doing so, it appears that data is output from the memory device in synchronization with the rising edge and the falling edge of the system clock input to the memory device. After all, a delay locked loop circuit is a circuit that finds out how much faster data must be output to correct the delay of the system clock inside the memory device.

As technology advances, the frequency of a system clock input to a semiconductor memory device is increasing. Therefore, the frequency of the delay locked clock output by the delay lock operation in the delay lock loop circuit is also increasing. The delay locked loop circuit operating at high frequency operates in the fast mode and the normal mode to effectively perform the delay locked operation. In the fast mode, the delay adjustment unit is made larger than the normal mode in the delay lock operation.

However, when the frequency of the clock to be delayed is too high, it may be higher than the delay value unit for delaying the fastening in fast mode, and thus the delay lock operation may not be performed at all.

The present invention is characterized by including a delay locked loop circuit capable of appropriately controlling the operation mode according to the operating frequency of the delay locked loop circuit.

The present invention includes a phase comparator for comparing the phase difference between the reference clock and the feedback clock; A delay unit adjusting and outputting a delay value of the reference clock in response to a result of the phase comparator, and controlling a unit delay value delayed according to an operation mode output from the phase comparator; And a clock cycle sensing unit configured to sense a cycle of the reference clock to control an operation mode of the phase comparator.

In addition, the present invention comprises the steps of comparing the phase difference between the reference clock and the feedback clock; Setting an operation mode corresponding to a phase difference between the reference clock and the feedback clock; Varying and outputting a delay value of the reference clock in response to the comparison result, wherein the delay value is changed to a unit delay value corresponding to the operation mode; Detecting a period of the reference clock; And controlling the magnitude of the unit delay value according to the sensed period.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a block diagram of a semiconductor memory device.

Referring to FIG. 1, the semiconductor memory device includes a clock buffer unit 10, a buffer control unit 20A, a DLL operation control unit 20B, a control clock generation unit 20C, a delay line control unit 30, and a delay line. 40, a fine delay unit 50, a clock driver 60, a delay model 70, a phase comparator 80, and a mode control unit 90 are provided.

The clock buffer unit 10 receives the system clocks CLK and CLKB and outputs a reference clock RCKT2. The buffer controller 20A controls the activation of the clock buffer unit 10. The delay line 30 receives the reference clock RCKT2 and controls the delay line 40 according to the control of the mode controller 90. The delay line 40 adjusts and outputs a delay value of the reference clock RCKT2 under the control of the delay line controller 30. The DLL operation control unit 20B controls the activation of the delay line control unit 30 and controls the activation of the control clock generation unit 20C. The control clock generation unit 20C receives the reference clock RCKT2 and generates the control clocks P1 and P2. The control clocks P1 and P2 are clocks divided by the reference clocks RCKT2 and have different periods. The control clocks P1 and P2 are clocks for determining the reference time point of the update when the delay lock value of the delay lock loop circuit is adjusted. The delay line 30 is provided with a plurality of unit delays in the form of a chain, and the number of unit delays used according to the control of the delay line control unit 30 is determined.

The fine delay unit 50 adjusts and outputs a fine delay value of the clock output from the delay line 40. The clock driver 60 improves the driving capability of the clock output from the fine delay unit 50 to generate delayed clocks RCKDLL and RCKDLL. The delay model 70 outputs a feedback clock FBCLK by delaying the clock output from the fine delay unit 50 to a modeled value. The phase comparator 80 compares the phases of the reference clock RCKT2 and the feedback clock FBCLK. The mode controller 70 controls the delay line controller 30 according to the comparison result of the phase comparator 80.

When the phases of the two clocks RCKT2 and FBCLK input to the phase comparator 80 become equal, the mode controller 90 and the delay line controller 30 delay the delay lines 40 and the fine delay unit 50. Do not adjust the delay value. Therefore, the delayed values of the delay line 40 and the fine delay unit 50 are fixed, and at this time, the delayed fixed clocks RCKDLL and FCK DLL output from the clock driver 60 are stored in the data output circuit of the semiconductor memory device. Used to output data.

The phase comparator 80 divides the delay lock operation into three modes of fast mode (FAST) and normal mode (COARSE) fine adjustment mode (FINE) according to the phase difference between the two clocks RCKT2 and FBCLK. To control. In the fast mode, the phase difference between the two clocks RCKT2 and FBCLK is relatively large. In the fast mode, two or more unit delays of the delay line 40 are changed to adjust the delay value. When the phase difference between the two clocks RCKT2 and FBCLK is relatively small, the unit delay included in the delay line 40 is changed one by one in order to adjust the delay value in the normal mode. The fine delay mode is a mode in which a delay value of a clock that is delayed and fixed by the fine delay unit 50 is adjusted in a state in which delay adjustment of the delay line 40 is completed. The adjustment change width delayed by the fine delay unit 50 is smaller than the delay value of one unit delay included in the delay line 40.

In recent years, the frequency of the system clock input to the semiconductor memory device is increasing. If the system clock cycle (tCK) is DDR3, use from 1.25ns to 2.5ns. In this case, 1/2 tCK of the system clock is 0.75 to 1.25 ns. If the delay of the unit delay included in the delay line 40 is 200 ps, the delay value delayed by the unit delay of the two stages is 400 ps. When the delay value of the unit delay is increased to about 350 ps, the unit delay of the second stage is 700 ps. In this case, if the delay lock operation is performed in the fast mode using the unit delay of two stages, the delay adjustment value at one time is almost equal to 1/2 tCK, so that the delay lock operation cannot be achieved. In this case, it is necessary to control not to operate in the fast mode.

The present invention proposes a semiconductor memory device having a delay locked loop circuit capable of sensing tCK and operating in a fast mode and a normal mode appropriately. The delay locked loop circuit according to the present invention can selectively turn on / off the fast mode among the three operations of the fast, normal mode, and fine adjustment mode using the tCK detector when operating at a high frequency.

2 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 2, the semiconductor memory device according to the present embodiment includes a clock buffer unit 100, a buffer controller 200A, a DLL operation controller 200B, a control clock generator 200C, and a delay line controller ( 300, a delay line 400, a fine delay unit 500, a clock driver 600, a delay model 700, a phase comparator 800, a mode control unit 900, and a clock cycle detection unit 1000. do. A circuit block of the same name as the circuit block shown in FIG. 1 among the circuit blocks shown in FIG. 2 performs substantially the same operation.

A characteristic of the semiconductor memory device according to the present embodiment is that the clock cycle detector 1000 for controlling the phase comparator is provided. The clock period detector 1000 detects the period of the reference clock RCKT2 and controls whether the phase comparator 800 operates in the fast mode. When the clock period detecting unit 1000 detects that the period of the reference clock RCKT2 is smaller than the predetermined width, the phase comparator 800 does not operate in the fast mode but operates only in the normal mode and the fine adjustment mode. The predetermined width may be appropriately determined according to the operating state of the semiconductor memory device, and in particular, the predetermined width may be determined according to the delay value of the unit delay included in the delay line.

Therefore, even when the semiconductor memory device operates at a high frequency such as DDR3, the delay lock loop circuit stably performs the delay lock operation so that the semiconductor memory device can output data at a reliable timing.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

Although the control of the fast mode is illustrated in the present embodiment, the present invention can be applied to the control of another operation mode.

According to the present invention, even when operating at a high frequency, the delay lock operation is stable, and data can be output at a predetermined timing.

Claims (7)

A phase comparator for comparing the phase difference between the reference clock and the feedback clock; A delay unit adjusting and outputting a delay value of the reference clock in response to a result of the phase comparator, and controlling a unit delay value delayed according to an operation mode output from the phase comparator; And Clock period sensing unit for controlling the operation mode of the phase comparator by sensing the period of the reference clock A semiconductor memory device having a. The method of claim 1, The operation mode is And a normal operation mode in which a variation of the delay value delayed by the delay unit is changed by a unit delay value, and a fast mode in which the delay value is changed by N times the unit delay value. . The method of claim 2, The clock cycle detection unit And if the period of the reference clock becomes smaller than a predetermined period, controlling the phase comparator so that the phase comparator does not operate in the fast mode. The method of claim 3, wherein The scheduled cycle is And the unit delay provided in the delay unit is determined in correspondence with a delay value that can delay the unit delay. Comparing the phase difference between the reference clock and the feedback clock; Setting an operation mode corresponding to a phase difference between the reference clock and the feedback clock; Varying and outputting a delay value of the reference clock in response to the comparison result, wherein the delay value is changed to a unit delay value corresponding to the operation mode; Detecting a period of the reference clock; And Controlling the magnitude of the unit delay value according to the sensed period Method of driving a semiconductor memory device comprising a. The method of claim 5, wherein The operation mode is And a normal mode in which the delayed unit delay value is changed by a delay value of a unit delay, and a fast mode in which the delay value is changed by N times the unit delay value. . The method of claim 6, The step of controlling the magnitude of the unit delay value according to the detected period And if the period of the reference clock becomes smaller than a predetermined period, controlling the unit delay value so as not to operate in the fast mode.

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