KR100417039B1 - A rubber band logic circuit for evaluating a logic input in response to a reference output and an evaluation method therefor - Google Patents

Abstract

The present invention provides a method of controlling a clock terminal for connecting a first clock terminal for connection with a first clock delayed from a reference clock by a first frequency dependent delay period and a second clock terminal for connecting a second clock delayed from a reference clock by a second frequency dependent delay period Lt; RTI ID = 0.0 > a < / RTI > The circuit further includes a first circuit stage including a pulse generating circuit coupled to the first clock terminal and the second clock terminal. In one embodiment, the first circuit stage comprises an output terminal, an evaluation device coupled to the output terminal, and a precharge device coupled to the pulse generation circuit and the output terminal, a third clock terminal, and a first logic level, a third frequency dependent delay period And a third clock delayed from the reference clock.

Description

A rubber band logic circuit for evaluating a logic input in response to a reference output and an evaluation method therefor

The present invention relates to a method and apparatus for improving CMOS circuits. More particularly, the present invention relates to a new type of CMOS circuit that advantageously precharges output nodes and evaluates logic inputs using pre-charge and evaluates delayed pulses between each other in a frequency dependent manner.

In a CMOS dynamic logic circuit, the output node is pre-charged using a pre-charge clock during the pre-charge cycle of the circuit. Logic input to the logic circuit after pre-charging is evaluated using the evaluation clock during the evaluation cycle of the circuit. To perform the precharge and evaluation tasks, the CMOS dynamic logic circuit generally pre-charges and evaluates the circuit steps using two separate delayed clocks. In dynamic logic circuits, the evaluation and pre-charge clocks are considered as fixed delayed clock signals. Because they are delayed from each other by a fixed delay period.

In order to avoid the presence of an undesired discharge path between V _dd and V _ss through a logic circuit that can cause a crowbar condition, that is, a logic evaluation error and an increase in power consumption, the dynamic logic circuit terminates the pre-charge cycle prior to the evaluation cycle It is important. In other words, it is important that the evaluation and pre-charge clocks are timed relative to each other so that there is an adequate safety margin between the time pre-charging and evaluation are to begin.

In general, the use of two clocks separated from each other by a predetermined delay period to precharge and evaluate the dynamic logic circuit is satisfactory if the delay period is accurately determined during design. In order to determine the appropriate delay for a given design, the circuit designer must roughly calculate the delay value determined in light of the parameters of the other circuit for a given operating clock speed. The logic circuit is then simulated several times using different delay values. The optimal settled delay time value for a given operating speed is to produce the correct evaluation results while minimizing the safety margin required between the circuit's pre-charge and evaluation cycles. Once the correct delay period is determined, a fixed delay element, such as an inverter, latch, or the like, is assembled to generate an appropriate precharge and evaluation clock for its operating frequency.

However, the use of multiple fixed delay clocks to control evaluation and precharge has many drawbacks. First, the determination of the safety margin between clocks and the optimal fixed delay value is often a time-consuming process in order to ensure correct evaluation without violating unfair performance practices. Moreover, these fixed delay periods can not be easily varied to accommodate changes in the operating speed of the circuit under any circumstances or to optimize performance, even if implemented through physical circuit elements, without undue design effort.

Due to improvements in design techniques or changes in system requirements, if the dynamic logic circuit needs to operate at a clock frequency other than the calculated operating frequency, a fixed delay value is determined again, Make sure that the evaluation clocks are timed with respect to each other and that there is still an adequate safety margin between the circuit's pre-charge and evaluation cycles. If a delay value needs to be changed for proper performance, a new element is physically assembled into the logic circuit so that the new delay period is calculated and the circuit is re-simulated and the function of the logic circuit itself is not changed, . In other words, if a fixed delay is used to generate the precharge and evaluation clocks, the circuit designer must once again calculate the optimal delay value and physically change some of the logic circuitry, even if the logic circuit operating speed changes.

In addition, it is difficult to implement a circuit that can evaluate multiple data cycles per system clock cycle using a fixed delayed clock. This difficulty arises as a result of the inherent rigidity of the generation and utilization of a fixed delay clock and the tendency of the fixed delay clock to become a process change when a fixed delay element is organized.

What is needed is an improved CMOS dynamic logic circuit in which precharge is an output node and evaluates the logic inputs using precharge and evaluates delayed clocks in a frequency dependent manner. The improved logic circuit ends the pre-charge cycle prior to the start of the evaluation cycle independent of the operating frequency.

Instead of using a fixed delay element to generate precharge and evaluation clock pulses, the improved logic circuit utilizes multiple clocks that are delayed from each other in a frequency dependent manner to generate precharge and evaluation clocks. Also, since the delay period and margin of the improved circuit are flexible with respect to the operating frequency, the precharge cycle is terminated prior to the start of the evaluation cycle independent of the operating frequency and the improved logic circuit requires a smaller safety margin between the precharge and evaluation cycles . When the required margin is reduced, the improved circuit operates at a higher operating frequency to improve performance. The apparatus and method also allow for more efficient and easier evaluation of multiple data per clock cycle.

The present invention provides a method of controlling a clock terminal for connecting a first clock terminal for connection with a first clock delayed from a reference clock by a first frequency dependent delay period and a second clock terminal for connecting a second clock delayed from a reference clock by a second frequency dependent delay period To a circuit for evaluating a logic input in response to a reference clock. The circuit further includes a first circuit stage of the circuit including a pulse generation circuit coupled to both the first clock terminal and the second clock terminal. In one embodiment, the first stage of the circuit (hereinafter referred to as the 'first circuit stage') is connected to an output terminal, an output terminal and an evaluation device coupled to the pulse generation circuit, and an output terminal, a third clock terminal, Wherein the third clock is delayed from the reference clock by a third frequency dependent delay period.

In yet another embodiment, the present invention relates to a method for improving the performance of a logic circuit and includes providing a precharge pulse to a precharge node of the logic circuit. The method further includes providing a data pulse delayed from the precharge pulse by a frequency dependent delay to the data input node of the logic circuit and precharging the output node of the logic circuit with a precharge pulse. The method includes evaluating a logic input to a logic circuit with a data pulse that will assure the logic state of the output node using an evaluation device of the logic circuit.

In yet another embodiment, the invention provides a method comprising: providing a first clock terminal having a first clock delayed from a reference clock by a first frequency dependent delay period; providing a first clock terminal having a second clock delayed from the reference clock by a second frequency dependent delay period; Lt; RTI ID = 0.0 > 2 < / RTI > clock terminal. In this embodiment, the method includes connecting a pulse generation circuit to a first clock negative and a second clock terminal, providing an output terminal, connecting the first stage evaluation device to the output terminal and the pulse generation circuit, And connecting a stage pre-charging device to a third clock terminal and an output terminal and a first logic level. The third clock terminal has a third clock and the third clock is delayed from the reference clock by a third frequency dependent delay period.

The invention also relates to a circuit comprising a pre-charge pulse activation edge defining a pre-charge pulse width that varies in response to a frequency of a reference clock and a pre-charge node providing a pre-charge pulse having a pre-charge pulse deactivation edge. The circuit further includes a data input node that provides a data pulse active edge defining a data pulse width that varies in response to a frequency of the reference clock and a data pulse having a data pulse deactivation edge during a data valid cycle. The data pulse activation edge is delayed from the precharge pulse deactivation edge by a frequency dependent delay. The circuit also includes a plurality of evaluation devices, wherein the first evaluation device of the plurality of evaluation devices is coupled to a data input node and the second evaluation device comprises a first logic level, an output node coupled to the precharge node and the first evaluation device, Connected to a precharge device coupled to the precharge node and the output node and to a second logic level, the precharge device coupling the output node to a second logic level responsive to the precharge pulse.

An improved dynamic logic circuit is disclosed and described in detail in SN 08 / 397,419 filed on March 1, 1995 by the present inventor and in the patent application "Wave Propagation Logic" (Attorney Docket No. P688 / SUN1P016). In the wave propagation logic circuit, the output node is pre-charged by a pre-charge pulse during a pre-charge cycle of the circuit. The logic input to the logic circuit after pre-charging is evaluated by the evaluation pulse during the evaluation cycle of the circuit. In this patent application, an improved dynamic logic circuit using multiple frequency dependent (rubber band) clocks for precharge and node evaluation is disclosed.

Figure 1 is a circuit used to generate multiple rubber band clocks. The rubber band clock is a clock whose frequency and delay to each other increase and decrease in response to the frequency of the external reference clock. The specific circuit of FIG. 1 is only one way to generate a multiple rubber band clock from an external reference clock and other variations are possible without departing from the spirit of the present invention.

FIG. 1 shows a PLL circuit 201. The PLL circuit 201 includes a phase frequency detector 203, a charge pump 205 and a voltage control oscillator 207 disposed at the front end of the PLL circuit. As is well known in the art of PLL, PLL circuit 201 may include other circuit elements such as regulators, filters, etc., but is omitted in FIG. 1 to simplify the description.

The PLL circuit 201 receives, as an input, an external reference clock signal (EXTCLK) 209 generated from a clock generating circuit such as a correction circuit known in the field of PLL. The PLL circuit 201 includes a plurality of rubber band clocks (CLK1 212, CLK2 218, CLK3 216, CLK4 214, CLK5 213). When these frequencies change, the rubber band clocks (CLK1 212, CLK2 218, CLK3 216, CLK4 214, and CLK5 213) are shifted in phase with respect to each other. In this way, these rubber band clocks are geothermal to each other as much as frequency dependent delays.

The phase frequency detector 203 of the operation when, PLL circuit 201 has an external reference clock signal (EXTCLK, 209) for receiving to an external reference clock signal and the internal reference clock signal the phase and frequency of the _{(EXTCLK, 209) (V fc} , 211). In one embodiment, the internal reference clock signal (V _fc , 211) is connected to some variation, such as a signal (CLK1, 212) or a buffered version of the signal (CLK1, 212). If the external reference clock signal EXTCLK 209 is faster than the internal reference clock signal V _fc 211 the phase frequency detector 203 generates an up signal 220 and supplies the up signal 220 to a charge pump (205). Conversely, if the external reference clock signal (EXTCLK) 209 is slower than the internal reference clock signal (V _fc , 211), then the phase frequency detector 203 generates a down signal 222 and supplies the down signal 222 to the charge pump 205.

The charge pump 205 receives the up signal 220 or the down signal 222 and outputs a controlled voltage VCNTRL 224 in response thereto. If the charge pump 205 receives the up signal 220, the controlled voltage VCNTRL, 224 is high. Conversely, when the charge pump 205 receives the down signal 222, the controlled voltage VCNTRL, 224 is low. The voltage VCNTRL 224 controlled with the dual signals VCNTRL2 and 252 is used to control steps 228, 230, 232, 233 and 234 in which the current of the voltage control oscillator 207 is insufficient.

In FIG. 1, there are five current-deficient steps 228, 230, 232, 233, 234 for generating five rubber band clocks CLK1-CLK5. Generally, the one-step current deprivation step, such as steps 228, 230, 232, 233, 234, utilizes an inverter to modulate the delay. The lack of current step 228 controls the frequency dependent delay of the clocks CLKP2, 242; The current shortage step 230 controls the frequency dependent delay of the clocks CLKP3, 246; The current shortage step 232 controls the frequency dependent delay of the clocks (CLKP4, 246); The step 233 of lacking current controls the frequency dependent delay of the clocks CLKP5, 247; The current shortage step 234 controls the frequency dependent delay of the clocks CLKP1, 248. The first figure shows only five current shortages and five corresponding output rubber band clocks, but it is possible to increase or decrease the number of rubber band clocks by adding or removing one or more current shortage steps.

There is a p-channel device 236 and an n-channel device 226 connected in series with an inverter 238 in a current-deficient step 228 as shown in FIG. The step of lacking current, such as step 228 of FIG. 1, is changed to delay in the step output signal for the step input signal in response to the amount of current flowing through the stepping device. For example, current shortage step 228 may cause clock 228 to be input to step 228 input signal 248 in response to the amount of current flowing through p-channel device 236, inverter 238, and n-channel device 226, The delay of CLKP2 242 is adjusted.

The p-channel device 236 is controlled by a controlled voltage VCNTRL2 (252) which is a double signal of the controlled voltage signal VCNTRL 224. [ If the controlled voltage VCNTRL 224 is large, a fairly large amount of current flows through the device in step 228 which is deficient. As a result, the output capacitance of step 228, which lacks current, including the capacitance of the buffer 254 associated with this step, and the gate current of the device forming the inverter in step 230 where the next current is insufficient, Thereby reducing the delay between the step output signal, the clock (CLKP2, 242) and the phase input signal, the clocks (CLKP1, 248). The clock CLKP2, 242, which is the output of step 228 lacking current, serves as the input signal for step 230 where current is lacking. The lack of current step 230 is controlled by the controlled voltages VCNTRL 224 and VCNTRL2 252 to control the delay of the output signal of step 230 which is shown by the clock signal CLKP2 242 (CLKP3, 244) in FIGURE 1 for the input signal 230 of FIG.

In a similar manner, clocks CLKP3 and 244 are responsive to the controlled voltages (VCNTRL 224, VCNTRL2 252) to produce a clock 232 (CLKP4, 246) for the input signal of step 232, Lt; RTI ID = 0.0 > 232 < / RTI > Similarly, clocks (CLKP4, 246) are responsive to the controlled voltage (VCNTRL 224, VCNTRL2 252) to generate a clock (CCLKP5, 247) for the input signal of step 233 And acts as an input to step 233 of lacking current to adjust the delay of the output signal. Similarly, clocks CLKP5 and 247 are applied to the input signal of step 234 in response to the controlled voltage (VCNTRL 224, VCNTRL2 252) in steps (shown as CLKP1,248 in FIGURE 1) 0.0 > 234 < / RTI > lacking current to adjust the output signal delay of the output signal 234.

The voltage control oscillator 207 receives the clocks CLKP1 and 248 to delay the signal for a frequency dependent period and the delay period comprises a controlled voltage (VCNTRL 224, VCNTRL2 252) that produces one or more rubber band clocks, . A number of step output signals, such as clocks 242, 244, 246, 247, 248, shifted in phase by as much as 216 degrees (1/5 of 360 degrees, 180 degrees due to the inverter used in the implementation of the step lacking current) do.

The rubber band clocks, i. E. Clocks 212,213, 214,216 and 218, are generated from the respective step output signals, i. E. Clocks 242,244,246,247,248, by buffer / driver circuits known in the art. The rubber band clocks 212, 213, 214, 216, and 218 are generated by the PLL circuit 201 from the external reference clock signal 209 and therefore change to their frequencies according to the frequency of the external reference clock signal 209. In Figure 1, each rubber band clock is shifted 216 degrees from each other regardless of the operating frequency.

FIG. 2A shows the frequency dependency between the external reference clock signal 209 and the rubber band clocks CLK1, 212 in a simplified timing diagram. In FIG. 2A, clocks CLK1 and CLK2 correspond to frequencies (F _p , periods T _p ) equal to the frequency (Fref, period Tref) of the external reference clock signal (EXTCLK) 209 . In addition, the clocks (CLK1, 212) precede the external reference clock signal (EXTCLK) 209 by a period, which is shown as a period (Td) in FIG. 2A. The period T _p expands or contracts when the period Tref expands or contracts in response to a change in the frequency of the external reference clock signal EXTCLK 209. The frequency of the clocks CLK1, 212 expands and contracts when the external reference clock signal 209 changes.

Figure 2B shows a simple timing diagram of the frequency dependencies between clocks (CLKP1, 248), rubber band blocks (CLK1, 212), clocks (CLKP2, 242) and rubber band clocks (CLK2, 218). Figure 2B the rubber band clock (CLK1, 212) is in the delay as from the clock (CLKP1,248) delay period (T _b1). The delay period T _b1 represents the delay associated with the buffer 264 and driver 266 circuitry used to generate the rubber band clocks CLK1, 212 from the clocks CLKP1, 248. Typically, this delay is determined by the design of the buffer and driver circuit and is usually kept small and does not vary in response to the frequency of the external reference clock signal 209. Buffer 264 in FIG. 1 may include a single-to-differential converter for converting a single signal to a differential signal. Only signals (CLK2 218, CLK3 216, CLK4 214, CLK5 213) are shown for purposes of illustration, although a differential signal is available.

2B shows the clocks CLKP2, 242 delayed from the clocks CLKP1, 248 by the delay period T _r . The delay period T _r is controlled by step 228 where the current controlled by the controlled voltage VCNTRL 224, VCNTRL2 252 is insufficient. In contrast to the delay period T _b1 , the delay period T _r varies with the frequency of the external reference clock signal 209.

It also shows the rubber band clock (CLK2, 218) is delayed from the clock by (CLKP2, 242) of claim 2B delay period (T _b2) degrees. Similar to the delay period Tb1, the delay period Tb2 represents the delay associated with the buffer and driver circuitry used to generate the rubber band clocks CLK2, 218 from the clocks CLKP2, 242. It is preferable that the delay period T _b1 is equal to the delay period T _b2 . Clock (CLKP2, 242) is because the delay from the clock (CLKP1, 248) by a frequency-dependent delay rubber band clock (CLK2, 218) Also, the rubber band clock (CLK1, 212) by the same frequency dependent delay period (T _r) from Delayed. As the frequency of the external reference clock signal 209 increases, the delay period (T _C2 -T _C1 ) between the two rubber band clocks decreases. Conversely, when the frequency of the external reference clock signal 209 decreases, the delay period (T _C2 -T _C1 ) between the two rubber band clocks increases.

FIG. 3 shows a simplified circuit diagram of a NAND-gate based rubber band logic circuit in accordance with an aspect of the present invention. The circuit of FIG. 3 is a NAND-gate based, since a NAND gate element is used to generate the pulse data signal. However, other gate elements such as NOR, XOR, AND, and OR may be used to derive the gate signal without departing from the spirit of the present invention. The circuit of FIG. 3 includes two circuit stages 80 and 82. At each step, there are evaluation devices 110, 112, 114 as the number of logic inputs, i.e., signals 88, 90, 92. The first circuit stage 80 and the second circuit stage 82 pre-charge each terminal, i. E., Nodes 100,108,122, 128,137, in response to a precharge pulse on the rubber band clock signal NINCLK 286. [ An evaluation data pulse is used to start the evaluation of the first circuit stage 80 when the rubber band clock signals INCLK1 84 and INCLK2 85 enter the evaluation stage and the data signal 88 is valid, Occurs. The output pulse from the first circuit stage 80 is then buffered and propagated to the second circuit stage 82 to begin the evaluation of the second circuit stage 82. In this way, pre-charging and evaluation is done in series like waves between stages of the rubber band logic circuit.

The NAND output 96 of the NAND gate 94 is high when one of the signals INCLK1 (84), INCLK2 (85) or data 88 is low in FIG. The transition of the clock signals INCLK1 and 84 from low to high when the clock signals INCLK2 and 85 are high and the data 88 is high is valid at the NAND gate 94 ' 96).

In one embodiment, the complementary clock signals NINCLK2, 86 at the clock signal INCLK1, 84 transition from high to low simultaneously when the clock signals INCLK1, 84 transition from low to high.

The transition from high to low of the clock signal NINCLK2, 86 turns off the n-channel device 116 and removes the node 100 from ground. The p-channel device 98 pulls the node 100 into the NAND output 96 as it goes down. When the clock (NINCLK2, 86) changes from low to high at the beginning of the pre-charge phase, the node 100 remains in the high state until pulled by the n-channel device 116. The p-channel device 98 and the n-channel device 116 function as dynamic inverters in the circuit of FIG. Although not required, dynamic inverters are preferred due to their advantages in circuit area and speed. The NAND gate 94, the p-channel device 98 and the n-channel device 116 together act as a pulse generation circuit for providing a pulse data signal to the circuitry of Figure 3. The clocks NINCLK2, At the beginning of the phase, going from high to low, inverter 102 drives node 104 high. Node 104 is maintained until the transition of low to high clock (NINCLK2,86) at the beginning of the precharge phase which causes node 104 to go from high to low. The evaluation devices 110, 112, 114 may be used to control the evaluation of the circuit steps 80 connected to the node 100.

The low node 104 turns on the p-channel pre-charge device 106 and connects the external terminal 108 to V _dd . During the low period of the node 100, the n-channel evaluating device 110 is turned off and disconnects the external terminal 108 from V _ss . During this pre-charge period, the output terminal 108 is precharged high through the p-channel pre-charge device 106.

If the data signal 88 is low during the evaluation period, the NAND output 96 will be raised by operation of the NAND gate 94. When the node 96 is high because the data signal 88 is low during the evaluation period, the p-channel device 98 is not turned on and the node 100 stays there. The n-channel estimation device 100 does not conduct during the evaluation phase when the node 100 stays low due to the low data signal 88. Although the inputs 90 and 92 to the n-channel estimators 112 and 114 are high, the output terminal 108 remains pre-charged during this evaluation stage.

Optionally, if data signal 88 and clock signals INCLK1 84 and INCLK2 85 are high then node 96 is low during the evaluation period so that node 100 is on a p- And is pulled high through the device 98. The high state of the node 100 conducts the n-channel evaluation device 110 and pulls the output terminal 108 to V _ss when the inputs 90 and 92 are high at some point during the evaluation phase.

The output terminal 108 goes high again when the clock (NINCLK2, 86) goes high at the beginning of the pre-charge phase. When the clock (NINCLK2, 86) goes high, the node 104 goes low and turns on the p-channel pre-charge device 106. [ For the sake of convenience of explanation, a description of the circuit steps 82 and the remainder of the third degree circuit only when the data signal 88 is high and the inputs 90 and 92 to the n-channel evaluation devices 112 and 114 are high, Is applied. The operation of the third degree circuit when the data signal 88 is low can be grasped from the circuit diagram of FIG.

Node 118 goes from high to low with the operation of inverter 120 when node 104 goes low to high early in the evaluation phase of the clock. Node 118 will remain low until node 104 changes from high to low to cause node 118 to go from low to high. When the output terminal 108 is changed from high to low during the evaluation (i.e., when the data signal 88 and the clock signals INCLK1 84 and INCLK2 85 are high and the n-channel devices 112 and 114 are in the evaluation phase) ) Node 122 goes from low to high due to the operation of p-channel device 124. Node 122 goes low by transitioning from low to high of node 118 at the beginning of the pre- Channel device 117. This is because the high state of node 118 conducts n-channel device 117 to connect node 122 to V _ss and pulls node 122 low. Channel device 117 and n-channel device 117 perform the function of a dynamic inverter / buffer that changes the polarity of the signal on output terminal 108 at the appropriate time.

On the other hand, the high-low transition of node 118 at the beginning of the evaluation phase causes node 127 to go high through the operation of inverter 125. The p-channel precharge device 126 connects the output terminal 128 to V _dd and disconnects the output terminal 128 from V _ss when node 127 was low and node 122 was low prior to the evaluation period Pre-charges the output terminal 128 in a manner similar to the pre-charging of the output terminal 108.

When node NINCLK2 86 propagates through inverters 102, 120 and 125 to node 127, node 127 goes low to turn off p-channel pre-charge device 126. The node 122 goes high and connects the output terminal 128 to V _ss through the n-channel devices 130,132,134,136, with the input to the gates of the n-channel devices 130,132,134, When all are high during the step). Also, when node 127 goes high, node 131 goes low through inverter 133 operation. Channel device 135 is disconnected and node 137 disconnects from V _ss when node 131 goes low. Channel device 138 causes node 137 to go high when output terminal 128 goes low. The output terminal 128 stays low until the node 127 is pulled high by the p-channel pre-charge device 126 when going low. When node 127 goes low, output terminal 128 is connected to V _dd via p-channel pre-charge device 126 and goes high.

Node 137 stays high until node 131 goes low by p-channel device 135 when going high. The transition from high to low of node 137 represents pre-charging to V _ss of the input to circuit steps (not shown) after circuit step 82.

Although this particular circuit shows a pre-charge controlled by the complementary rubber band clock (NINCLK2, 86) of the rubber band clock INCLK2, this is not necessary. Since the rubber band clocks NINCLK2 86 and INCLK 85 are complementary to each other in the third degree circuit, the clocks NINCLK2 and 86 are out of phase with the clocks INCLK2 and 85 by approximately 180 degrees. However, the clock (NINCLK2, 86) may be a rubber band clock generated from a PLL or a rubber band generated from one or more rubber bands. A precharge pulse may be generated that does not cause a race condition where clock NINCLK2 86 may go high after clock INCLK2 is low. It will be apparent to those skilled in the art that the use of signals other than the complementary of clock INCLK2 to control pre-charging provides additional flexibility in terms of timing. For example, it is possible to derive the rising edge of the clock NINCLK2 from the rubber band clock so that the clock NINCLK2 always goes high after the clock INCLK2 goes low. Similarly, it is possible to derive the falling edge of the clock NINCLK2 from the rubber band clock so that the clock NINCLK2 always goes low before the clocks INCLK1, 84 goes high. Since the rubber band clock is used to derive this clock (NINCLK2), the race condition can be avoided regardless of the frequency of the external reference signal.

The evaluation proceeds in a pulsed manner from the first circuit stage 80 to the second circuit stage 82 and to the subsequent circuit stage of the rubber band logic circuit of the present invention. Similarly, pre-charging leads to evaluation in a pulsed manner, resulting in pre-charging in a series fashion. An evaluation clock pulse through a NAND gate, a NOR gate, or the like is used to evaluate the first circuit stage. The result of the first circuit stage evaluation is propagated serially to subsequent circuit stages. The pre-charging of the first circuit stage is also performed through a pre-charge pulse. This pre-charge pulse propagates in series with subsequent circuit steps.

The number of evaluation devices in one step in the circuit of the present invention is equal to the number of logic inputs. The reduction in the number of serial devices relative to the evaluation tree of the domino logic circuit reduces the capacitance load on the clock, instantaneous peak current, Increase propulsion.

The third _stage circuit prevents the presence of a discharge path from V _dd to V _ss to preserve power and prevent error output. There is a discharge path if the p-channel pre-charge device 106 of the circuit stage 80 and the n-channel evaluation device are turned on at the same time. The circuit of FIG. 3 does not allow the occurrence of this condition. This is because the pre-charge is terminated by its own rubber band signal before another rubber band signal starts evaluation.

FIG. 4 shows the relationship between the logic state of the node of the third degree circuit and the rubber band clocks INCLK1 (84), INCLK2 (85), NINCLK2 (86) during evaluation and precharge at a simplified timing. 4 also, the rubber band clock (INCLK1, 84) having a pulse width (W _p) is shown. The rubber band clocks INCLKl and 84 are one of the signals input to the third NAND gate 94 to generate the pulse data signal for evaluating the first circuit stage 80. [ The second signal having a pulse width W _p and input to the NAND gate 94 is a rubber band clock INCLK2, 85. The two signals have the same pulse width (W _p ) since they are derived from the same reference clock signal. Clock (INCLK1, 84) are the clock and the phase is shifted from (INCLK2, 85) precedes by a clock (INCLK2, 85) frequency-dependent delay period (T _fd). The frequency dependent delay period (T _fd ) also changes when the frequency of the reference clock signal (i.e., signal 209 in FIG. 1) changes. 4 shows the rubber band clocks NINCLK2 and 86 generated by the same circuit used to generate the rubber band clocks INCLK1 and INCLK 85, which are mirror images of the rubber band clocks INCLK2 and 85, Respectively.

NAND output 96 stays high when one of signals 84,85,88 is low. Transition from low to high of the clock signals INCLK1 and 84 in combination with the already high clock signals INCLK2 and 85 when the clock signals INCLK1 and 84 go high ) Causes NAND output 96 to go low at edge 350. The NAND output 96 remains low until the clock signal INCLK2,85 goes low at edge 352 and causes the NAND output 96 to go high at edge 354.

The transition from high to low of NAND output 96 at edge 350 causes node 100 to go high at edge 356 through p-channel device 98 in FIG. Node 100 transitions from high to low through n-channel device 116 (FIG. 3) at edge 358 by a low-to-high transition of clock signals NINCLK2,86 at edge 360, NINCLK2, 86 transition at the same time when the clock signal INCLK2, 85 goes high-low transition. The pulses defined by the edges 356 and 358 define the evaluation data pulses used to control the n-channel device 110 to evaluate step 80.

The low-to-high transition of node 100 at edge 356 causes output node 108 to go from pre-charged high to low at edge 360 (provided inputs 90 and 92 are high). The low-to-high transition of clock NINCLK2 86 at edge 360 causes node 104 to go from high to low as shown in FIG. 4 (by inverter 102) The p-channel device 106 connects the output node 108 to V _dd so that it pulls the output node 108 back high at the edge 364. Causes node 108 to go high at edge 364 after going low since clock signal NINCLK2 86 crosses inverter 102 and undergoes a propagation delay before turning on p-channel device 106. [ In contrast, the n-channel device 116 is turned on as soon as the clock signal NINCLK 86 goes high. Thus, the output node 108 is disconnected from V _ss prior to pre-charging to V _dd .

The high-to-low transition of node 108 at edge 360 causes node 122 to go high through p-channel device 124 at edge 366. The high-to-low transition of node 104 causes node 118 to go high at edge 371 causing node 122 to fall low at edge 368. The pulses defined by the edges 366 and 368 are evaluation pulses used in the evaluation step 82 of FIG. If the output node 108 of step 80 does not change from high to low, node 122 will not go high for evaluation. The low-high edge 366 of the evaluation pulse on conductor 122 causes node 128 to go from pre-charged high to low at edge 370 (provided that n-channel evaluation devices 132,134, ).

The high-to-low transition of node 104 causes node 118 to transition from low to high across inverter 120 such that n-channel device 117 at node 368 causes node 122 to fall low And the evaluation pulse is ended. The output node 128 is effectively removed from V _ss when node 122 goes low again at the end of the evaluation pulse. The high-to-high edge 371 on node 118 is moved through inverter 125 to cause node 127 at node 372 to transition from high to low and through p-channel pre-charge device 126 Pre-charges the output node 128. As a result, node 128 goes from low to high, as shown at edge 374.

The transition from high to low of output node 128 during evaluation causes output node 137 to go high at edge 378 due to p-channel device 138. The low-to-high transition of the output node 137 may be used to initiate an evaluation of the further step of the rubber band logic circuit. The high-to-low transition of node 127 at edge 127 causes node 131 to transit low-high across the inverter 133 at edge 376. The low-to-high transition of node 131 turns device 135 on and causes output node 137 to go low at edge 379, causing output node 137 to begin precharging low.

The use of rubber band clocks in dynamic logic circuits simplifies circuit performance optimization. In the known art, delay and margin are precomputed and implemented in an unchangeable manner. In the known circuit, changing the margin between the pre-charge clock and the evaluation clock requires significant resources and cost. Therefore, designers working with known circuits are very conservative in their delays and margins and make mistakes in designing too many margins and delays in the circuit. When this occurs, the circuit does not operate optimally at a given system clock speed. According to one aspect of the present invention, a designer can implement a circuit by estimating optimal delays and margins using a rubber band clock to control pre-charging and evaluation. Once the circuit is assembled, the designer can increase the reference clock (clock 209 in FIGURE 1) to increase or decrease the margin and delay needed to optimize performance. Because of the rubber band nature of the clock, the pre-charge and evaluation pulses can be shifted in phase with each other to prevent the crowbar condition independent of the speed at which the circuit operates.

In some logic systems (eg, microprocessors), two or more data cycles are provided in a system clock. When multiple data can be processed for each system clock, the processing power of a given logic circuit can be effectively doubled without having to increase the speed of the system clock. The timing when there are multiple data valid cycles to evaluate for each system clock poses a challenge to the designer of the CMOS dynamic logic circuit. The pre-charge and evaluate pulses become shorter as the frequency of the pre-charge and evaluate clocks increases to handle more data per system clock cycle. When this happens, it is necessary to reduce the margin between pulses in order to evaluate and pre-charge the data before the time to evaluate the next data.

The reduction in available time for the safety margin and the increase in frequency between the precharge and evaluation cycles make it necessary for the precharge and evaluation pulses to be timed appropriately for each other. The use of multiple rubber band clocks facilitates timing by allowing the precharge clock to shift the phase from the evaluation clock by a given percentage for each clock period, regardless of the operating frequency. In addition, both the pre-charge and evaluation pulse clocks are derived from the external reference clock, thus minimizing both clocks to maximize performance. Unlike known circuits in which the delay between the clocks that increase the delay between the clock and the corresponding safety margin is fixed, if the frequency of the external reference clock is reduced if more safety margins are needed, The margin between the evaluation of the circuit and the pre-charge cycle can be easily adjusted to achieve the maximum performance.

In Figure 5-8 a rubber band logic circuit is shown for performing two data evaluations for each cycle of the reference clock. Figure 5 shows a simple circuit diagram of the circuit used to generate the pre-charge pulse for a rubber band logic circuit capable of evaluating two data per clock cycle. FIG. 6 shows a simple timing diagram of a number of rubber band clocks and the pre-charge and evaluation signals generated therefrom. 7 and 8 show, in a simple circuit diagram, the relevant parts of a representative rubber band logic circuit including a pre-charge clock and an evaluation clock.

In FIG. 5, two AND gates 501 and 502 are shown. OR gate 511 receives the rubber band clocks (CLK3 505, CLK1 508) as inputs. The AND gate 501 outputs a signal (CLKPC1, 510) used as an input to the subsequent OR gate 512. [ The AND gate 502 receives as inputs the rubber band clocks CLK3B 514, CLK1B 516. From this input, the AND gate 502 outputs the signal (CLKPC2, 518) used as the input to the 2-input OR gate 512. From the inputs (CLKPC1 510, CLKPC2 518), the OR gate 512 outputs the rubber band signal (CLKPC) 520 used to precharge the rubber band logic circuit twice per cycle of the system clock. The signal CLKPC 520 goes high when both the clocks CLK3 505 and CLK1 508 are high or when the clocks CLK3B 514 and CLK1B 516 are both high, Stay at low.

To further illustrate the role of the rubber band signal (CLKPC, 520) in a rubber band logic circuit that evaluates two data per system clock cycle, FIG. 6 illustrates the use of multiple rubber band clocks (CLK1, CLK3) As a simple timing chart. The clocks CLK1 and CLK3 and their complementary clocks may be generated by a circuit similar to that shown in FIG.

The clock signals CLK1 and CLK3 are shown in FIG. The clock signals CLK1 and CLK3 represent a rubber band clock phase shifted with respect to each other, that is, delayed from each other by a frequency dependent delay period. Clock CLK3 is the clock CLK3 on conductor 505 of FIGURE 5 and clock CLK1B is clock CLK1B on conductor 516 of FIGURE 5. [ FIG. 6 shows the selected complementary clock of the rubber band clock. The selected complementary rubber band clock shown in FIG. 6 is the clocks CLK1B and CLK3B. The complementary rubber bad clock CLK3B is the clock CLK3B on the conductor of FIG. 5 and the clock CLK1 is the clock CLK1 on the conductor of FIG. 5. The complementary clock CLK1B is an image of the rubber band clock CLK1. FIG. 6 shows the signals CLKPC1 and CLKPC2 which are the signals shown on the conductors 510 and 518 of FIG. 5.

FIG. 6 shows a rubber band signal (CLKPC) used to pre-charge the output node of the seventh-degree logic circuit 2 every cycle of the system clock. The signal CLKPC shown on the conductor 520 is generated from the signals CLKPC1 and CLKPC2. The clocks (CLKPC, CLKPC1, CLKPC2) are derived from the rubber band clock and the clocks (CLKPC, CLKPC1, CLKPC2), respectively, are delayed from the reference clock (209) in the first degree by the frequency dependent period. 6, there is shown a data signal 616 shown as having data valid cycles 618 and 620 per cycle of the system clock.

Consider the rubber band clocks CLK3 and CLK1 in the relationship between the signal CLKPC1 and the multiple rubber band clock. The rubber band clock CLK1 is already high when the rubber band clock CLK3 transitions from low to high at the edge 622. The high state of the clocks CLK3 and CLK1 is the AND gate 501, (CLKPC1) at an edge 624 via the signal CLKPC1. Signal CLKPC1 stays high until rubber band clock CLK1 transitions from high to low at edge 626. [ Signal CLKPC1 goes low at edge 627 through the operation of AND gate 501 when rubber band clock CLK3 is still high when clock CLK1 makes a high-low transition at edge 626. [ The pulse on the clock CLKPC1 due to the edges 622 and 626 is defined by the edges 624 and 627 in FIG. In the same manner, when the rubber band clock CLK3 goes high at the edge 632, the signal CLKPC1 goes high again at the rising edge 630 and falls when the rubber band clock CLK1 goes low from the edge 636 Lt; / RTI > transition from high to low at the edge 634 of FIG.

While the signal CLKPC2 is controlled by complementary rubber band clocks CLK1B and CLK3B. The complementary rubber band clock (CLK1B) is already high when the complementary rubber band clock (CLK3B) transitions from low to high at edge (640). Hence, AND gate 502 causes signal CLKPC2 to go high at edge 642. When the complementary rubber band clock CLK1B goes low at the edge 644, the signal CLKPC2 goes low at the edge 646, even though the complementary rubber band clock CLK3B is still high. The subsequent rising edge of the clock (CLKPC) pulse, which features edge 650, is generated in the same manner.

Precharge clock signal CLKPC, which is the sum of signals CLKPC1 and CLKPC2, is shown in FIG. Each precharge pulse of the signal CLKPC is slightly delayed from each constituent pulse by the signal CLKPC1 or the signal CLKPC2 due to the operation of the OR gate 51. [ The delay associated with OR gate 512 is shown in FIG. 6 for a period 654.

Four pre-charge pulses are generated with two pre-charge pulses per clock cycle or with pulses 660, 662, 664, 666 in FIG. 6 using the circuit of FIG. 5 and multiple rubber band clocks CLK1, CLK1B, CLK3, CLK3B. As a result, there is one precharge pulse per data valid cycle, providing the precharge pulse at the appropriate time to pre-charge the rubber band logic circuit. As the reference clock is accelerated and the time between edges 622, 626, 640, 644, 632, 636 shrinks, the size of the precharge pulses 660, 662, 664, 666 decreases while the frequency of the precharge clock signal CLKPC increases. Conversely, when the reference clock is decelerated and the time between edges 622, 626, 640, 644, 632, 636 expands, the size of the precharge pulses 660, 662, 664, 666 increases while the frequency of the precharge clock signal CLKPC decreases.

Figure 7 shows a simple circuit diagram of a rubber band logic circuit that utilizes multiple rubber band clocks to evaluate two data per clock cycle. 7 shows an evaluation tree 708 of a rubber band logic circuit stage that includes a p-channel pre-charge device 710 and an n-channel evaluation device 712, 714, 716. In FIG. The operation of the remainder of the rubber band logic circuit has not been repeated here, as discussed in FIG.

The N-channel estimator 712 is controlled on the conductor 718 by a data pulse DP. The N-channel estimators 714 and 716 are controlled by signals (DATA-A, DATA-C) on conductors 720 and 722. The gates of the n-channel estimation devices 714 and 716 are connected to V _dd while the inputs to the gates of the n-channel devices 714 and 716 are logic inputs to the rubber band logic circuit of FIG. 7. However, one of the devices 712, 714, 716 may be used to control the evaluation of the seventh-degree circuit connected to the conductor 718. A further logic input DATA-A to the rubber band logic circuit of FIG. 7 is shown on the conductor 730. DATA-A is coupled to a first input port of a two-input NOR gate 738. [ The second input of the NOR gate 738 is connected to the rubber band signal CLKPC by a conductor 746. The signal CLKPC provides a pre-charge pulse to the rubber band logic circuit of FIG. the signal CLKPC passing through the conduction line 745 to control the p-channel pre-charge device 710 is inverted by the inverter 748 as shown in FIG. 7 to indicate the presence of a crowbar condition Stop. A delay inherent in the inverter 748 prevents unnecessary power consumption.

As is well known to those familiar with NOR gates, if one of the inputs to NOR gate 738 is high, conductor 718 stays low. Conversely, if all inputs to NOR gate 738 are low, conductor 718 goes high and turns on n-channel estimator 712. During pre-charging, signal CLKPC on conductor 745 is high. The high state of conductors 745 and 746 causes the output of NOR gate 738 to stay low to turn off n-channel device 712 and disconnect the output node 752 of the seventh degree rubber band logic circuit from V _dd . At the same time, conductor 750 goes low through the operation of inverter 748 to turn on p-channel pre-charge device 710 and pre-charge output node 752. The p-channel device 710 may be turned on by making the delay time for the transition from the high input to the low output of the inverter 748, which is slightly longer than the propagation delay of the NOR gate 738 after the n- have. At the end of the pre-charge cycle, signal CLKPC on conductor 745 goes low to drive conductor 750 high through inverter 748 to turn off p-channel device 710.

The high DATA-A on conductor 730 during the evaluation cycle when the clock signal CLKPC is low causes the output of NOR gate 738 to stay low. In this case, the n-channel estimator 712 is not turned on and the output node 752 stays pre-charged high. In contrast, the output of NOR gate 738 goes high through the operation of NOR gate 738 when DATA-A on conductor 730 is low. Thus, the n-channel estimator 712 is turned on and the output node 752 is pulled low through the evaluation devices 712, 714, and 716. Inverter 748 is tilted so that the delay for the low input-high output transition is slightly shorter than the propagation delay of NOR gate 738. [ Therefore, the p-channel pre-charge device 710 is turned off and the output node 752 is removed from Vdd before the conductor 718 goes high. The evaluation cycle ends when CLKPC goes high on conductor 745 early in the pre-charge cycle.

FIG. 8 shows another embodiment of the circuit of FIG. 7 in which the rubber band signal CLKEV is used for evaluation and the separated rubber band signal NCLKPC is used for pre-charging. In the circuit of FIG. 8, conductor 730 is connected to DATA. However, the conductor 746 connected to one of the NOR gate 738 inputs is not connected to the signal CLKPC shown in FIG. 7 and is connected to the separate rubber band signal CLKEV of FIG. FIG. 8 shows a conductor 750 used to control the p-channel pre-charge device 710 coupled to the signal NCLKPC. The signal NCLKPC can be derived by applying the inverter to the signal CLKPC in the manner shown in FIG. 7, which is the inverse of the seventh degree signal CLKPC. Conversely, it can be derived directly from the plurality of rubber band clocks generated by a circuit similar to that shown in FIG. 5, except that the OR gate 512 is replaced by a NOR gate. In order to avoid a race condition, the evaluation pulse of the rubber band signal NCLKEV does not overlap with the precharge pulse of the evaluation rubber band signal NCLKPC. Since the rubber band clock is used to generate the rubber band signals (NCLKPC, CLKEV), the pulses on the signal never overlap by selecting the appropriate rubber band clock for pulse generation. Even when the frequency of the external reference signal changes in this manner, the relative relationship between the evaluation on the rubber band signals (CLKEV, NCLKPC) and the pre-charge pulse does not change. In addition, since the delay between clocks is no longer dependent on the configuration of the fixed physical delay elements, the present invention avoids process variation problems associated with the assembly of fixed physical delay elements.

Although the present invention has been described in detail for the sake of understanding, modifications may be made within the scope of the appended claims. It will be apparent to those skilled in the art that combinations and permutations are possible without departing from the spirit of the invention. For example, although a specific example refers to a circuit for evaluating two data cycles per clock cycle, a circuit for evaluating more or fewer data cycles per clock cycle may be implemented. Also, although the present technology and circuit are described with reference to a wave propagation circuit, the present invention is not limited thereto and can be applied to various types of CMOS circuits including NOR logic circuits and domino logic circuits. Accordingly, the scope of the present invention is not to be limited to the specific embodiments, but is defined in the appended claims.

Figure 1 is a circuit diagram used to generate multiple rubberband clocks;

Figure 2A is a timing diagram showing the frequency dependency between an external clock signal and a rubber band clock;

Figure 2B is a timing diagram showing the frequency dependency of the rubber band clock.

Figure 3 is a block diagram of a NAND gate based rubber band logic circuit according to one aspect of the present invention;

4 is a timing diagram showing the relationship between the logic state of the node of the third degree circuit and the rubber band clock during evaluation and pre-charging;

5 is a circuit diagram used to generate a precharge pulse for a rubber band logic circuit capable of evaluating two data per clock cycle.

FIG. 6 shows multiple rubber bands and pre-charging and evaluates signals generated therefrom.

7 shows a rubber band logic circuit using multiple rubber band clocks to evaluate two data for each clock cycle.

FIG. 8 shows another embodiment of a seventh phase circuit in which one rubber band signal is used for evaluation and another separate rubber band is used for pre-charging.

* Code Description

80, 82 ... circuit steps 100,108,122,128,137 ... node

110, 112, 114 ... evaluation device 201 ... PLL circuit

203 ... phase frequency detector 205 ... charge pump

207 ... Voltage control oscillator 209 ... External reference clock signal

211 ... internal reference clock signal 212,213,214,216,218 ... clock

220 ... up signal 222 ... down signal

224,252 ... control voltage 226 ... n-channel device

228, 230, 232, 233, 234 ...

236,710 ... p-channel device 238,748 ... Inverter

242, 244, 246, 247, 248 ... clock 254 ... buffer

378,622,624,626,627,630,632,634,636,640,644,650 ... Corner

508,510,518,520 ... conductors

501, 502 ... AND gate 512 ... NOR gate

618,620 ... Data Cycle

660,662,664,666 ... Pre-charge pulse

712,714,716 ... n-channel device

718, 720, 722, 730, 745, 746, . . conductor

738 ... NOR gate 752 ... output node

Claims (22)

A first clock terminal for coupling with a first clock that is delayed from a reference clock by a first frequency dependent delay period; A second clock terminal for coupling with a second clock that is delayed from the reference clock by a second frequency dependent delay period; And A pulse generator circuit coupled to the first clock terminal and the second clock terminal, an output terminal, an evaluation device coupled to the output terminal and the pulse generator circuit, and an output terminal coupled to the output terminal and a first logic level and a third frequency dependent delay time And a first circuit stage (80) including a precharge device coupled to a third clock terminal that is delayed from a reference clock to evaluate a logic input in response to a reference clock. 2. The rubber band logic circuit of claim 1, wherein the third frequency dependent delay period is similar to the first frequency dependent delay period, wherein the third frequency dependent delay period is similar to the first frequency dependent delay period. 2. The rubber band logic circuit of claim 1, wherein the third frequency dependent delay period is longer than the first frequency dependent delay period and the second frequency dependent delay period. 4. The apparatus of claim 3, wherein the pulse generator circuit comprises: a first inverter having an inverter output coupled to the evaluation device; and A gate having a first gate element input at one data terminal, a second gate element input coupled to the first clock terminal, a third gate element input coupled to the second clock terminal, and a gate element output coupled to the first inverter input, And wherein the logic gate comprises an element gate. 5. The apparatus of claim 4, wherein said first inverter is connected to said first logic level, said evaluation device and said gate element output, and a first p- Further comprising a first n-channel device coupled to the first p-channel device, the evaluation device, the third clock terminal and a second logic level. Logic circuit. 6. The method of claim 5, wherein the first circuit stage (80) further comprises a second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the third clock terminal, And a second inverter output is coupled to the control terminal of the pre-charge device. The method according to claim 6, The second circuit (82) step output terminal, A second stage evaluation device connected to the second circuit stage output terminal, A second stage precharge device coupled to the second circuit stage output terminal and to the first logic level; And Further comprising a second circuit stage comprising a third inverter connected in series between the output terminal of the first circuit stage (80) and the evaluation device of the second circuit stage (82) A rubber band logic circuit responsive to evaluating a logic input. 8. The method of claim 7, wherein the pulse generation circuit generates a data pulse in response to an evaluation cycle of the first clock terminal and the second clock terminal. Circuit. 2. The rubber band logic circuit of claim 1, wherein the second frequency dependent delay period is the same as the first frequency dependent delay period, and wherein the logic input is evaluated in response to a reference clock. The method according to claim 1, A first inverter having an inverter output connected to the evaluation device, A first gate element input coupled to the data terminal, a second gate element input coupled to the first clock terminal, a third gate element input coupled to the second clock terminal, and a gate element output coupled to the input of the first inverter Wherein the logic input is in response to a reference clock. Providing a precharge pulse to a precharge node of the logic circuit; Providing a data pulse delayed from the precharge pulse by a frequency dependent delay period at a data input node of the logic circuit; Charge the output node of the logic circuit with the precharge pulse; And And evaluating a logic input to the logic circuit using the evaluating device of the logic circuit with the data pulse to derive a logic state of the output node, How to evaluate input. 12. The method of claim 11 wherein said data pulse and said precharge pulse are generated by at least two clocks, said at least two clocks being clocks derived from a reference clock and shifted relative to each other. How to evaluate logic inputs in response. 13. The method of claim 12, wherein the two clocks are generated from the reference clock using PLL circuitry. Providing a first clock terminal having a first clock delayed from a reference clock by a first frequency dependent delay period; Providing a second clock terminal having a second clock that is delayed from the reference clock by a second frequency dependent delay period; And Connecting a pulse generation circuit to the first clock terminal and the second clock terminal, providing an output terminal, connecting a first circuit stage evaluation device to the output terminal and the pulse generation circuit, and And a first circuit stage (80) for connecting the precharge device to a third clock terminal that is delayed from the reference clock by a first logic level and a third frequency dependent delay period, To evaluate logic inputs. 15. The method of claim 14, wherein the step of providing the pulse generating circuit provides a first inverter; Connecting an output terminal of the first inverter to the first circuit stage evaluation device; Providing a gate element gate; And A second gate terminal input of said gate element gate to said first clock terminal, a third gate element input of said gate element gate to said second clock terminal And connecting a gate element output of the gate element gate to an input of the first inverter. 16. The method of claim 15, wherein said step of providing said first inverter Providing a first p-channel device; Connecting said first p-channel device to said first logic level, said first circuit stage evaluation device and said gate element output; Providing a fourth clock terminal having a first channel device and a fourth clock, said third clock being an inverted version of said fourth clock; And And connecting said first n-channel device to said first p-channel device, said first circuit stage evaluator, said fourth clock terminal, and a second logic level. A method for evaluating a logic input. 17. The method of claim 16, wherein said step of providing said first inverter provides an output terminal of a second circuit stage (82), connecting said second circuit stage evaluation device to said second circuit stage output terminal, Providing a second circuit step comprising connecting a circuit-stage pre-charging device to the second circuit-stage output terminal and the first logic level; And And connecting a second inverter in series between the output terminal of the first circuit stage and the second circuit stage evaluation device. 18. The method of claim 17, further comprising providing a plurality of evaluation devices, each of the plurality of evaluation devices being coupled to a logic input, and wherein a first one of the plurality of evaluation devices is coupled to the second logic level And a second evaluation device is coupled to the first circuit stage evaluation device. 19. The method of claim 18, wherein the sum of the plurality of evaluation devices and the first circuit stage evaluation device is equal to the number of logic inputs to the first circuit stage evaluating the logic input in response to the reference clock Way. A precharge node providing a precharge pulse having a precharge pulse activation edge and a precharge pulse deactivation edge defining a precharge pulse width varying in response to a frequency of a reference clock; A data input node providing a data pulse having a data pulse activation edge and a data pulse deactivation edge during a data valid cycle, the data pulse activation edge defining a data pulse width varying in response to a reference clock frequency, Delayed from the charge pulse deactivation edge); A plurality of evaluation devices, wherein a first evaluation device of the plurality of evaluation devices is connected to the data input node and a second evaluation device is connected to the first logic level; An output node coupled to the pre-charged node; And A precharge device coupled to the precharge node, the output node and a second logic level, the precharge device coupling the output node to the second logic level in response to the precharge pulse, How to evaluate logic inputs in response. 21. The method of claim 20, wherein the data pulse activation edge and the precharge pulse deactivation edge are generated by at least two clocks, wherein the at least two clocks represent a phase shifted relative to each other. To evaluate logic inputs. 22. The method of claim 21, wherein the two clocks are generated from the reference clock using a PLL circuit.