KR100406585B1 - Cell-to-cell repair apparatus - Google Patents

Abstract

PURPOSE: A cell-to-cell repair apparatus is provided to reduce a failure rate due to a defect of a spare cell and enhance the productivity by driving the spare cell instead of a failed normal cell. CONSTITUTION: A cell-to-cell repair apparatus includes an address fuse box, an address decoder, a disable normal word line/bit line selector, and a spare word line/bit line driver. The address fuse box(10) includes one or more fuses and outputs selectively an address signal when a state of failure is generated from a normal cell. The address decoder(20) is used for decoding an address signal of the address fuse box. The disable normal word line/bit line selector(30) is used for selecting a word line and a bit line of a failed normal cell in response to a decoding signal of the address decoder. The spare word line/bit line driver(40) is used for driving a word line and a bit line of a corresponding spare cell to substitute the failed normal cell with the spare cell in response to the decoding signal of the address decoder.

Description

Cell-to-Cell Repair Device

The present invention relates to a repair apparatus, and more particularly, to a cell-to-cell repair apparatus capable of increasing yield by performing cell-to-cell repayment on a failed normal cell.

The semiconductor memory device has a plurality of memory cells arranged in a matrix of rows and columns, and as memory capacity increases, a larger number of memory cells are arranged in a unit area. The semiconductor memory device cannot be used even if a defect occurs in any one of the memory cells.

Thus, a method of improving a yield by allowing a memory cell having a faulty memory cell to be used even if a faulty memory cell is present, comprising a plurality of spare cells corresponding to a normal memory cell array, and causing a faulty normal cell. A method of replacing with a spare cell has been proposed. That is, in the early days when the repair technology was proposed, a fuse is connected to each bit line or word line of the semiconductor memory device, and when a defect occurs in the normal cell, the fuse connected to the bit line or word line connected to the normal cell is connected to the laser projection. Repair was performed by cutting in the same manner.

However, as the degree of integration of semiconductor memory devices increases, fuses cannot be connected to bit lines and word lines of many memory cells existing in a chip, thereby decoding an internal address for a spare cell when a normal cell fails. A way of doing this has been proposed. Recently, when an address signal corresponding to a defective bit line or word line is input, the repair is performed by operating the word line or bit line of the spare cell instead of the bit line or word line of the normal cell. do.

That is, FIG. 1 is a view showing a schematic configuration of a semiconductor device for explaining a general repair method. As shown in FIG. 1, a predetermined failed cell area A is shown in the normal cell area N of the semiconductor device. In this case, if an address (Add) signal is specified according to the normal operation, the address (a) of the failed cell region (A) is selected to cause a device defect. However, if an Add signal according to the repair operation is designated, the repair is performed by selecting the spare cell region B. Such repairing is performed in units of one row or one column (COLUMN). do.

However, in the above-described conventional repair, as a spare cell is replaced by a row or column unit, there is a problem that a device fails due to a defect of the spare cell.

That is, most of normal cells fail due to defects in particles or process margins. When a failed normal cell is replaced with a spare cell, the failed normal cells are replaced according to whether or not the spare cell is defective. By performing the repair, the value of the FTA that determines whether the repaired cells can operate normally can be changed. Therefore, the defect of the spare cell is closely related to the productivity.

For example, a spare cell that is replaced by a row or color unit, even when the failed normal cell is about 1 bit or a predetermined bit, must use about 1K bit, causing defects in such spare cells to increase the probability of a device failing. do.

Accordingly, the present invention was created in view of the above-described problems, and performs a cell-to-cell (ie, 1: 1) repair on the failed cell, thereby minimizing the failure rate of the device due to the defect of the spare cell. It is an object of the present invention to provide a cell-to-cell repair apparatus capable of increasing yield.

1 is a view for explaining a general repair method.

2 is a block diagram schematically illustrating a cell-to-cell repair apparatus according to an embodiment of the present invention.

3A-3D illustrate internal circuitry of a cell-to-cell repair device in accordance with one embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: address fuse box 20: address decoding unit

30: disable normal word line / bit line selector

40: spare word line / bit line driver

The cell-to-cell repair apparatus according to the present invention for achieving the above object is a repair apparatus having a plurality of normal cells and a plurality of spare cells, and replaces the plurality of spare cells in the failure of the plurality of normal cells An address fuse box including at least one fuse and selectively outputting an address signal input according to the cutting of the fuse when a failure of the normal cell occurs; Address decoding means for decoding an address signal output from said address fuse box and generating a decoded signal; Disable normal word line / bit line selection means for selecting and disabling word lines and bit lines of a fail-generated normal cell among the plurality of normal cells in response to a decoding signal from the address decoding means; And spare word line / bit line driving means for driving a word line and a bit line of the spare cell in order to replace the fail-generated normal cell with a predetermined spare cell in response to a decoding signal output from the address decoding means. Characterized in that.

According to the present invention having the above configuration, the repair of the corresponding cell is performed through the row and column addresses of the failed normal cell. When the row and column addresses of the failed normal cell are specified, the failed normal cell is disabled. The selected spare cell is driven.

(Example)

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2 is a block diagram schematically illustrating a cell-to-cell repair apparatus according to an embodiment of the present invention.

As shown in FIG. 3, the cell-to-cell repair apparatus includes at least one fuse, an address fuse box 10 for selectively outputting an address signal input according to the cutting of the fuse when a normal cell fails, and an address; An address decoding unit 20 which decodes an address signal output from the fuse box 10 to generate a decoding signal, and a normal cell of which a failure is generated among a plurality of normal cells in response to the decoding signal from the address decoding unit 20. A predetermined normal word line / bit line selector 30 for selecting and disabling word lines and bit lines and a normal cell in which the fail is generated in response to a decoded signal output from the address decoder 20 are selected. In order to replace a spare cell, a spare word line / bit line driver 40 for driving a word line and a bit line of the spare cell is provided. Equipped.

Next, the operation of the device having the above-described configuration will be described with reference to the internal circuit diagrams shown in Figs. 3A to 3B.

First, FIG. 3A is a diagram illustrating an internal circuit diagram of the address fuse box 10 shown in FIG. 2. The address fuse box 10 includes a first transistor M1 connected to a fuse F, and the first transistor. A first inverter INV1 for inverting the signal output from the connection point A of the fuse F and the first and second transmission gates having the address signal Ai and the inverted address signal Ai as their respective inputs. (T1, T2) are provided. Here, the output signal from the connection point A is input to the gate of the N-MOS transistor of the first transmission gate T1 and is also input to the gate of the P-MOS transistor of the second transmission gate T2. In addition, the output of the first inverter INV1 is connected to the connection point B of the first and second transmission gates T1 and T2, and is input to the gates of the respective P-MOS and N-MOS transistors. It is input to the gate of one transistor. The outputs of the first and second transmission gates T1 and T2 are connected to each other to output the address signal RAi.

That is, in the above-described address fuse box 10, when the fuse F is blown when the input address signal Ai is at the logic level "low", the address signal RAi at the logic level "high" is output. do.

Accordingly, the address signal RAi output from the address fuse box 10 is decoded by the address decoding unit 20. FIG. 3B shows a row X for the case where the address signal RAi is RA0 to RA3. A circuit for decoding the address of the column Y is shown.

That is, as shown in FIG. 3B, the address decoding unit 20 performs a logical AND on the first and second row address signals X0 and X1 and then inverts the first NAND gate NAND1 and the third and fourth nodes. A second NAND gate NAND2 that inverts and then inverts the row address signals X2 and X3, and a first NOR gate NOR1 that inverts and then inverts the output of the first and second NAND gates NAND1 and NAND2. And inversely multiply the signal output from the second nodal gate NOR2 of the column address with the signal output from the first nodal gate NOR1 of the row address in the same manner as the logic circuit of the row address. The fifth NAND gate NAND5 is provided.

Accordingly, when the first to fourth row address signals X0 to X3 and the first to fourth column address signals Y0 to Y3 are all at the logic level "high", the logic level is changed from the fifth NAND gay NAND5. Low "control signal C is output.

Subsequently, the control signal C of the logic level " low " is input to the disable normal word line / bit line selector 30 and the spare word line / bit line driver 40, respectively.

First, FIG. 3C shows a word line (W / L) and a bit line (B / L) of a normal cell that are disabled by a control signal (C) output from the address decoding unit (20) and a predetermined input signal (I). Is a diagram illustrating an internal circuit of the disable normal word line / bit line selector 30 in which () is selected. That is, as shown in FIG. 3B, the disable normal word line / bit line selector 30 may receive a control signal input to one word line W / L and a bit line B / L, respectively. C) and the sixth and seventh NAND gates NAND6 and NAND7 which are inversely multiplied by the input signal I and then inverted, and the respective output signals 01 from the sixth and seventh NAND gates NAND6 and NAND7. Are provided with second and third inverters INV2 and INV3 for outputting the signals as inverted signals 02. Accordingly, one word line W / L and a bit are output by the output signals 02 of the second and third inverters INV2 and INV3 among the word lines W / L and bit lines B / L. The disable or enable for line B / L is selected.

That is, Table 1 below shows the output signal (01, 02) and the word line (W / L) and the bit line according to the input signal (C, I) of the disable normal word line / bit line selector 30 described above As a table showing the state of (B / L), the word line (W / L) and the bit line (B / L) are disabled when a control signal (C) of logic level "low" is input.

TABLE 1

3D shows a spare word line for driving word lines W / L and bit lines B / L of the spare cells enabled by the control signal C outputted from the address decoding unit 20. The internal circuit of the bit line driver 30 is shown.

That is, as illustrated in FIG. 3D, the spare word line / bit line driver 30 may include a third inverter INV3 for inverting and outputting the control signal C and an output connection point of the third inverter INV3. A fifth transistor M5 having a gate connected to H and a seventh transistor having a gate connected to a source of a sixth transistor M6 and a fifth transistor M5 connected in series with the fifth transistor M5; An M7 is connected to one word line and one bit line. Here, the fuse F1 is connected to the gate of the sixth transistor M6, the drain and the bit line B / L of the seventh transistor M7 are connected, and predetermined data is output through the source. do. In such a configuration, the gates of the predetermined transistors are connected to each bit line B / L of the spare cell through the output connection point H of the third inverter INV3.

In addition, the inverted control signal output from the third inverter INV3 is applied to the gates of the twelfth and fourteenth transistors M12 and M14 connected to the word line W / L. Accordingly, when the control signal C having the logic level "low" is input, the word line W / L and the bit line (s) of the spare cell are generated by the "high" signal inverted through the third inverter INV3. B / L) is selected and driven. That is, a spare cell that replaces the corresponding cell of the disabled word line and the bit line in the disable normal word line / bit line selector 30 is selectively driven.

According to the above-described embodiment, the repair of the corresponding cell is performed through the address of the row and column of the failed normal cell. When the address of the row and column of the failed normal cell is specified, the failed normal cell is disabled. The selected spare cell is driven. That is, as the spare cell is repaired with respect to the cell to cell failed normal cell, the failure occurrence rate of the device due to the coupling of the spare cells is minimized, so that the yield is improved.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

As described above, according to the present invention, a cell-to-cell repair apparatus capable of increasing the yield by performing cell-to-cell repair on a failed normal cell can be realized.

Claims (3)

In the repair apparatus having a plurality of normal cells and a plurality of spare cells, and when the failure of the plurality of normal cells to replace the plurality of spare cells, An address fuse box including at least one fuse and selectively outputting an address signal input according to the cutting of the fuse when a failure of the normal cell occurs; Address decoding means for decoding an address signal output from said address fuse box and generating a decoded signal; Disable normal word line / bit line selecting means for selecting and disabling word lines and bit lines of a fail-generated normal cell among the plurality of normal cells in response to a decoding signal from the address decoding means; And A spare word line / bit line driving means for driving a word line and a bit line of the spare cell in order to replace the fail-generated normal cell with a predetermined spare cell in response to a decoding signal output from the address decoding means. Cell-to-cell repair device. The method of claim 1, And the address fuse box outputs a signal having a logic level 'high' when a normal cell fails. The method of claim 1, The address fuse box outputs a signal of logic level 'high' when a failure of the normal cell occurs, And the address decoding means outputs a logic level 'low' signal when a normal cell fails.