KR100406563B1 - Planarization method of semiconductor device - Google Patents

Planarization method of semiconductor device Download PDF

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KR100406563B1
KR100406563B1 KR1019970017506A KR19970017506A KR100406563B1 KR 100406563 B1 KR100406563 B1 KR 100406563B1 KR 1019970017506 A KR1019970017506 A KR 1019970017506A KR 19970017506 A KR19970017506 A KR 19970017506A KR 100406563 B1 KR100406563 B1 KR 100406563B1
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wafer
laser
semiconductor device
planarization
etched
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KR1019970017506A
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Korean (ko)
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KR19980082528A (en
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안희균
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A planarization method of a semiconductor device is provided to be capable of improving the characteristic, reliability, and integration degree of the semiconductor device. CONSTITUTION: A to-be-etched layer of a wafer(17) is etched from the upper portion of the wafer to an end-point by using laser beam which irradiates to the side of the wafer. At the same time, the particles generated at the upper portion of the wafer are removed by flowing inert gas. Preferably, the etching process is performed by adding deionized water. At the time, the wafer is capable of being rotated by using a rotation pedestal(13), wherein the rotation pedestal is formed at the lower portion of the wafer.

Description

반도체소자의 평탄화방법Planarization method of semiconductor device

본 발명은 반도체소자의 평탄화방법에 관한 것으로, 특히 반도체 소자의 층간 절연막을 평탄화시키는 방법에 있어서, 레이져를 이용하여 실시함으로써 반도체 소자의 특성 및 신뢰성을 향상시키는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device. In particular, in the method of planarizing an interlayer insulating film of a semiconductor device, the laser device is used to improve characteristics and reliability of the semiconductor device.

반도체 소자의 고집적화에 따라 소자 표면의 요철은 더욱 심화되어 고단차의표면을 절연막으로 채우는 평탄화 기술은 반도체 소자 제조에 있어 중요한 기술중 하나로 대두되고 있다.As the integration of semiconductor devices increases, the unevenness of the surface of the device is further intensified, and the planarization technology of filling the surface of the high step with an insulating film has emerged as one of the important technologies in the manufacture of semiconductor devices.

일반적으로, 평탄화기술은 금속배선 이전의 도전배선간 절연막으로서 또한 기 형성된 도전배선으로부터 기인된 표면을 평탄화하기 위해서, 고농도의 붕소(B)및 인(P)을 첨가한 비.피.에스.지. ( Boro Phospho Silicate Glass, 이하에서 BPSG 라 함 ) 산화막이나 에스.오.지. ( spin on glass, 이하에서 SOG 라 함 ) 산화막을 도전배선 상부에 증착하여 고온에서 리플로우 ( reflow ) 시키는 방법을 이용하였다.In general, the planarization technique is a B.P.S. paper containing high concentrations of boron (B) and phosphorus (P) to planarize the surface resulting from the previously formed conductive wiring as an insulating film between the conductive wirings before the metal wiring. . (Boro Phospho Silicate Glass, hereinafter referred to as BPSG) Oxide or S.O. (Spin on glass, hereinafter referred to as SOG) An oxide film was deposited on the conductive wiring to reflow at high temperature.

그러나, 상기 리플로우 방법은, 이미 두꺼운 두께로 형성하고 열공정을 실시하여 리플로우시킴으로써 평탄화하였으나, 이는 반도체소자의 고집적화를 충족시키지 못하였다.However, the reflow method is already formed to a thick thickness and planarized by reflowing by performing a thermal process, but this does not satisfy the high integration of the semiconductor device.

이를 해결하기 위하여, 최근에는 화학기계연마 ( chemical mechanical polishing, 이하에서 CMP라 함 ) 방법을 이용하여 평탄화 공정을 실시하였다.In order to solve this problem, a planarization process has been recently performed by using chemical mechanical polishing (hereinafter, referred to as CMP).

그러나, 상기 CMP 공정은 기계적 연마를 실시하여 웨이퍼의 가장자리가 많이 연마되기 쉽고, 슬러리 ( slurry ) 에 의한 오염이 있어 세정공정을 필히 수반하여야 한다. 그리고, CMP 하는 표면의 재질이 상이한 경우는 한곳이 다른 한곳보다 먼저 연마되는 경우도 발생하여 완전한 평탄화를 이룩하지 못한다.However, in the CMP process, the edge of the wafer is easily polished by mechanical polishing, and there is contamination by slurry, so the cleaning process must be accompanied. In addition, when the material of the CMP surface is different, the case where one place is polished before the other place occurs, thereby failing to achieve perfect planarization.

이로인하여, 상기 CMP 공정은 CMP 공정의 균일성이 나쁘고, 슬러리 제거 세정공정을 필요로하며, 고집적화에 필요한 평탄화 정도를 만족시키지 못한다.As a result, the CMP process has a poor uniformity of the CMP process, requires a slurry removal cleaning process, and does not satisfy the degree of planarization required for high integration.

상기한 바와같이 종래기술에 따른 반도체소자의 평탄화 방법은, 세정공정 추가로 공정단계를 증가시키고 고집적화에 적합한 평탄화 공정을 실시하지 못하여 반도체소자의 고집적화를 어렵게 하고 그에 따른 반도체소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, the planarization method of the semiconductor device according to the prior art makes it difficult to increase the integration of the semiconductor device due to an increase in processing steps and a failure to perform a planarization process suitable for high integration, thereby degrading the characteristics and reliability of the semiconductor device. There is a problem.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 레이저를 이용하여 단순화된 공정으로 평탄화시킴으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 평탄화방법을 제공하는데 그 목적이 있다.The present invention provides a planarization method of a semiconductor device to improve the characteristics and reliability of the semiconductor device and thereby high integration of the semiconductor device by flattening in a simplified process using a laser to solve the above problems of the prior art. Its purpose is to.

도 1a 및 도 1b는 본 발명의 실시예에 따른 반도체소자의 평탄화방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a planarization method of a semiconductor device in accordance with an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of Symbols for Main Parts of Drawings>

11 : 반응챔버 13 : 회전대11: reaction chamber 13: swivel

15 : 웨이퍼 고정대 17 : 웨이퍼15: wafer holder 17: wafer

19 : 레이저 검출기 21 : 레이저 건 지지/이동대19: laser detector 21: laser gun support / mobile

23 : 레이저 건 25 : 배출구23 laser gun 25 outlet

27 : 불활성가스 주입구 29 : 피식각층27: inert gas injection port 29: etching target layer

ⓐ : 최상부에서 레이저 경로 ⓑ : 엔드-포인트의 레이저 경로Ⓐ: Laser path at the top ⓑ: Laser path at the end point

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 평탄화방법은,In order to achieve the above object, the semiconductor device planarization method according to the present invention,

피식각층을 갖는 웨이퍼를 평탄화시키는 반도체소자의 평탄화방법에 있어서,In the planarization method of a semiconductor device for planarizing a wafer having an etched layer,

회전하는 웨이퍼의 피식각층을 레이저를 이용하여 식각하되, 레이저를 상기 웨이퍼의 측면에서 상기 피식각층의 상부로 부터 엔드-포인트까지 식각하는 동시에 불활성가스를 주입하여 상기 웨이퍼 상부에 발생되는 파티클을 제거하는 것을 특징으로한다.The etching target layer of the rotating wafer is etched using a laser, and the laser is etched from the top of the etching target layer to the end-point at the side of the wafer while injecting an inert gas to remove particles generated on the wafer. It is characterized by.

또는, 피식각층을 갖는 웨이퍼를 평탄화시키는 반도체소자의 평탄화방법에 있어서,Or in the semiconductor device planarization method which planarizes the wafer which has an etched layer,

회전하는 웨이퍼의 피식각층을 레이저를 이용하여 식각하되, 레이저를 상기 웨이퍼의 측면에서 엔드-포인트부분을 식각하는 동시에 불활성가스를 주입하여 상기 웨이퍼 상부에 발생되는 파티클을 제거하는 것을 특징으로 한다.The etching target layer of the rotating wafer is etched using a laser, and the laser is etched from the end-point portion at the side of the wafer and injected with an inert gas to remove particles generated on the wafer.

한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, 고정대 ( chuck ) 상부에 웨이퍼를 회전시키는 반응챔버의 내벽 일측에 레이저 건 ( gun ) 이 구비된 레이저 건 지지/이동대를 형성하고, 타측에 레이저 검출기를 형성한 다음, 평탄화식각공정의 엔드-포인트 ( end-point ) 을 설정하고, 상기 레이저 건과 레이저 검출기를 이용하여 평탄화식각하는 동시에 불활성기체를 불어줌으로써 배기구를 통하여 식각된 파티클을 외부로 방출하는 것이다. 이때, 상기 평탄화식각공정은 상부로 부터 상기 엔드-포인트 까지 순차적으로 실시하거나, 상기 엔드-포인트를 기준으로 한번에 실시한다.On the other hand, the principle of the present invention for achieving the above object is to form a laser gun support / moving table equipped with a laser gun on one side of the inner wall of the reaction chamber for rotating the wafer on the top of the chuck, and on the other side After forming the laser detector, the end-point of the planarization etching process is set, and the laser gun and the laser detector are used to flatten the etching and blow inert gas to the outside to blow the etched particles outward. To emit. In this case, the planarization etching process is performed sequentially from the top to the end-point, or at a time based on the end-point.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 및 도 1b 는 본 발명의 실시예에 따른 반도체소자의 평탄화방법을 도시한 단면도로서, 도 1b 는 도 1a의 ㉮ 부분을 상세히 도시한 것이다.1A and 1B are cross-sectional views illustrating a planarization method of a semiconductor device in accordance with an embodiment of the present invention, and FIG. 1B illustrates the detail of FIG. 1A in detail.

먼저, 웨이퍼 고정대(15)와 피식각층(29)을 갖는 웨이퍼(17)을 구비하는 회전대(13)를 구비하고, 반응챔버(11)의 내벽 일측에 레이저 건 지지/이동대(21)을 구비하고, 상기 레이저 건 지지/이동대(21)의 반대쪽 내벽에 레이저 검출기(19)를 구비하고, 상기 웨이퍼(17)를 향한 불활성가스 주입구(27)를 구비하고, 파티클을 배출하는 배출구(25)를 구비하는 진공 반응챔버(11)를 형성한다.First, the rotary table 13 including the wafer holder 15 and the wafer 17 having the etching target layer 29 is provided, and the laser gun support / moving table 21 is provided on one side of the inner wall of the reaction chamber 11. A discharge detector 25 having a laser detector 19 on the inner wall opposite the laser gun support / moving table 21, an inert gas injection hole 27 facing the wafer 17, and discharging particles; To form a vacuum reaction chamber 11 having a.

이때, 상기 웨이퍼(17)는 두께구배가 큰 표면이 형성된 것이다. 그리고, 상기 레이저 건 지지/이동대(21)는 레이저 건(23)을 포함하며, 상기 레이저 건(23)을 상하로 이동시키며 지지하는 역할을 한다. 그리고, 상기 불활성가스 주입구(27)는 상기 웨이퍼(17)를 향하며, 가스를 주입하여 상기 웨이퍼(17) 상부에 유발되는 파티클을 제거하기 위한 것으로, 다수를 설치할 수 있다. 그리고, 상기 레이져 건(23)은 레이저 발생기(도시안됨)에 연결된 것이다.At this time, the wafer 17 is a surface having a large thickness gradient is formed. In addition, the laser gun support / moving table 21 includes a laser gun 23, and serves to support the laser gun 23 by moving it up and down. The inert gas injection hole 27 faces the wafer 17 and injects gas to remove particles caused on the wafer 17, and a plurality of inert gas injection holes 27 may be installed. The laser gun 23 is connected to a laser generator (not shown).

그 다음에, 상기 웨이퍼(17)의 평탄화식각공정시 엔드-포인트를 설정한다. 이때, 상기 엔드-포인트는 상기 웨이퍼의 상측에서 레이저를 이용하여 상기 웨이퍼(17)의 두께를 측정함으로써 단차가 가장 낮은 부분을 엔드-포인트로 결정한 것이다.Next, an end-point is set during the planarization etching process of the wafer 17. At this time, the end-point is the portion of the lowest step is determined as the end-point by measuring the thickness of the wafer 17 using a laser on the upper side of the wafer.

그리고, 상기 웨이퍼(17)를 회전시키는 동시에 상기 레이저 발생기에서 발생되는 레이저를 상기 레이저 건(23)으로 발사하며 상기 웨이퍼(17)의 최상측으로 부터 식각하며 상기 엔드-포인트까지 식각하여 평탄화된 웨이퍼(17)를 형성한다. 여기서, ⓐ 는 발사되는 레이저의 최상측을 도시하며, ⓑ 는 엔드-포인트를 도시한다.At the same time, the wafer 17 is rotated and the laser generated by the laser generator is emitted to the laser gun 23, the wafer is etched from the uppermost side of the wafer 17 and etched to the end-point to make the wafer flattened ( 17). Where ⓐ shows the top side of the laser to be fired and ⓑ shows the end-point.

이때, 상기 불활성가스 주입구(27)을 통하여 질소나 아르곤과 같은 불활성가스를 주입하여 상기 레이저를 이용한 식각공정시 발생되는 파티클을 상기 웨이퍼(17) 상부에 제거하고, 상기 파티클을 배출구(25)을 통하여 반응챔버(11)의 외부로 유출시킨다.At this time, by injecting an inert gas such as nitrogen or argon through the inert gas inlet 27 to remove the particles generated during the etching process using the laser on the wafer 17, the particles to the outlet 25 Through the outflow of the reaction chamber 11 through.

여기서, 상기 평탄화식각공정은, 상기 레이저 건 지지/이동대(21)가 정밀할 수록 표면의 막질을 향상시킬 수 있다. 그리고, 상기 레이저의 구경이 작거나, 레이저의 파장이 작은 경우에도 표면의 막질을 향상시킬 수 있다.Here, in the planarization etching process, the more precise the laser gun support / moving table 21 is, the better the film quality of the surface may be. The film quality of the surface can be improved even when the aperture of the laser is small or the wavelength of the laser is small.

한편, 상기 평탄화식각공정의 다른 방법은, 상기 웨이퍼(17)의 하측에서 레이저를 이용하여 상기 웨이퍼(17) 두께를 측정하되, 가장 얇은 부분을 기준으로 하여 엔드-포인트를 설정하고 상기 엔드-포인트에 상기 레이저 건(23)을 고정한 다음, 레이저를 이용하여 식각하는 동시에 상기 주입구(27)을 통하여 불활성가스를 주입하여 파티클을 상기 웨이퍼(17) 상부에 제거하고, 상기 파티클을 반응챔버 밖으로 유출시켜 평탄화공정을 완료한다. (도 1a, 도 1b)Meanwhile, another method of the planarization etching process may measure the thickness of the wafer 17 using a laser at the lower side of the wafer 17, but sets an end-point based on the thinnest part and sets the end-point. After fixing the laser gun 23 to the laser, the laser is etched and at the same time inert gas is injected through the injection hole 27 to remove particles on the wafer 17, and the particles flow out of the reaction chamber Complete the planarization process. (FIG. 1A, FIG. 1B)

본 발명의 다른 실시예는 상기 레이저를 이용한 식각공정시 피식각층의 식각공정시 불필요한 부분의 손상을 방지하기 위하여 순수를 첨가하여 습식으로 진행하는 것이다.Another embodiment of the present invention is to proceed with a wet by adding pure water in order to prevent damage of unnecessary parts during the etching process of the etching layer during the etching process using the laser.

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 평탄화방법은, 레이저를 이용하여 평탄화공정은 실시함으로써 화학약품 사용으로 인한 오염을 방지할 수 있으며, 광학적인 배열로 웨이퍼 막질의 균일성을 유지할 수 있고, 그에 따른 막질 특성을 향상시킬 수 있는 효과가 있다.As described above, in the planarization method of the semiconductor device according to the present invention, the planarization process is performed by using a laser to prevent contamination due to the use of chemicals, and the uniformity of wafer film quality can be maintained in an optical arrangement. As a result, there is an effect that can improve the film properties.

Claims (4)

피식각층을 갖는 웨이퍼를 평탄화시키는 반도체소자의 평탄화방법에 있어서,In the planarization method of a semiconductor device for planarizing a wafer having an etched layer, 회전하는 웨이퍼의 피식각층을 레이저를 이용하여 식각하되, 레이저를 상기 웨이퍼의 측면에서 상기 피식각층의 상부로 부터 엔드-포인트까지 식각하는 동시에 불활성가스를 주입하여 상기 웨이퍼 상부에 발생되는 파티클을 제거하는 것을 특징으로하는 반도체소자의 평탄화방법.The etching target layer of the rotating wafer is etched using a laser, and the laser is etched from the top of the etching target layer to the end-point at the side of the wafer while injecting an inert gas to remove particles generated on the wafer. A planarization method of a semiconductor device, characterized in that. 청구항 1 에 있어서,The method according to claim 1, 상기 피식각층 식각공정은 순수를 첨가하여 실시하는 것을 특징으로하는 반도체소자의 평탄화방법.The etching process of the etching layer is performed by adding pure water. 피식각층을 갖는 웨이퍼를 평탄화시키는 반도체소자의 평탄화방법에 있어서,In the planarization method of a semiconductor device for planarizing a wafer having an etched layer, 회전하는 웨이퍼의 피식각층을 레이저를 이용하여 식각하되, 레이저를 상기 웨이퍼의 측면에서 엔드-포인트부분을 식각하는 동시에 불활성가스를 주입하여 상기 웨이퍼 상부에 발생되는 파티클을 제거하는 것을 특징으로하는 반도체소자의 평탄화방법.A semiconductor device is etched using a laser to etch the etching target layer of the rotating wafer, and the laser is used to etch the end-point portion from the side of the wafer and inject an inert gas to remove particles generated on the wafer. Method of planarization. 청구항 3 에 있어서,The method according to claim 3, 상기 피식각층 식각공정은 순수를 첨가하여 실시하는 것을 특징으로하는 반도체소자의 평탄화방법.The etching process of the etching layer is performed by adding pure water.
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