KR100398577B1 - Method for manufacturing semiconductor device improve static noise margin - Google Patents

Abstract

According to the present invention, there is provided a method of manufacturing a semiconductor device having improved static noise margin, comprising: defining an active region and a field region in a semiconductor substrate, forming an isolation layer in the field region, and selectively forming a first conductivity type in the active region. Forming a well, forming a second conductivity type region in a predetermined region of the first conductivity type well, forming an access region in a predetermined region of the second conductivity type region, selectively in the active region Forming a second conductivity type well, forming a first conductivity type region in a predetermined region of the second conductivity type well, and having a gate insulating layer on the first conductivity type well and the second conductivity type well Forming two gate electrodes, forming a source / drain region in the semiconductor substrate on both sides of the gate electrode, and applying a back-bias proportional to a power supply voltage in the first conductivity type well. To Saint back-it characterized in that it comprises the step of: attaching a bias generator.

Description

Method of manufacturing semiconductor device with improved static noise margin {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE IMPROVE STATIC NOISE MARGIN}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device with improved static noise margin, and more particularly, to improve the stability of an SRAM cell operated at a wide range voltage supply. Back bias generator (Backbias generator) is attached to the back bias voltage (Vbb) in proportion to the power supply voltage (Vcc) to improve the high voltage operation stability, and also by selectively increasing the substrate doping of the access transistor The present invention relates to a method for manufacturing a semiconductor device having improved static noise margin with improved cell ratio at high voltage.

In general, low voltage slow SRAM (Slow Power Slow SRAM) is used as a portable computer, a memory card, the power supply voltage is becoming a wide area according to the requirements of the market.

Optimized device / circuit and in-line CD variation to create SRAMs that operate reliably over a wide range from low voltage (~ 1.7V) to high voltage (~ 3.3V). Needs to meet very narrow manufacturing process requirements / control requirements, such as minimizing and minimizing process variation. In other words, the design window is very narrow.

1 is a circuit diagram of a conventional high resistance load type SRAM cell.

Conventional SRAM cells, as shown, have first and second pull-up drivers P1 and P2, first and second pull-down drivers N1 and N2, and first and second access transistors N3 and N4. Consists of

The first pull-up driver P1 is connected between the power supply voltage Vcc and the node Nd1, and the first pull-down driver N1 is connected between the node Nd1 and the ground voltage Vss. Gates of the first pull-up and pull-down driver P1 N1 are commonly connected to the node Nd2.

The second pull-up driver P2 is connected between the power supply voltage Vcc and the node Nd2, and the second pull-down driver N2 is connected between the node Nd2 and the ground voltage Vss. The gates of the second pull-up and pull-down drivers P2 and N2 are commonly connected to the node Nd1.

The first access transistor N3 is connected between a bit line BL and the node Nd1, and the second access transistor N4 is connected between a bitbar line / BL and the node Nd2. The gates of the first and second access transistors N3 and N4 are connected to a word line WL.

Here, the PMOS transistor P1 (P2) as the load element is realized by a thin film transistor, and the PMOS transistors P1 and P2 are the first and second pull-down drivers N1 (N2) and access transistors. It is formed through an insulating layer on the silicon substrate on which (N3) (N4) is formed. Load elements P1 and P2 of high resistance load type memory cells are formed on the silicon substrate by the polysilicon over the insulating layer. Forming the load elements P1 and P2 in this manner is for reducing the area of the memory cell.

2 shows a characteristic curve during read operation in an SRAM cell.

Here, A and B represent the stabilization voltage (stable point) of the node (Nd1) and node (Nd2), and when the two stabilization voltages correspond to the node (Nd1) and node (Nd2) and the node (Nd1) and There may be two cases corresponding to the node Nd2, and it is expressed that '0' or '1' is stored in the cell, respectively. That is, in order to maintain the data ("0" or "1") stored in the SRAM cell, the presence of two stabilization voltages denoted by A and B is essential.

On the other hand, the stabilization voltage may be unstable due to external noise, process changes, and asymmetry of the left and right inverters constituting the cell. In this case, when the static noise margin (SNM) becomes zero, the stabilization voltage is no longer formed. As a result, bit line failure occurs. Therefore, the larger the static noise margin (SNM), the better the stability against external noise of the cell.

If the linear slope of the inverter gain is urgent, the inverter gain is high, and if the linear slope is moderate, the inverter gain is low.

3 is a waveform diagram illustrating measured values of a static noise margin according to a conventional power supply voltage.

As shown, when the power supply voltage Vcc starts to increase gradually, the static noise margin also increases proportionally. However, as the power supply voltage (Vcc) increases, the output undervoltage increases proportionally (not linearly), but the inverter gain (output roll-off) because the threshold voltage (Vth) of the driver transistor does not change. The voltage remains almost constant. Therefore, as the power supply voltage Vcc increases, the static noise margin changes to have a fixed value or tend to decrease little by little.

However, the above-described conventional semiconductor device of the SRAM cell has the following problems.

The threshold voltages of the driver and access transistors must be lowered to ensure the cell's read current at low voltages, but at high voltages to prevent deterioration of static noise margin during read operation rather than the cell's read current. To a certain level. Thus, the device design window under wide power supply voltage is very narrow or even impossible.

Accordingly, the present invention has been made to solve the above problems, and in order to improve the stability of the SRAM cell operating at the wide area power supply voltage, a back bias generator is attached to the P well of the cell, which is proportional to the power supply voltage Vcc. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device having improved static noise margin which improves high voltage operation stability by applying a back bias voltage Vbb.

In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device which improves the static noise margin which improves the cell ratio at high voltage by selectively increasing the substrate doping of the access transistor.

1 is a circuit diagram of a conventional high resistance load type SRAM cell.

2 is a graph showing characteristic curves of a read operation in an SRAM cell.

3 is a waveform diagram showing a measured value of a static noise margin according to a conventional power supply voltage

4 is a circuit diagram of a back bias generator used in the present invention.

FIG. 5 shows characteristic curves required in the back bias generator shown in FIG. 4. FIG.

6 is a simulation diagram showing a static noise margin (SNM) of a semiconductor device having an improved static noise margin according to the present invention.

7A to 7E are cross-sectional views illustrating a method of manufacturing a semiconductor device having improved static noise margin according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10 charge pump circuit portion 12 ring oscillator portion

14: charge storage capacitor 20: voltage comparison unit

30: level shifting switch unit

In order to achieve the above object, a method of manufacturing a semiconductor device having improved static noise margin according to the present invention includes: defining an active region and a field region on a semiconductor substrate, and then forming an isolation layer in the field region; Selectively forming a first conductivity type well in the trench, forming a second conductivity type region in the predetermined region of the first conductivity type well, and forming an access region in the predetermined region of the second conductivity type region; And selectively forming a second conductivity type well in the active region, and forming a first conductivity type region in a predetermined region of the second conductivity type well, and above the first conductivity type well and the second conductivity type well. Forming a plurality of gate electrodes having a gate insulating film on the substrate; forming a source / drain region in the semiconductor substrate on both sides of the gate electrode; Generating a back-bias-bag in proportion to is characterized in that it comprises the step of: attaching a bias generator.

The first conductivity type well is p-type, and the second conductivity type well is n-type.

The gate electrode formed in the first conductivity type well may be a gate electrode of an access transistor and a gate electrode of a driver transistor.

The gate electrode formed in the second conductivity type well is a gate electrode of the load transistor.

In forming the access region, the energy is 60 to 80 KeV, the impurities are boron, and the concentration is 2.0 to 4.02E12.

Hereinafter, a semiconductor device for improving a static noise margin according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In order to increase the static noise margin SNM, the point A of FIG. 2 should move to the right and the point B should move to the bottom. To do this, the output roll off voltage of '1', the characteristic curve of the upper inverter (the point at which the Vnode voltage maintains Vcc and starts to fall in curve '1') should move to the right. For this purpose, it is necessary to increase the threshold voltage of the driver transistor. Because the main cause of the roll-off (roll-off) is that the driver transistor is turned on, the output roll-off voltage increases when the voltage to be turned on, that is, the threshold voltage (Vth) increases.

Secondly, the output low voltage (the last point of the curve in FIG. 1) must move downward, which requires increasing the cell rate (driver transistor on current ÷ access transistor on current). This enhances the pull-down capability of the driver transistors, bringing the output row voltage close to 0V. If only one of these two conditions is met, the SNM is improved and the static noise margin (SNM) can be maximized if both conditions are met.

The power supply voltage Vcc dependency of the static noise margin SNM is as follows. First, when the power supply voltage Vcc starts to increase from the lower limit, the static noise margin SNM also increases proportionally. However, as the power supply voltage Vcc increases, the output row voltage increases proportionally (not linearly proportionally). At this time, the threshold voltage Vth of the driver transistor does not change, so the output roll-off voltage (Output Roll-) Off Voltage) maintains a substantially fixed value, so that as the power supply voltage Vcc increases, the static noise margin (SNM) tends to have a fixed value or decrease slightly.

In general, static at low / medium supply voltage (Vcc) in view of the principle that the higher the supply voltage (Vcc), the higher the demand for static noise margin (SNM) for stable cell operation. Even if the requirements of the noise margin SNM are met, the static noise margin SNM may become insufficient at the 'high' supply voltage Vcc. Therefore, in order to improve this, the threshold voltage Vth of the driver transistor increases as the 'high' power supply voltage Vcc increases, and the cell ratio increases to satisfy the condition of increasing the static noise margin SNM described above. . However, if the threshold voltage Vth of the access transistor does not increase together when the threshold voltage Vth of the driver transistor is adjusted upward, the cell ratio decreases and the static noise margin SNM falls, so that the threshold voltage of the access transistor ( Vth) must also be increased to maintain cell rate. However, in the 'low' power supply voltage Vcc, when the threshold voltage Vth of the access transistor increases, the cell current decreases, and in extreme cases, when the power supply voltage Vcc becomes smaller than the threshold voltage Vth of the access transistor, the cell In this case, the threshold voltage Vth of the access / driver transistor should be small at the 'low' supply voltage (Vcc).

The most effective way to meet all of the above conditions is to use a back-bias generator that generates a back bias voltage Vbb proportional to the power supply voltage Vcc.

FIG. 4 is a circuit diagram of a back bias generator used in the present invention, which receives a charge pump circuit portion 10 including a ring oscillator portion 12 and a charge storage capacitor portion 14, and a back bias voltage (-Vbb) to level shift. A level shifting switch unit 30 and a signal obtained by comparing and detecting a back bias voltage (-Vbb) and a reference voltage V _REF received from the level shifting switch unit 30 to the ring oscillator unit 12. The voltage comparison part 20 which generate | occur | produces is provided.

The ring oscillator unit 12 generates a pulse signal of a predetermined period by a signal generated from the voltage comparator 20, and the charge storage capacitor unit 14 generates a pulse generated by the ring oscillator unit 12. The back shift voltage (-Vbb) is pumped to the level shifting switching unit 30 by the signal.

FIG. 5 is a diagram illustrating a characteristic curve required in the back bias generator shown in FIG. 4.

The back bias generator is not very different from the back bias generator used in conventional DRAM or Flash products. However, the back bias generator used in the present invention has a difference in that a back bias voltage Vbb is generated in proportion to the power supply voltage Vcc.

6 is a simulation showing a static noise margin (SNM) of a semiconductor device having an improved static noise margin according to the present invention.

As shown, it can be seen that the static noise margin (SNM) is markedly improved by applying the back bias voltage (Vbb) generator and accessdeep.

The simulation of FIG. 6 shows a first case using a conventional SRAM cell, a second case using a back bias voltage (Vbb) generator with a voltage gain of -0.5 (Vbb = -0.5 Vcc), and a voltage gain of-. In the third case using a back bias voltage (Vbb) generator equal to 1 (Vbb = -Vcc), and in the case of increasing the body factor of the access transistor by 37% for the first to third cases (access Six or more of the above cases, such as a deep implant, are compared, and the static noise margin SNM up to the range (1.2V-5V) of the power supply voltage Vcc is compared with each other. In Figure 6 it can be clearly seen that the static noise margin (SNM) increases in the first to third cases, especially in the 'high' power supply voltage (Vcc) region. In addition, it can be seen that when the body factor of the access transistor is increased by 37% (a curve connected by a line in FIG. 6), further improvement is made.

In addition, it can be further seen in FIG. 6 that the static noise margin (SNM) is improved regardless of the back bias compared to the case of increasing the body factor of the access transistor, i.e., applying the access deep implant. From this, it can be seen that the static noise margin (SNM) can be sufficiently improved by additional processes without design changes in existing products. This is a very likely technology that can be easily applied to all existing SRAM products.

7A to 7E are cross-sectional views illustrating a method of manufacturing an SRAM semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 7A, an active region and a field region are defined in the semiconductor substrate 1, and then the field region is selectively removed to form a trench having a predetermined depth. A first insulating film is deposited on the entire surface of the substrate 1 including the trench, and an etch back or CMP process is performed on the entire surface of the semiconductor substrate 1 so that only the inside of the trench remains. The element isolation film 2 is formed.

As shown in FIG. 7B, the first photoresist 3 is deposited on the entire surface of the semiconductor substrate 1, and the first photoresist pattern 3 is formed using an exposure and development process. 1 The P well region 4 is formed through an impurity ion implantation process using the photoresist pattern 3 as a mask. In this case, an access transistor and a driver transistor to be performed in a later process are formed in the P well region 4.

The N conductive impurity region 5 is formed in the predetermined region of the P well region 4 by implanting N conductive impurity ions using the first photoresist pattern 3 as a mask.

As shown in FIG. 7C, after the first photoresist pattern 3 is removed, the second photoresist 6 is deposited on the entire surface of the substrate, and an area where the access transistor is to be formed is formed by using an exposure and development process. The second photoresist pattern 6 is formed to be exposed.

Subsequently, P conductive impurity ions are implanted using the second photoresist pattern 6 as a mask to form an access impurity region 7. At this time, the P-conductive impurity is boron, 8M slow SRAM energy is 60 ~ 80Kev, the concentration is about 2.0 ~ 4.0E12.

As shown in FIG. 7D, a third photoresist 8 is deposited on the entire surface of the semiconductor substrate 1, and a third photoresist pattern 8 is formed on the P well region 4 using an exposure and development process. N well region 9 is formed through an impurity ion implantation process using the third photoresist pattern 8 as a mask. In this case, a load transistor to be performed in a later process is formed in the N well region 9.

P-conductive impurity ions are implanted using the third photoresist pattern 8 as a mask to form a P-conductive impurity region 10 in a predetermined region of the N well region 9.

As shown in FIG. 7E, the third photoresist pattern 8 is removed, polysilicon is deposited on the entire surface, and then selectively patterned to form a plurality of gate electrodes 11. The spacer sidewall 12 is formed on the side of the gate electrode 11, and then source / drain regions are formed through an impurity ion implantation process.

As described above, in the method of manufacturing a semiconductor device having improved static noise margin according to the present invention, in order to ensure the stability of the SRAM cell at the 'high' power supply voltage Vcc, the NMOS transistor region of the SRAM cell is By applying the back bias voltage to the P well pickup, the static noise margin (SNM) at the 'high' supply voltage (Vcc) can be increased. In addition, if the back bias increases proportionally with the power supply voltage Vcc, the cell stability at the high power supply voltage Vcc may be improved at the same time without degrading the characteristics of the low power supply voltage Vcc. . In addition, when an access deep implant is applied to increase the substrate concentration of the access transistor region, the cell ratio increases as the power supply voltage Vcc is increased, thereby increasing the 'high' power supply voltage (Vcc). There is an advantage to further improve the static noise margin (SNM).

Claims (5)

Defining an active region and a field region in the semiconductor substrate, and forming an isolation layer in the field region; Selectively forming a first conductivity type well in the active region, and forming a second conductivity type region in a predetermined region of the first conductivity type well; Forming an access region in a predetermined region of the second conductivity type region; Selectively forming a second conductivity type well in the active region, and forming a first conductivity type region in a predetermined region of the second conductivity well; Forming a plurality of gate electrodes having a gate insulating layer on the first conductive well and the second conductive well; Forming a source / drain region on the semiconductor substrate at both sides of the gate electrode; And attaching a back-bias generator for generating a back-bias proportional to a power supply voltage to the first conductive type well. The method of claim 1, And said first conductivity type well is p-type and said second conductivity type well is n-type. The method of claim 1, And a gate electrode formed in the first conductivity type well is a gate electrode of an access transistor and a gate electrode of a driver transistor. The method of claim 1, And a gate electrode formed in said second conductivity type well is a gate electrode of a load transistor. The method of claim 1, The method of manufacturing a semiconductor device with improved static noise margin, wherein the energy of the access region is 60 to 80 KeV, the impurities are boron, and the concentration is 2.0 to 4.02E12.