KR100396493B1 - Plasma display panel - Google Patents

Abstract

In a so-called SDR type plasma display panel in which a plurality of R, G, and B cells are surrounded by quadrilateral partitions, and a set of R, G, and B cells are arranged in a triangular shape, an address voltage is supplied to each cell. The address electrodes provided to extend the line width of the portion passing through the inside of the cell are larger than the line width of the portion passing under the partition wall. Optionally, the address electrodes are formed according to the radiation efficiency of R, G, and B phosphors. Line widths of portions passing through the inside of the cell are different for each of the R, G, and B cells. This minimizes the effect of the voltage applied to a specific address electrode on the discharge state of a cell other than the corresponding cell, thereby increasing the address voltage margin and improving the color temperature by adjusting the luminance ratio of each R, G, and B cell. .

Description

Plasma Display Panel {PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel which can improve color temperature by increasing address voltage margin and changing luminance ratio of each R, G, and B cell.

In general, a plasma display panel (PDP) is referred to as a 'PDP' for convenience, and is a display device that implements a predetermined image by using vacuum ultraviolet rays generated by gas discharge for emitting phosphors. It is getting into the spotlight as the next generation thin display device.

The specific structure of the PDP includes a stripe type in which a plurality of R, G, and B cells are partitioned into stripe patterns, and a plurality of R, G, and B cells are surrounded by quadrilateral partitions. Segmented electrodes in Delta color arrayed Rectangular subpixel structure (SDR) types are known in which they are arranged in a triangular shape.

FIG. 8 is an exploded perspective view of the SDR type PDP according to the prior art, and FIG. 9 is a cross-sectional view of the SDR type PDP cut in the x-axis direction in FIG. 8.

On the lower substrate 1 of the illustrated PDP, a plurality of address electrodes 3 arranged in a stripe pattern along the y-axis direction of the drawing, and are formed on the entire lower substrate 1 while covering the address electrodes 3. A dielectric layer 5, a barrier rib 7 having a constant height on the dielectric layer 5 and provided in a quadrangular shape, and R, G, and B applied inside each cell partitioned by the barrier rib 7. The fluorescent layers 9R, 9G, 9B are provided.

On the inner surface of the upper substrate 11, a plurality of bus electrodes 13 are arranged in a stripe pattern along the x-axis direction of the drawing, and a constant discharge gap is directed from the two bus electrodes 13 toward the inside of each cell. A pair of transparent sustain electrodes 15 are formed to extend with a gap therebetween. In addition, the transparent dielectric layer 17 and the protective layer 19 are disposed on the entire surface of the upper substrate 11 while covering the bus electrode 13 and the sustain electrode 15, and all R, G, and B cells have discharge gas inside. Is charged.

According to the above structure, the address discharge is performed by applying a voltage between any one of the sustain electrodes 15, and then a sustain discharge is applied between the two sustain electrodes 15 corresponding to the cell. UV light generated by the excitation of the fluorescent layer provided to the cell emits visible light.

Here, in the above-described SDR type PDP, an address electrode 3 for driving another cell passes under the partition wall 7 that distinguishes each of the R, G, and B cells. It's a big difference.

Thus, for example, when the address voltage Va is applied to the address electrode 3G passing through the G cell to turn on the G cell, the voltage applied to the address electrode 3G is the sustain electrode (the B cell and the R cell). 15) affects the voltage distribution and causes a mis-discharge.

Therefore, in the SDR type PDP, the upper limit of the Va voltage applied to the address electrode 3 is lower than that of the stripe type PDP due to the above-mentioned problems, and the address voltage margin (the upper limit and the lower limit of the Va voltage that can maintain a stable discharge state) is reduced. As the difference is not large, it acts as one cause of difficulty in driving PDP.

On the other hand, the phosphor used in the PDP should be excited at low energy compared with the phosphor of the cathode ray tube which is excited at high energy. Therefore, the phosphor suitable for the PDP has a very limited selection. The known phosphors used in the PDP are R, The luminous efficiency, i.e., the luminance difference, is very different for each of the G and B colors, which makes it difficult to adjust the white balance and the color temperature.

Therefore, as a method for compensating for the luminance difference of each of the R, G, and B cells, in the known stripe type PDP, the widths of the R, G, and B cells are varied according to the luminous efficiency of the R, G, and B phosphors. The different application of the area is disclosed in Korean Laid-Open Patent Publication No. 1996-42809.

However, in the above-described SDR type PDP, since all the cells are completely surrounded by the partition wall 7, the structure becomes very complicated when the size of each cell is applied differently. In particular, the partition wall (while maintaining the distance between the address electrodes 3 remains the same) 7) In the case of changing only the structure, it is expected that the address electrode 3 for driving a specific cell will further affect the discharge state of another cell, so that the misdischarge problem becomes serious.

Accordingly, the SDR type PDP requires a new method for easily compensating the color temperature drop due to the luminance difference of the R, G, and B phosphors without complicated structural changes, and increasing the voltage margin of the address electrode 3.

Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to minimize the effect of the voltage applied to a specific address electrode on the discharge state of a cell other than the corresponding cell, thereby increasing the upper limit of the address voltage, It is to provide a plasma display panel that can increase the voltage margin.

Another object of the present invention is to provide a plasma display panel which can improve the color temperature by easily adjusting the luminance ratio of each R, G, B cell without requiring a complicated structure change.

1 is a partially exploded perspective view of a plasma display panel according to a first embodiment of the present invention.

2 is a cross-sectional view of a plasma display panel according to a first embodiment of the present invention.

3 is a plan view of a lower substrate of the plasma display panel shown in FIG. 1;

4A and 4B are graphs showing address voltage margins measured for R, G, and B cells in a plasma display panel according to the present invention and a plasma display panel according to the related art, respectively.

5 is a plan view of a lower substrate in a plasma display panel according to a second embodiment of the present invention;

6 and 7 are schematic diagrams for explaining another example of the configuration of the address electrode.

8 is a partially exploded perspective view of a plasma display panel according to the prior art.

9 is a sectional view of a plasma display panel according to the prior art;

In order to achieve the above object, the present invention,

First and second substrates, a plurality of address electrodes formed on the first substrate, a dielectric layer formed on the entire surface of the first substrate while covering the address electrodes, and provided at a predetermined height on the dielectric layer. A partition wall which encloses the one address electrode in a quadrangular shape on two other address electrodes centered on the address electrodes of the cell and partitions the plurality of cells so that a set of R, G, and B cells are in a triangular arrangement; A plurality of R, G, B fluorescent layers applied therein and a plurality of sustain electrodes provided in pairs with a predetermined discharge gap therebetween corresponding to each cell on one surface of the second substrate facing the first substrate Include,

The address electrodes provide a plasma display panel in which a line width of a portion passing through the inside of the cell is larger than a line width of a portion passing under the partition wall.

Preferably, the address electrodes are in a range of 40 to 75% of a distance between two partition walls in which a line width of a portion passing through the inside of the cell is parallel to the address electrode in each cell.

Optionally, the address electrodes have different line widths of portions passing through the cells for R, G, and B cells, and line widths of portions passing through the cells satisfy the following ranges.

D _R <D _G <D _B

Here, D _R represents the line width of the address electrode passing through the inside of the R cell, D _G represents the line width of the address electrode passing through the inside of the G cell, and D _B represents the line width of the address electrode passing through the inside of the B cell.

Accordingly, the present invention increases the address voltage margin by minimizing the effect of the voltage applied to a specific address electrode on the discharge state of another cell by increasing the line width of the address electrode passing through the cell, and addressing each R, G, B cell. By changing the line width of the electrode has the advantage of improving the color temperature by adjusting the luminance ratio of the R, G, B cells.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is an exploded perspective view of a plasma display panel according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the plasma display panel cut in the x-axis direction of FIG. 1.

As shown, the plasma display panel according to the present embodiment (hereinafter referred to as 'PDP' for convenience) is divided into a plurality of R, G, and B cells into a rectangular partition wall, and a set of R, G, and B cells are triangular in shape. As a so-called SD (SDR) type arranged in a row, one address electrode 2 and a pair of sustain electrodes 4 are provided corresponding to each cell to independently control light emission of the cell.

More specifically, a plurality of address electrodes 2 are formed on the first substrate of the PDP (hereinafter, referred to as 'lower substrate' 6 for convenience) in a stripe pattern along the y-axis direction of the drawing, and the dielectric layer 8 ) Is formed on the entire surface of the lower substrate 6 while covering the address electrodes 2. A partition 10 is formed on the dielectric layer 8 with a predetermined height to partition a plurality of cells, and a plurality of R, G, and B fluorescent layers 12R, 12G, and 12B are formed inside the cell.

Since the partition wall 10 must enclose one of the address electrodes 2 in a square shape and divide a cell, the set of R, G, and B cells must be arranged in a triangular shape, so that both sides of the partition wall 10 correspond to corresponding addresses. It is disposed on two other address electrodes 2 adjacent to the electrode 2, and the address electrode 2 for driving the other cells passes under the partition 10 forming the boundary of each cell.

On the second substrate of the PDP (hereinafter referred to as 'upper substrate' 14 for convenience), a pair of sustain electrodes 4 are disposed with a constant discharge gap G between each cell region. The field 4 is connected to the bus electrode 16 to receive a voltage, and the sustain electrodes 4 are made of a transparent indium tin oxide (ITO) electrode to transmit light emitted from the fluorescent film 12. The transparent dielectric layer 18 and the MgO protective layer 20 are positioned in front of the upper substrate 14 while covering the sustain electrodes 4 and the bus electrodes 16.

Here, the PDP provided in this embodiment changes the line width of the address electrode 2 in order to increase the address voltage margin. FIG. 3 is a plan view of the lower substrate 6 of the PDP shown in FIG. As shown in FIG. 3, all of the address electrodes 2 have a line width D1 of a portion passing through the inside of the cell larger than a line width D2 of a portion passing under the partition wall 10.

That is, the address electrode 2 passing through the inside of the R cell and the B cell has a line width of D1 and the other address electrode 2 for driving the G cell passing under the partition 10 between the R cell and the B cell. Has a line width of D2. Of course, the address electrode 2 for driving the G cell is also formed at the line width of the D1 inside the G cell.

When the line width of the address electrode 2 is changed in this way, the discharge distribution inside the cell changes. As the line width of the address electrode 2 passing through the cell increases, the potential of the other address electrode 2 provided under the partition 10 increases. The influence on the discharge state of the cell can be reduced.

For example, when 70 V is applied to the address electrode 2 passing through the G cell to turn on the G cell, and 0 V is applied to the address electrode 2 passing through the R cell and the B cell, The R cell and the B cell may increase the area maintaining the 0 V potential due to the enlarged line width of the address electrode 2, thereby reducing the influence of the address voltage of the 70 V potential passing under the barrier 10. . As a result, the R cell and the B cell can maintain a more stable discharge state regardless of whether the G cell is turned on or off.

Therefore, since the PDP provided in this embodiment can increase the upper limit of the address voltage applied to each address electrode 2, the PDP increases the address voltage margin, which is advantageous in driving the PDP.

Here, the line width D1 of the address electrode 2 passing through the inside of the cell is the distance between two partition walls 10 positioned in parallel with the address electrode 2 in each cell, that is, the width of the horizontal width H of the cell interior space. It is preferable that it consists of 40 to 75% of range.

This is because, as a result of the applicant's experiment, when the line width D1 of the address electrode 2 is set to 40% or less of the horizontal width H of the inner space of the cell, it is difficult to achieve a sufficient discharge voltage margin and thus it is difficult to realize stable discharge conditions. This is because when the line width D1 of the address electrode 2 is set to 75% or more of the H, the chance of occurrence of a short with the other address electrode 2 passing under the partition 10 becomes high.

4A and 4B show an address voltage Va margin for the sustain voltage Vs for each of R, G, and B cells in the PDP of the present invention and the PDP according to the prior art, respectively. As a graph measured, the upper curve of the graph indicates the upper limit of the address voltage Va, the lower curve of the graph indicates the lower limit of the address voltage Va, and the upper and lower limits of the address voltage Va. The difference in means the address voltage margin.

In addition, the size of the R, G, and B cells is 720 × 540 μm in both the Examples and Comparative Examples, and the line width D1 of the address electrode 2 passing through the inside of the cell is 300 μm and passes under the partition 10. The line width D2 of the address electrode 2 is 60 m, and in the comparative example, the address electrode has a line width of 60 m as a straight line.

As shown in the graph, the graph of the example shows the result of the address voltage upper limit of the G cell rising and the address voltage lower limit of all the cells of R, G, and B lowering compared with the graph of the comparative example, and the address shown in the comparative example Compared with the margin of the voltage, it can be seen that the address voltage margin of the embodiment increased by about 30 V on average.

On the other hand, increasing the line width of the address electrode 2 passing through the cell as described above increases the brightness of the cell, and the line width of the address electrode 2 passing through the cell for each R, G, B cell is increased. By changing, the luminance ratio of each R, G, B cell can be easily adjusted.

FIG. 5 is a plan view of a lower substrate among the PDPs according to the second embodiment of the present invention. In the present embodiment, the address electrodes 2 are formed in a portion in which the line width of the portion passing through the inside of the cell passes under the partition wall 10. The line width of the address electrode 2 passing through the inside of the R, G, and B cells is different depending on the radiation efficiency of the R, G, and B phosphors.

That is, the line width of the address electrode 2 passing through the inside of the cell is made to satisfy the following equation.

Here, D _R is the line width of the address electrode 2 passing through the inside of the R cell, D _G is the line width of the address electrode 2 passing through the inside of the G cell, and D _B is the address passing through the inside of the B cell. The line width of the electrode 2 is shown.

The maximum line width of the address electrode 2 corresponding to the B cell is set because the radiation efficiency of the B phosphor is the lowest. As the line width of the address electrode 2 is increased, the vacuum ultraviolet rays emitted from the cell are increased. The amount is increased to improve the brightness, and the luminance data measured according to the change of the line width of the address electrode 2 and the discharge sustain voltage Vs is shown in Table 1 below.

Luminance (cd / m ² ) Vs = 170 V Vs = 175 V Vs = 180 V Vs = 185 V Test 1 644.5 673.5 692.5 740 Test 2 692 724.5 743.5 796 % Increase in brightness 7.4 7.6 7.4 7.6

In the table, Test 1 and Test 2 measure the front luminance of three R, G and B cells when the line widths of the address electrodes 2 passing through the R, G and B cells are 200 μm and 300 μm, respectively. As shown in the above table, it can be seen that as the line width of the address electrode 2 increases, the luminance improves. At this time, the horizontal width W of the sustain electrode 4 (shown in FIG. 1) provided corresponding to each cell in the PDP used for the measurement is R = 380 µm, G = 490 µm, and B = 540 µm.

Accordingly, the luminance ratio of the R, G, and B cells can be easily adjusted by changing the line width of the address electrode 2 for each of the R, G, and B cells. As shown in Equation 1, the R, G, and B cells can be adjusted. By varying the line width of the address electrode 2, the luminance ratio of the cells can be improved in the order of B cells, G cells, and R cells.

As a result, it is possible to effectively improve the luminance ratio of the B cell having the lowest emission efficiency of the phosphor, and when the luminance ratio of the B cell is increased by 2 to 3% when the color temperature is substantially improved by adjusting the luminance ratio. The result is that the color temperature is improved to about 10,000K.

Meanwhile, the shape of the address electrode 2 passing through the inside of each cell may be circular and hexagonal as shown in FIGS. 6 and 7 in addition to the rectangular shape shown above. The shape is not limited to that described above.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications and changes can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings. Naturally, it belongs to the range of.

Thus, the present invention increases the address voltage margin by minimizing the effect of the voltage applied to the address electrode on the discharge state of another cell by increasing the line width of the address electrode passing through the cell, thereby driving R. By changing the line widths of the address electrodes for each of the G, B cells, the color temperature can be easily improved by adjusting the luminance ratio of the R, G, B cells.

Claims (5)

First and second substrates; A plurality of address electrodes formed on the first substrate; A dielectric layer formed over the first substrate while covering the address electrodes; It is provided on the dielectric layer at a predetermined height and surrounds one of the address electrodes in a quadrangular shape with respect to one of the address electrodes, and at the same time, a set of R, G, and B cells are arranged in a triangular arrangement. A partition wall partitioning the plurality of cells as much as possible; A plurality of R, G, B fluorescent layers applied inside the cell; And A plurality of sustain electrodes provided in pairs with a predetermined discharge gap therebetween corresponding to each cell on one surface of the second substrate facing the first substrate; And the line electrodes having a line width of a portion passing through the inside of the cell is greater than a line width of a portion passing under the partition wall. The method of claim 1, And the address electrodes have a line width of a portion passing through the inside of the cell in a range of 40 to 75% of a distance between two partition walls in parallel with the address electrodes in each cell. The method of claim 1, And the address electrodes have different line widths of portions of the R, G, and B cells passing through the cells. The method of claim 3, wherein And a line width of the address electrodes passing through the cell to satisfy the following range. Here, D _R represents the line width of the address electrode passing through the inside of the R cell, D _G represents the line width of the address electrode passing through the inside of the G cell, and D _B represents the line width of the address electrode passing through the inside of the B cell. The method of claim 1, And a shape of an address electrode passing through the inside of the cell is rectangular, circular or hexagonal.