KR100396286B1 - Apparatus and method for generating sync word pattern and transmitting and receiving said sync word in w-cdma communication system - Google Patents

Abstract

The present invention provides a synchronous verification method using a pilot pattern in an asynchronous CDMA mobile communication system. For example, when a frame having a 10 ms period consists of 15 slots and pilot symbols exist in each slot, frame synchronization may be confirmed using a pattern in the pilot symbol, that is, a sync word. An object of the present invention is to provide a synchronization verification method in which a correlation value characteristic of a synchronization word has one maximum point and two minimum points per slot offset period. The maximum point of the correlation value indicates that the frame synchronization is correct, and the minimum point indicates that the frame synchronization is shifted by a specific number of slots. Such sync words are generally applicable when the number of slots is 15 or when 2 ^K -1 (K is a positive integer).

Description

Synchronization word generation, transmission and reception device and method of asynchronous code division multiple access communication system

The present invention is to generate and verify the sync word of the code division multiple access communication system The present invention relates to an apparatus and a method, and more particularly, to an apparatus and a method capable of generating and verifying a sync word of an asynchronous code division multiple access communication system.

Currently, standardization work for 3G mobile communication is actively underway, and efforts are being made to integrate global mobile communication into one.

In particular, harmonization between North American synchronous code division multiple access (hereinafter referred to as cdma2000) and European asynchronous code division multiple access (hereinafter referred to as W-CDMA) has been accelerated. In the above integration process, the possibility of recently adjusting the chip rate of the asynchronous W-CDMA to 3.84 Mcps at 4.096 Mcps (chip per sec). Therefore, in the case of W-CDMA operating at a chip rate of 4.096 Mcps, it is necessary to redesign some parts of the system to reduce the chip rate to 3.84 cps / 4.096 cps, or 15/16 times. That is, the conventional asynchronous code division multiple access communication system is composed of 16 slots in one frame, but the number of integrated asynchronous code division multiple access communication system will be composed of 15 slots. Therefore, in the integrated asynchronous code division multiple access communication system, a method of optimizing the number of slots to 15 slots per frame without changing the structure of each slot is considered as an optimization design. Therefore, integration between cdma 2000 and W-CDMA is considered. In order to change the number of slots constituting the frame of the asynchronous code division multiple access communication system, one of the parts requiring design change is a pilot sync word pattern used for frame synchronization verification.

In addition, among the technologies of the conventional asynchronous code division multiple access communication system, the W-CDMA wireless communication standard, which is underway in the 3rd Generation Partnership Project (3GPP) as of May 1999, includes a technique of verifying synchronization of a frame using a sync word. It is. The sync word in the prior art is designed on the assumption that one frame consists of 16 slots. However, as discussed above, a new design is now under discussion, with the number of slots currently changing from 16 to 15 per frame. At this time, if the number of slots per frame is 15, the conventional 16-slot synchronous verification method cannot be applied to a system using 15 slots per frame. Therefore, when the number of slots per frame is 15, a new synchronous verification method must be designed accordingly.

Accordingly, an object of the present invention is to provide an apparatus and method for generating a synchronization word in an asynchronous code division multiple access communication system. Another object of the present invention is to divide one frame into 15 slots and each slot is a plurality of slots. An apparatus and method for generating a frame sync word in an asynchronous code division multiple access communication system divided into sync bits are provided. Another object of the present invention is to synchronize a frame sync word in an asynchronous code division multiple access communication system. Provides a device having a first correlation value and generating a synchronization word having a second correlation value different from the first correlation value at at least two positions in which synchronization occurs by a specific slot in the frame section. Another object of the present invention is to achieve a synchronization of frame sync words in an asynchronous code division multiple access communication system. A first correlation value in which a correlation value is maximized, a second correlation value in which the correlation value is minimum at at least two positions in which the frame synchronization word is shifted by a specific slot in the frame section, and the frame synchronization word The present invention provides an apparatus and method for generating a sync word having a third correlation value different from the first and second correlation values at a position where synchronization is lost when the two conditions are not satisfied.

Another object of the present invention Synchronization word generator of asynchronous code division multiple access communication system 2 length^KGenerating a frame sync word by generating at least two sequences of -1 (K is a positive integer), the frame sync word generating a first correlation value that is maximum when frame sync is performed, and the frame sync being performed A second correlation value that is minimum when offset to two specific slot intervals in a non-supporting state, and has a third correlation value at slot positions other than the positions of the slots when the frame synchronization is not performed An apparatus and method for generating a sync word are provided.

It is still another object of the present invention to provide at least two sequences in an asynchronous code division multiple access communication system, generating a first correlation value having a maximum point when the sequences coincide with a starting point, and a minimum point at two specific offsets. The present invention provides a device and method for generating a second correlation value with and generating and transmitting a sync word having a third correlation value at an intermediate position at remaining offsets.

Another object of the present invention is to generate a first correlation value having a maximum point when a transmitting side matches a start point in a code division multiple access communication system, and generate a second correlation value having a minimum point at two specific offsets. The present invention provides an apparatus and method for transmitting data using a sync word having a third correlation value of an intermediate position at the remaining offsets, and allowing a receiver to acquire frame sync at the receiver by using the sync word.

In a code division multiple access communication system according to an embodiment of the present invention for achieving the above object, a synchronization word generation device for performing frame synchronization using a synchronization word of each slot includes one frame having 15 slots. Having at least two sequences of 15, the sequences generating a first correlation value having a maximum point when the starting points match, generating a second correlation value having a minimum point at two specific offsets, and remaining offsets Generates a sync word having a third correlation value at an intermediate position.

In order to achieve the above object, each frame of a series of frames is divided into a given plurality of slots, each slot having a plurality of sync symbols, and a sync word of the frame consists of sync symbols of the respective slots. The apparatus for generating the frame synchronization word in a code division multiple access communication system has a first correlation when the reference frame is synchronized with the received two frames, and at predetermined intervals of a plurality of given slots of each reference frame. Sequence generators for generating sequences of at least two sync symbols each having a second correlation value different from the first correlation value whenever a start slot of each received frame is located at each of the divided at least two slot division points; And multiplexing respective sync symbols generated from the sequence generators, each slot of the slots And a selector having corresponding multiplexed sync symbols.

In addition, in order to achieve the above object, each frame of the series of reference sync frames and the receive sync frames is divided into a plurality of slots, each slot is divided into a plurality of bits, and each frame is a sync word. And a device for synchronizing the series of receive synchronization frames to the series of reference synchronization frames, wherein the apparatus has a first correlation when the reference synchronization frames and the synchronization frame of synchronization are matched with each other. The frame sync word is set to have second correlation values different from the first correlation value whenever a start frame of each reception synchronization frame is located at each of at least two slot division points divided by a given interval of a plurality of slots. A sync word generator for providing a sync word extractor for extracting a frame sync word from the received frame information, And a frame synchronization verifier for verifying frame synchronization by calculating a correlation value between the extracted frame synchronization word and the provided synchronization word.

1A-1C illustrate the concept of frame synchronization in an asynchronous code division multiple access communication system.

2A through 2D are diagrams illustrating slot structures of respective channels in an asynchronous code division multiple access communication system.

3A through 3H are diagrams illustrating a pilot structure of each channel in an asynchronous code division multiple access communication system.

4A through 4C are diagrams showing sync words of respective slots in an asynchronous code division multiple access communication system.

FIG. 5 is a diagram illustrating a relationship between a frame, a slot, a pilot, and a sync word having the structure shown in FIG. 1 to FIG. 4.

6 is a diagram illustrating a sync word form used in an asynchronous code division multiple access communication system according to an embodiment of the present invention.

7 is a flowchart illustrating a process of generating a sync word according to an embodiment of the present invention.

8 illustrates a correlation characteristic of a sync word having the same structure as in FIG. 6 according to an embodiment of the present invention.

9 is a diagram showing the structure of a transmitting apparatus of an asynchronous code division multiple access communication system according to an embodiment of the present invention.

10 is a diagram showing the structure of a receiving apparatus of an asynchronous code division multiple access communication system according to an embodiment of the present invention.

FIG. 11 is a diagram illustrating an implementation example of a sync word generator in a receiving device having the structure as shown in FIG. 10.

FIG. 12 is a diagram illustrating an implementation example of a sync word generator according to another embodiment in a receiving device having the structure as illustrated in FIG. 10.

13A and 13B illustrate a structure of a frame synchronization verifying apparatus in a receiving apparatus having the structure as shown in FIG.

FIG. 14 is a flowchart illustrating a process of verifying and obtaining frame synchronization in a receiving apparatus having the structure as shown in FIG. 10.

Verifying the synchronization word pattern and the synchronization according to an embodiment of the present invention is a technique that can be applied to the CDMA mobile communication system, in particular, a technique suitable for a CDMA mobile communication system of the asynchronous (base station) between base stations. The specific technical field relates to a method of using a sync word for synchronous verification. Here, the sync word means a bit string of a predetermined pattern which is preset and known to both the transmitter and the receiver. The information on the sync word pattern is generally determined in advance and stored in the transceiver. However, the sync word pattern may be generated during actual operation or exchanged between the transceivers.

In addition, synchronization can be divided into PN chip synchronization, slot synchronization, and frame synchronization, which means that a signal transmitted from a transmitter in units of PN chips, slots, and frames, and a receiver's operation of the signal in time To match. In particular, an embodiment of the present invention provides a method and apparatus for generating a sync word for verifying synchronization of a frame which is a basic transmission unit. In this case, the frame synchronization verification is a procedure that is performed after PN chip synchronization, slot (division of frame) synchronization, and frame synchronization are acquired. In order to verify the synchronization of the frame as described above, the transmitter transmits a bit string having a specific pattern for each slot in the frame, that is, a sync word, and obtains a correlation value between the received sync word and the sync word generated at the receiver. It is determined whether the frame is synchronized. After determining whether the frame is synchronized, if synchronization is not corrected, a process for synchronization is performed. If synchronization is corrected, information is obtained by demodulating and decoding the received frame. The above operation will be described later with reference to FIG. 14.

First, let's look at the operation of frame synchronization. 1A to 1C are diagrams for explaining the concept of frame synchronization in an asynchronous code division multiple access communication system. 1A to 1C show slot numbers 1 to 15, and shows a case in which 15 slots constitute one frame.

1A, 1B, and 1C, the upper part of the frame represents the time of the received frame sync word, and the lower part of the frame represents the time of the frame sync word generated by the receiver itself. In this case, FIG. 1A illustrates a case in which synchronization between two frames is matched by matching the reception time of the frame synchronization word transmitted by the transmitter with the time of the frame synchronization word generated by the receiver. 1B and 1C illustrate an example in which the synchronization time between the two frames is inconsistent because the reception time of the frame synchronization word transmitted from the transmitter and the frame acquired by the receiver are different from each other. Here, as shown in FIGS. 1B and 1C, it is assumed that slot synchronization is correct (that is, slot boundaries coincide) even if the frame is not synchronized. As shown in FIGS. 1B and 1C, when the frame synchronization is shifted by an integer multiple of the slot, the offset unit size is defined as the offset. For example, FIG. 1A illustrates an offset of 0, FIG. 1B of an offset of +1, and FIG. 1C of an offset of -5. When the offset is 15 or a multiple of 15, it can be regarded as the case where the offset is 0. In this case, the offset of-may be treated in the same manner as the offset of + depending on the periodic nature.

2A to 2D are diagrams illustrating the position and number of bits in a pilot slot for each channel according to an ongoing 3GPP W-CDMA radio standard. Here, the pilot in each channel is a signal that is spread and transmitted without modulation, and is a signal that can be used for channel estimation, that is, a reference for synchronous demodulation.

FIG. 2A illustrates a slot structure of an uplink dedicated physical control channel (DPCCH). The pilot is located at the front of each slot and occupies 5, 6, 7, or 8 bits. FIG. 2B illustrates a slot structure of a downlink dedicated physical channel (DPCH), which is a downlink dedicated physical channel. The pilot is located behind the slot and occupies 4, 8, or 16 bits. FIG. 2C illustrates a slot structure of a downlink primary common control physical channel (PCCPCH) channel. The pilot is located at the rear of the slot and occupies 8 bits. FIG. 2D illustrates a slot structure of a downlink secondary common control physical channel (SCCPCH) channel, wherein the pilot is located behind the slot and occupies 8 or 16 bits.

Some of the bits of the pilot having the structure shown in FIGS. 2A to 2D may be used to form a sync word. Herein, bits included in one slot of bits used to form the sync word (hereinafter, referred to as sync bits) will be defined as a sync symbol. Then, each sync bit is gathered to form one sync symbol in one slot, and the sync symbols of each slot are gathered in one frame to form a sync word.

3A to 3H are diagrams illustrating a structure of bits used as frame sync symbols among pilot bits included in a specific slot of each channel applied to an ongoing 3GPP W-CDMA radio standard. The bits shown in white in FIGs. 3A to 3H are pilot bits having the same value in each slot (that is, bits which are not part of a sync word among pilot bits included in one slot: The bits shown in dark color are pilot bits having a special value for each slot (i.e., sync bits used for frame synchronization verification, bits forming a sync word among pilot bits: ) Is shown. All or part of the pilot bits may be used for channel estimation.

3A to 3D illustrate a case in which 4 bits each of 5, 6, 7, and 8 bits are used as sync bits in one slot of an uplink DPCCH. 3E and 3F illustrate a case in which two bits are used as sync bits, respectively, of a 4-bit pilot and a 4-bit diversity pilot in one slot of the downlink DPCH. FIG. 3G is a diagram illustrating a case where 4 bits of 8-bit pilots are used as sync bits in one slot of DPCH, PCCPCH, or SCPPCH in the downlink. FIG. 3H illustrates a case in which 8 bits of 16-bit pilots are used as sync bits in one slot of the DPCH or SCCPCH of the downlink.

As shown in FIGS. 2A-2D and 3A-3H, the position and number of sync bits among pilot bits are an example implemented to help an understanding of an embodiment of the present invention. It should be noted that many combinations are possible in addition to the structures shown in FIGS. 2A-2D and 3A-3H, and the present invention can be easily applied to other types of bit arrangements.

In the embodiment of the present invention, as described above, in the asynchronous code division multiple access communication system in which one frame consists of 15 or 2 ^P -1 slots (P is a positive integer), a sync word pattern generally applied And a method and apparatus for generating such a sync word pattern. In the embodiment of the present invention, for convenience of description, it is assumed that the number of slots of one frame is 15.

4A to 4C are diagrams illustrating a structure of a sync word by extracting sync bits of respective slots within a frame including 15 slots.

4A illustrates that a sync word is composed of sync symbols of 30 (= 2 * 15) bits in one frame when the sync symbol included in one slot consists of 2 bits. 4B illustrates that a sync word is composed of sync symbols of 60 (= 4 * 15) bits in one frame when the sync symbol included in one slot is composed of 4 bits. FIG. 4C shows that a sync word is composed of 120 (8 * 15) bit sync symbols in a frame composed of 8 bits of a sync symbol in one slot. The sync words having the structure shown in FIGS. 4A to 4C are repeated every frame.

5 is a diagram illustrating a relationship between a frame, a slot, a pilot, and a sync word having the above structure. FIG. 5 illustrates an uplink DPCCH using a 6-bit pilot signal as shown in FIG. 3B. Referring to FIG. 5, one frame includes 15 slots as shown in FIG. 1, as shown in FIG. 5A, and one slot includes pilot and information data, as shown in FIG. 5B. The pilot consists of the synchronization bits that make up the sync word and the general pilot bits that are not part of the sync word.The sync word, like (5d), is a sync such as (5c) in one frame, such as (5a). It is made up of bits.

FIG. 6 is a diagram illustrating a pattern of sync words generated according to an embodiment of the present invention, and assumes a 60-bit sync word.

Referring to FIG. 6, when the number of sync bits per slot, that is, the number of bits of a sync symbol is N, the period of the sync word (hereinafter referred to as sync word length) is 15N. Therefore, as shown in FIG. 5, when N is 4, the sync word length is 60 bits.

As shown in Fig. 6, the sync word is composed of N sequences having a period of 15. Each sequence consists of sync bits at the same position in the slots of a frame, so the period is 15 equal to the number of slots.

If the i th element of the n th sequence of the N sequences is S _n (i), the synchronization symbols of the slots are shown in Table 1 below.

The synchronization symbols of the first slot are S ₁ (1), S ₂ (1), ..., S _N (1) The synchronization symbols of the second slot are S ₁ (2), S ₂ (2), ... , S _N (2) Synchronization symbols in slot 3 are S ₁ (3), S ₂ (3), ..., S _N (3) Synchronization symbols in slot 4 are S ₁ (4), S ₂ ( 4), ..., S _N (4) Synchronous symbols in slot 5 are S ₁ (5), S ₂ (5), ..., S _N (5) Synchronization symbols in slot 6 are S ₁ ( 6), S ₂ (6), ..., S _N (6) The sync symbol of the seventh slot is S ₁ (7), S ₂ (7), ..., S _N (7) Synchronization symbols are S ₁ (8), S ₂ (8), ..., S _N (8) .Synchronization symbols in slot 9 are S ₁ (9), S ₂ (9), ..., S _N ( 9) The synchronization symbols of the 10th slot are S ₁ (10), S ₂ (10), ..., S _N (10) The synchronization symbols of the 11th slot are S ₁ (11), S ₂ (11),. .., S _N (11) Synchronous symbols in slot 12 are S ₁ (12), S ₂ (12), ..., S _N (12) Synchronous symbols in slot 13 are S ₁ (13), S ₂ (13), ..., S _N (13) The sync symbol of slot 14 is S ₁ (14), S ₂ (14), ..., S _N (14) Sync symbol of slot 15 is S ₁ (15), S ₂ (15), ..., S _N (15)

In this case, since the value of N is 4, the sync word is shown in Table 2 below.

The sync symbol of the first slot is S ₁ (1), S ₂ (1), S ₃ (1), S ₄ (1). The sync symbol of the second slot is S ₁ (2), S ₂ (2), S ₃ (2), S ₄ (2) The 3rd slot sync symbol is S ₁ (3), S ₂ (3), S ₃ (3), S ₄ (3) 4th slot sync symbol is S ₁ ( 4), S ₂ (4), S ₃ (4), S ₄ (4) Synchronization symbols in the 5th slot are S ₁ (5), S ₂ (5), S ₃ (5), S ₄ (5) The synchronization symbols of the sixth slot are S ₁ (6), S ₂ (6), S ₃ (6), and S ₄ (6). The synchronization symbols of the seventh slot are S ₁ (7), S ₂ (7), S ₃ (7), S ₄ (7) 8th slot sync symbol is S ₁ (8), S ₂ (8), S ₃ (8), S ₄ (8) 9th slot sync symbol is S ₁ ( 9), S ₂ (9), S ₃ (9), S ₄ (9) Synchronization symbols in the 10th slot are S ₁ (10), S ₂ (10), S ₃ (10), S ₄ (10) The synchronization symbol of the 11th slot is S ₁ (11), S ₂ (11), S ₃ (11), S ₄ (11) The synchronization symbol of the 12th slot is S ₁ (12), S ₂ (12), S ₃ (12), S ₄ (12) Sync symbol of the 13th slot is S ₁ (13), S ₂ (13), S ₃ (13), S ₄ (13) Sync symbol of the 14th slot is S ₁ ( 14), S ₂ (14), S ₃ (14), S ₄ The synchronization symbol of the 15th slot is S ₁ (15), S ₂ (15), S ₃ (15), and S ₄ (15).

The method can be described as follows.

Procedure 1. Repeat the procedure 2 below as shown in slot numbers i = 1 to 15.

Step 2. Repeat Step 3 from bit number n = 1 to N in the slot.

Procedure 3. Output the sync bit S _n (i).

Referring to the synchronization word generation process as described above, it is performed in the procedure shown in FIG.

Referring to FIG. 7, when the sync word generation operation is started, slot index i is set to 1 in step 711, and sync index n in the slot is 1 in step 713. In operation 715, the synchronization bit S _n (i) is output, and in operation 717, the synchronization index n is increased by one. If the sync index n is greater than 4 in step 719, the process proceeds to step 715. Otherwise, the process proceeds to step 721 to increase the slot index i by one. If the slot index i is greater than 15 in step 723, the process returns to step 711, initializes the slot index i to 1, and repeats the sync word generation operation as described above. Otherwise, the process returns to step 713 to synchronize the next slot. After generating the synchronization index n to 1 to generate the bits, the above operation is repeated.

The sync word may be generated by a combination of several sequences in the above manner or may be generated by viewing the entire sync word as one sequence. The sync word is made to have a correlation characteristic that is easy for sync detection.

The sync word generated by the process as shown in FIG. 7 shows the autocorrelation value characteristic as shown in FIG. 8 according to the characteristic thereof.

Referring to FIG. 8, when using the sync word as described above, if the frame sync is correct as shown in FIG. 1A (i.e., the offset is a multiple of zero or 15), the autocorrelation value of the sync word is 15N, That is, the first correlation value 811 is shown. If the frame synchronization is not correct (i.e., the offset is not a multiple of 15), the autocorrelation value of the sync word is the third correlation value 813, which is a value between the maximum and minimum points depending on the offset, or the autocorrelation value is minimum. It becomes the 2nd correlation value 812 which becomes point -P. Where P is a number greater than zero. The case where the correlation value becomes the minimum correlation value -P appears at two positions among the 15 possible offsets, and in the embodiment of the present invention, the offset value is 5 and 10.

Sequences constituting a sync word having the characteristics as shown in FIG. 8 can be obtained as follows.

First, the autocorrelation property is examined for all sequences of length 15, that is, 32768 sequences. This gives 572 types of correlation properties. At this time, two correlation type pairs in all cases among the 572 correlation types are selected, and correlation values for each offset are added, and the correlations at offsets other than the minimum number of minimum points and the minimum correlation value are added. Choose a form pair where the absolute value of the value is as small as possible. Table 3 below shows the sequence of length 15 constituting the pair of shapes to be selected in the above process and the corresponding correlation form. As shown in Table 3 below, since there are many sequences having the same type of correlation value, Table 5 below shows each of the sequences having each type of correlation value.

Can heat Correlation type (offset 0-14) S ¹ 110110110000000011011011000000001101101100000000110110110000000011011011000 15, 3, -1, 7, -1, -5, -1, -5, -5, -1, -5, -1, 7, -1, 3 S ² 111010101110000111100010101000011101010111000101010001111000011110001010100 15, -1, 3, -9, -1, -5, 3, 3, 3, 3, -5, -1, -9, 3, -1 S ³ 111010011000000110010111000000011101001100000011001011100000001110100110000 15, 3, -1, -1, -1, -5, -1, 3, 3, -1, -5, -1, -1, -1, 3 S ⁴ 101011011001000100110110101000110110101000100110111010100100010101101100100 15, -5, -1, 3, 3, -5, -1, -1, -1, -1, -5, 3, 3, -1, -5

Referring to Table 3, the sequences S ¹ and S ² , S ³ and S ⁴ are correlation diagram pairs selected in the process of finding the sequences described above, respectively. In the case of S ¹ and S ² , the correlation form for each offset is [15, 3, -1, 7, -1, -5, -1, -5, -5, -1, -5,- 1, 7, -1, 3] and [15, -1, 3, -9, -1, -5, 3, 3, 3, 3, -5, -1, -9, 3, -1] It can be seen that. And if you add it by each term, it can be seen that it becomes [30, 2, 2, -2, -2, -10, 2, -2, -2, 2, -10, -2, -2, 2, 2]. . Accordingly, in FIG. 8, the correlation value at the multiple slot offset of 0 or 15 is the first correlation value having the maximum point of 15. The correlation value at the offset of the fifth and tenth slots is a minimum of −10. It can be seen that the second correlation value having a point, and the correlation value for the offsets of the remaining slots is 2 or -2, has a third correlation value with a very low absolute value.

In the case of S ³ and S ⁴ , the correlation form for each offset is [15, 3, -1, -1, -1, -5, -1, 3, 3, -1, -5,- 1, -1, -1, 3] and [15, -5, -1, 3, 3, -5, -1, -1, -1, -1, -5, 3, 3, -1,- 5]. And if you add this by each term [30, -2, -2, 2, 2, -10, -2, 2, 2, -2, -10, 2, 2, -2, -2] also the fifth and 10 Only at the first offset, the correlation has a minimum point of -10, and the correlation for the remaining offsets is 2 or -2, which is very low in absolute value.

In this case, if the multiple shape pairs are selected again by returning to the above process, selecting two correlation shape pairs among the correlation shape of the shape pairs and adding the correlation values for each offset are shown in FIG. 8. Frame sync words having correlation characteristics can be found. In this case, when the frame sync word is configured by using the sequences S ¹ and S ² and S ³ and S ⁴ as shown in Table 3, the slot offset is 0 within the interval of 1 frame including 15 slots. Has a maximum correlation value (first correlation value: “30” in this case), and has a minimum correlation value (second correlation value: “-10” in this case) when the slot offset is 5 or 10, except for the above case. Slot offset positions have different correlation values (third correlation value: here "2" or "-2").

Referring to the form pairs described above, the sequence S ¹ , S ² , S ³ , and S ⁴ are correlation pairs selected in the process of finding the sequence described above, respectively. In this case, the correlation shape pairs for each offset are [30, 2, 2, -2, -2, -10, 2, -2, -2, 2, -10, -2, -2, 2, 2] and [30, -2, -2, 2, 2, -10, -2, 2, 2, -2, -10, 2, 2, -2, -2]. And adding this for each term represents the above correlation. That is, in this case, when the four sequences shown in Table 3 are alternately outputted for each term, a sequence constituting a synchronization word having a length of 60 having the above correlation characteristics is obtained.

Here, the sync word is an example consisting of four bits per slot, but as shown in FIG. 3, the sync word may be composed of bits such as 2, 4, and 8 per slot. In this case, when the sync word per slot is composed of 2 bits, any one of the sequences S ¹ and S ² or S ³ and S ⁴ having the characteristics of a correlation type pair may be selected and used. When the sync word per slot is composed of 4 bits, any one sequence may be selected and used from the sequences S ¹ , S ² , S ³ , and S ⁴ , and the sequences S ¹ and S ² or Any two sequences from S ³ and S ⁴ may be selected and used. In addition, when a sync word consists of 8 bits per slot, any two sequences may be selected and used among the sequences S ¹ , S ² , S ³ , and S ⁴ , and the sequences S ¹ and S ² may be used. Alternatively, any four sequences each of S ³ and S ⁴ may be selected and used.

In addition, the sequences shown in Table 3 have the correlation characteristics as shown in FIG. 8 even when delayed in the same bit unit. That is, even when the S ¹ and S ² sequences are delayed in the same bit unit or the S ³ and S ⁴ sequences are delayed in the same unit, they have the same correlation characteristics according to the offset of the sequence. Therefore, the delayed sequences (S ¹ and S ² or S ³ and S ⁴ ) having the characteristics of the correlation type pair at the output terminal of the sync word generator 1023 have the characteristics as shown in FIG. Sync words can be generated.

Therefore, in the case of using the synchronization word having the structure as shown in Table 3, when the synchronization word generated by the receiver and the synchronization word of the received frame are received as shown in FIG. 1A and the frame synchronization is matched (slot offset is 0 or 15). In the case of a multiple of), as shown in 811 of FIG. 8, the first correlation has a correlation value of 15N. However, when the frame synchronization does not match as shown in FIG. 1B or 1C, the correlation value does not have the first correlation value 811. In this case, as shown in FIG. 1B, when the slot offset is not a multiple of 0 or 5, the correlation value becomes 0 as shown in 813 of FIG. 8, and the slot offset is 5 slots or 10 slots. Like 812 of 8, the correlation value has a second correlation value whose specific value is -P. That is, in the case of using the sync word as described above, when the frame sync is not matched, it has a different correlation value according to the slot offset.

That is, when the receiving apparatus verifies frame synchronization, first, the correlation value is detected, and the detected correlation value is analyzed to determine whether the frame is synchronized. At this time, when the detected correlation value has the first correlation value 811, it is determined that frame synchronization is correct. However, when the detected correlation value has the third correlation value 813, the correlation value in the next slot is detected while moving by one slot. When the second correlation value 812 is detected while the correlation value is detected by moving one slot as described above, the frame synchronization is verified by shifting the slot by five slots until the first correlation value 811 is detected. Therefore, by using the synchronization word having the above correlation value characteristics, it is possible to improve the reliability when determining whether to synchronize the frame, and if the frame synchronization is not synchronized, the relationship between the first correlation value and the second correlation value Can be used to quickly synchronize.

Hereinafter, a configuration and an operation of an apparatus for transmitting and receiving a sync word in an asynchronous code division multiple access communication system using a sync word generated according to an embodiment of the present invention will be described.

9 is a diagram showing the configuration of a data channel transmitter for generating and transmitting a sync word according to an embodiment of the present invention. The transmitter as shown in FIG. 9 may be a transmitter of a base station or a mobile station.

Referring to FIG. 9, the sync word generator 911 is an apparatus for generating the sync word, which will be described in detail with reference to FIGS. 12 and 13. The sync word generator 911 is a device for generating the sync word and outputs a sync symbol composed of N sync bits for each slot. That is, the sync word generator 911 outputs a sync word composed of 15N sync bits per frame. The controller 921 generates a first selection signal sel1 for selecting sync bits and general pilot bits output from the sync word generator 911 in each pilot section of the slot, and also selects pilot and other data in the slot section. 2 Generates the selection signal sel2. That is, the information of the pilot interval used according to the channels of the corresponding link of the uplink and the downlink are different as shown in FIGS. 3A to 3H. Accordingly, the controller 921 generates a first selection signal sel1 for selecting sync bits and general pilot bits to be inserted into pilot periods of respective slot periods of a corresponding channel, wherein the controller 921 generates a first selection signal sel1 in the pilot period by the first selection signal sel1. The selected pattern of sync bits and general pilot bits is any of the patterns of FIGS. 3A-3H. In addition, the information of the pilot section selected as described above is inserted in the slot section according to the corresponding channels of the uplink and downlink, respectively, as shown in Figs. 2a to 2d. Accordingly, the controller 921 generates the second selection signal sel2 for selecting a position to which the pilot information is inserted and transmitted in each slot section of the corresponding channel, wherein the second selection signal sel2 generates the second selection signal sel2. The position pattern is any one of FIGS. 2A-2D. The first selector 913 multiplexes the sync bits and the general pilot bits output from the sync word generator 911 by the first select signal sel1 of the controller 921 in a pattern of a corresponding channel in FIGS. 3A to 3H. . The second selector 915 selects data different from the pilot output from the first selector 913 according to the second select signal sel2 of the controller 921 to change the data of the corresponding channel among the patterns of FIGS. 2A to 2D. Multiplex with and output. The first selector 913 and the second selector 915 may use a multiplexer. A spreader 917 spreads and outputs slot information having a structure as shown in FIG. 2 output from the second selector 915.

Here, the transmitter of the base station includes a data channel transmitter and the like in addition to the synchronization channel transmitter. The synchronization channel may transmit synchronization information using first and second synchronization channels, and may also transmit synchronization information using only the first synchronization channel. The structure and operation of such a sync channel transmitter are disclosed in 1999 Patent Nos. 15322 and 18921, filed earlier by the present applicant.

10 is a diagram illustrating a configuration of an apparatus for receiving sync words generated according to an embodiment of the present invention. The receiving device having the above structure may be a mobile station or a base station device. In FIG. 10, the sync word generator 1023 has the same configuration as that of the sync word generator 911 of FIG. 9, and the generated sync words have the same characteristics.

The synchronizer 1013 of FIG. 10 is a device for obtaining PN chip, slot, and frame synchronization of a received signal and may acquire synchronization in a three-step or two-step manner. Such a motivator 1013 is disclosed in detail in 1999 Patent Application Nos. 15152 and 18921 filed by the applicant. The configuration of the synchronizer as described above may be a mobile station or a base station apparatus. The synchronization unit 1013 according to the embodiment of the present invention provides the timing control signal and the state information of the synchronization word to the synchronization word generator 1023 in the receiving device from the obtained synchronization. The timing control signal controls the timing of output of the sync word generator 1023. In addition, the state information of the sync word is information for indicating a position that the sync word generator 1023 should output at one time on the sync word.

Referring to FIG. 10, the sync word generator 1023 receives timing control signals for generating sync words and status information of the sync words from the sync unit 1013, and under the control of the sync word generation controller 1021, the characteristics of FIG. Generates a sync word with The sync word generated by the sync word generator 1023 is used as information for achieving frame synchronization compared with the sync words of the frame information received by the receiver.

11 and 12 are diagrams for describing a relationship between a sync word generator 1023 and a peripheral device according to an exemplary embodiment of the present invention. The period of the sync word sequence generated by the sync word generator 1023 is 15 slots in one frame, and 15N sync bits are output in one frame period. Therefore, the resulting sync word has the pattern shown in FIG. 6 and the characteristics shown in FIG.

FIG. 11 shows an example in which the sync word generator 1023 is configured with a memory for storing sync words. Referring to FIG. 11, the sync word generator 1023 receives size information N of a sync word output from the sync word generation controller 1021, and corresponds to a length corresponding to the size information of the sync word (ie, N bits per slot). 15N bits per frame are accessed and output as N sync bits per slot. In addition, the sync word generator 1023 receives timing control signals and state information of the sync word from the sync unit 1021, and outputs sync bits of the sync word according to a given time and sync word in accordance with positions according to states.

12 shows a configuration of another type of sync word generator 1023 according to an embodiment of the present invention. 12 shows an example in which the sync word generator 1023 stores a sequence of sync words, and this structure stores the necessary sequences in a memory and outputs them as needed.

In FIG. 10, the despreader 1011 despreads the signals of the received channel using the synchronization information output from the synchronizer 1013. The multiplexing controller 1015 generates a multiplexing control signal for separating and selecting pilot and other data from slot signals received in the structure shown in FIG. 2. The demultiplexer 1017 demultiplexes pilot and other data having a structure as shown in FIG. 3 in a slot despread by the selection signal output from the controller 1015. Here, the demultiplexer 1017 performs the reverse operation of the second selector 915 in the transmission apparatus having the structure as shown in FIG. 9. The sync word extractor 1019 extracts sync bits, which are pilot bits used for a sync word, from a pilot signal having the structure as shown in FIG. That is, the sync word extractor 1019 extracts the sync bits of the blackened part of the pilot bits shown in FIG. 3. The sync word extractor 1019 performs a reverse function of the first selector 913 in the transmitter, and the operation of the sync word extractor 1019 may be performed under the control of the controller 1015.

The frame sync verifier 1025 verifies the frame sync by inputting the sync bits output from the sync word extractor 1019 and the sync words generated from the sync word generator 1023. Fig. 13A shows a configuration example of the frame synchronization verifier 1025. In the embodiment of the present invention, that is, an example of using two thresholds TH1 and TH2 is assumed. In this case, the frame synchronization verifier 1025 calculates a correlation value and compares the value with the first threshold value TH1 and the second threshold value TH2 (TH1> TH2) and outputs the result as two bits. Here, the first threshold value TH1 is used as reference data for detecting the first correlation value 8111 of FIG. 8, and the second threshold value TH2 is used as reference data for detecting the second correlation value 812 of FIG. 8. do.

FIG. 13A illustrates a structure of a frame sync validator according to an exemplary embodiment of the present invention, in which a frame sync validator 1023 receives two sync words from a sync word extractor 1019 and a sync word generator 1023 of the receiver. Multiply by a large number of bits and accumulate the values in one frame to obtain a correlation value between two sync words. The determiner in the frame synchronizer verifier 1025 determines whether the frame is synchronized or a specific offset from the correlation value and outputs the result. The determiner 1315 may include a plurality of multiple threshold devices as shown in FIG. 13B. In this case, the determiner 1315 determines whether the correlation value is greater than the first threshold value TH1 (if synchronous) or the correlation value is not greater than the first threshold value TH1 and not smaller than the second threshold value TH2 (synchronization). Is false and the slot offset is not a multiple of five, or the correlation value is less than the second threshold TH2 (if the synchronization is incorrect and the slot offset is a multiple of five).

Referring to FIG. 13A, the frame sync verifier 1025 receives a sync word output from the sync word extractor 1019 and its own sync word generator 1023, and generates a signal for verifying frame sync. The multiplier 1311 receives the two sync words as described above and multiplies each bit by bit. The adder accumulator 1313 accumulates the multiplication value generated by the multiplier 1311 in one frame unit and calculates a correlation value between the two sync words. The determiner 1315 determines whether or not a frame is synchronized from the correlation value of the two sync words output from the accumulator adder 1513. FIG. 13B illustrates an example of the determiner 1315 and compares a predetermined threshold value and an output of the adder accumulator 1513 with specific threshold values TH1 and TH2 to determine whether to synchronize frames.

Referring to FIG. 13B, the first threshold value TH1 is set to a value smaller than the first correlation value 811 and larger than the third correlation value 813. The second threshold value TH2 is set to a value smaller than the third correlation value 813 and larger than the second correlation value 812. The first comparator 1351 compares the correlation value output from the cumulative adder 1313 with the first threshold value TH1, and determines that the first correlation value 811 is detected when the output of the cumulative adder 1313 is greater than the first threshold value TH1. A true signal is generated, and a false signal is generated when it is smaller than the first threshold value TH1. In addition, the second comparator 1353 compares the correlation value output from the cumulative adder 1313 and the second threshold value TH2, and detects the second correlation value 812 when the cumulative adder 1313 output is smaller than the second threshold value TH2. A true signal is generated by the determination, and a false signal is generated when it is larger than the second threshold value TH2. A parallel to serial converter (P / S) 1355 inputs the outputs of the first and second comparators 1351 and 1353 and outputs the outputs of the comparators 1351 and 1353 in two consecutive bits. In this case, the determiner 1315 determines the detection of the first correlation value 811 when the first comparator 1351 generates a true signal, and outputs a first determination signal. When the second comparator 1353 generates a true signal, the second comparator 1315 generates the true signal. The second judgment signal is output by determining that the correlation value 812 is detected. When both the first comparator 1351 and the second comparator 1353 generate a false signal, it is determined that the third correlation value is detected and outputs the third decision signal.

Accordingly, the determiner 1315 generates a determination signal indicating that the frame synchronization is correct when the correlation value output from the accumulator adder 1313 is greater than the first threshold value TH1 and the second threshold value TH2. And a value not greater than the first threshold value TH1 and not smaller than the second threshold value TH2 generates a determination signal indicating that frame synchronization is not correct and that the slot offset is not a multiple of five, and the value is smaller than the second threshold value TH2. In this case, a determination signal is generated indicating that the frame synchronization is incorrect and the slot offset is a multiple of five.

The output of the frame synchronization verifier 1025 which generates the above determination signal is transmitted to the synchronization unit 1013 to control an operation of obtaining frame synchronization.

The synchronization acquisition method as described above may be terminated after performing one synchronization verification process at the time of synchronization acquisition as shown in FIG. 14, and may be repeatedly performed at a predetermined cycle.

14 is a flowchart illustrating a synchronization verification and synchronization recovery process according to the present invention. In a first process, a receiver acquires synchronization using a synchronization device from a received signal. In the second process, the receiver calculates a correlation value between a sync word obtained from a received signal and a sync word generated by itself. In the third process, the receiver compares the correlation value with the first threshold value TH1. If the correlation value is greater than the first threshold value TH1, the receiver determines that synchronization is correct and demodulates and decodes the frame. However, if the correlation value is not greater than the first threshold value TH1, the receiver compares the correlation value with the first threshold value TH2 (TH2 <TH1) in the fourth process. If the correlation value is smaller than the second threshold value TH2, the receiver performs shift by 5 slots for its frame synchronization in the sixth process and then returns to the second process of frame verification. If the correlation value is not smaller than the second threshold value TH2, the receiver returns to the second process after performing a shift by one slot for frame synchronization in the seventh process. Here, the shift of the frame synchronization of the receiver itself may be performed by changing the sync word state information output to the sync word generator 1023 according to the control signal received from the frame sync verifier 1025. The sync word state information is information indicating a position on a sequence of sync words to be output at a specific time, that is, a sync word state. For example, the sync word state information includes information on at which offset position the self sync word used for sync verification should be located.

Referring to the synchronization verification process operated in the same order as in FIG. 14 using the synchronization word according to an embodiment of the present invention, if synchronization is obtained in step 1411, the frame obtained by calculating a correlation value of the synchronization word in step 1413 Verify your motivation. In this case, when the correlation value is greater than the first threshold value TH1 in step 1415, the first correlation value 811 is detected (that is, frame synchronization is performed). In step 1417, the receiving device demodulates and decodes the received frame data. Do this.

However, if the correlation value is smaller than the first threshold value in step 1415, it is checked whether the correlation value is smaller than the second threshold value TH2 in step 1419. In this case, when the correlation value is not smaller than the second threshold value TH2, the third correlation value 813 is obtained. In this case, the slot offset is not a multiple of five. In this case, in step 1423, the frame synchronization verifyer 1025 transfers the third determination signal to the synchronization unit 1013, thereby shifting the receiver frame synchronization by one slot. In step 1413, the frame verification operation is performed again. In addition, when the correlation value is smaller than the second threshold value TH2 in step 1419, the second correlation value is 812. In this case, the slot offset becomes the fifth or tenth slot in the interval of one frame. In this case, in step 1421, the frame synchronization verifier 1025 transfers the second determination signal to the synchronization unit 1013, which causes the synchronization unit 1013 to move the receiver frame synchronization by 5 slots. Subsequently, the frame verification operation is performed again in steps 1413 and 1413.

Therefore, in the embodiment of the present invention, it is understood that the synchronization word having the correlation characteristics as shown in FIG. 8 is used, and the receiving apparatus is configured as shown in FIG.

Accordingly, in the first process of FIG. 14, the receiver of FIG. 10 obtains synchronization through the synchronizer 1013 from the received signal. It is assumed that the synchronizer 1013 acquires PN chip synchronization and slot synchronization to perform basic despreading. In addition, if the synchronization is successfully acquired, the frame synchronization is matched.

In the second process, the receiver as shown in FIG. 10 calculates a correlation value between a sync word obtained from a received signal and a sync word generated by itself using a frame synchronizer 1025 (composed of a correlator including a multiplier and a summer).

In a third process, the receiver compares the correlation value with the first threshold value TH1 using the first comparator of the determinator in the frame synchronization verifier 1025. In this case, when the frame synchronization is correct, it corresponds to the offset 0 of FIG. 8, and thus, the first correlation value 811 having the highest correlation value is shown. If the correlation value is larger than the first threshold value TH1, the decision of the frame synchronization verifier 1025 of the receiver determines that the synchronization is correct, and sends a synchronization confirmation signal (first determination signal) to the synchronization unit 1013. Accordingly, the receiver demodulates and decodes the frame in the fifth process. That is, information is obtained from another data output of FIG. If the correlation value is not greater than the first threshold value TH1, the receiver proceeds to the fourth process.

In the fourth process, the receiver compares the correlation value with the second threshold TH2 (TH2 <TH1) using the second comparator of the determinator in the frame synchronizer 1025. When frame synchronization is shifted by 5 or 10 slots, this corresponds to the case of offset 5 or 10 in FIG. 7, and thus the correlation value represents the minimum point (second correlation value 812). If the correlation value is smaller than the second threshold value TH2, the decision device of the receiver frame synchronization verification device determines that the frame synchronization is shifted by 5 or 10 slots, and sends the first synchronization correction signal (second decision signal) to the synchronization device. Therefore, in the sixth process, the receiver performs a shift of 5 slots in its frame synchronization through the synchronization device, and then returns to the second process to start the frame synchronization verification process again. If the correlation value is not less than the second threshold value T2, in the decision apparatus of the receiver frame synchronization verifying apparatus, if the correlation value is not the highest or minimum point in FIG. 7 (third correlation value 813), that is, the offset is 0, 5, or 10. If it is not a multiple of 5, it sends a second synchronization correction signal (third decision signal) to the synchronization device, and accordingly, in the seventh process, the receiver moves 1 slot (Shift) to its frame synchronization through the synchronization device. ), Go back to the second step and start the frame sync verification process again.

In the correlation characteristic of FIG. 7, two minimum points appear at offsets 5 and 10. In addition, the minimum point positions may be different, but a synchronization word having a similar correlation characteristic may be formed. In this case, the synchronization may be applied by applying the concept of the present invention. Verification and motivation recovery processes can be performed.

The sync word generated by the above method has the characteristics as shown in FIG. 8 according to the characteristics of the sequence. If the frame synchronization is correct, that is, the offset is a multiple of zero or 15, the autocorrelation value of the sync word is 15N. If the slot offset is not a multiple of five, the autocorrelation value of the sync word is zero when the frame sync is incorrect. If the frame offset is incorrect and the slot offset is a multiple of 5, the autocorrelation value of the sync word becomes a specific negative value (-P). Therefore, by using the sync word generated by the above method, it is possible to verify the frame synchronization with high reliability. Also, if the motivation is not correct, the motivation can be effectively restored. For example, if the correlation value is larger than the first threshold, the frame synchronization is determined to be correct, and the frame is demodulated and decoded. If the correlation value is smaller than the second threshold value (second threshold value <first threshold value), the slot offset is determined to be a multiple of five, and the synchronization is checked again at the position shifted by five slots. If the correlation value is between the first and second thresholds, check synchronization again at the position shifted by one slot. If you repeat this process, assuming that the decision is accurate, you can synchronize with up to seven synchronization checks.

Claims (53)

delete delete delete delete delete delete delete delete delete delete delete In a sync word generator of a code division multiple access communication system in which one frame consists of slots of 2 ^P -1 (P is a positive integer), A clock generator for generating a clock of the slot period rate; At least two sequences having a chip size of 2 ^K −1 (K is a positive integer), wherein the sequences generate a first correlation with the maximum point when the chip start points coincide, and at two specific chip offsets Generating second correlation values having a minimum point, the sequence generators having a third correlation value at an intermediate position at the remaining chip offsets, And a selector for selecting corresponding chips of the sequences selected at corresponding slot positions of the frame and outputting the selected chips as a sync word. 13. The sync word generator of claim 12, wherein the one frame consists of 15 slots and the chip size of the sequences is 15. 15. The apparatus of claim 13, wherein the specific chip offset position is a fifth and tenth chip position of every frame. delete delete delete delete A channel transmitting apparatus of a code division multiple access communication system in which one frame consists of 15 slots, Having at least two sequences of length 15, said sequences generating a first correlation value with a maximum point when the starting points match, a second correlation value with a minimum point at two specific offsets, and remaining A sync word generator for generating a sync word having a third correlation value of an intermediate position at offsets; A first selector for selecting the synchronization bits and pilot bits not used for the synchronization word and inserting the synchronization bits into a predetermined position of a pilot section in the slot; And a second selector for generating channel data to be transmitted by selecting data different from the pilot bits output from the first selector. delete delete delete delete delete delete delete delete delete delete delete In the asynchronous code division multiple access communication system, each frame of a series of frames is divided into a plurality of given slots, each slot includes a plurality of sync symbols, and a sync word of the frame consists of sync symbols of the respective slots. In the apparatus for generating the frame sync word, The start of each received frame has a first correlation when the reference frame is synchronized with two received frames, and each of at least two slot splitting points divided at predetermined intervals of a given plurality of slots of each reference frame. Sequence generators for generating sequences of at least two sync symbols each having a second correlation value different from the first correlation value each time a slot is located; And a selector for multiplexing respective sync symbols generated from said sequence generators and having each slot of said slots has said multiplexed sync symbols corresponding thereto. 32. The apparatus of claim 31, wherein the frame divided into the plurality of slots comprises fifteen slots, and the two slot splitting points are fifth and tenth slots. 33. The method of claim 32, wherein when the starting slots of the respective reception frames are located at each of the slot division points other than a multiple of five, the first and second correlation values between the first correlation value and the second correlation value. A synchronization word generator in an asynchronous code division multiple access communication system having three correlation values. 34. The method of claim 33, wherein the frame sync word has first and second sync symbols for each slot, and the first and second sequence generators for generating the first and second sync symbols, respectively, are shown in Table 4 below. And a synchronization word generator of an asynchronous code division multiple access communication system for generating one of each of the first sequence S1 and the second sequence S2. 34. The apparatus of claim 33, wherein the frame sync word has first and second sync symbols for each slot, and the first and second sequence generators for generating the first and second sync symbols, respectively, are shown in Table 5 below. And a synchronization word generator of an asynchronous code division multiple access communication system for generating one of each of the first sequence S1 and the second sequence S2. 36. The apparatus of claim 34 or 35, wherein the channel using the frame sync word is a downlink DPCH channel. 34. The apparatus of claim 33, wherein the frame sync word has first to fourth sync symbols in each slot and generates a first sequence generator and third and fourth sync symbols to generate the first and second sync symbols. 2. A synchronization word generator of an asynchronous code division multiple access communication system, wherein the second sequence generators respectively generate two sequences among the first sequence S1 and the second sequence S2 as shown in Table 6 below. 34. The apparatus of claim 33, wherein the frame sync word has first and fourth sync symbols for each slot and generates a first sequence generator and third and fourth sync symbols to generate the first and second sync symbols. 2. A sync word generator of an asynchronous code division multiple access communication system, wherein the second sequence generators respectively generate two sequences among the first sequence S1 and the second sequence S2, as shown in Table 7 below. 34. The method of claim 33, wherein the frame sync word has first and fourth sync symbols for each slot, and sequence generators for generating the first to second sync symbols, respectively, are shown in Table 1 below. S1-synchronization word generator of an asynchronous code division multiple access communication system for generating one each of the fourth sequence S4. 40. The apparatus of any one of claims 37 to 39, wherein the channel using the frame sync word is an uplink DPCCH channel. 40. The apparatus according to any one of claims 37 to 39, wherein the channel using the frame synchronization word is a downlink DPCH channel. 40. The apparatus of any one of claims 37 to 39, wherein the channel using the frame sync word is a downlink PCCHPCH channel. 40. The apparatus of any one of claims 37 to 39, wherein the channel using the frame sync word is an SCCPCH channel of the downlink. 34. The apparatus of claim 33, wherein the frame sync word has first to eighth sync symbols in each slot, and generates a first sequence generator and fifth to eighth sync symbols to generate the first to fourth sync symbols. 2. A synchronization word generator of an asynchronous code division multiple access communication system, wherein the second sequence generators respectively generate four sequences among the first sequence S1 and the second sequence S2 as shown in Table 9 below. 34. The apparatus of claim 33, wherein the frame sync word has first and eight sync symbols for each slot and generates a first sequence generator and a fifth to eight sync symbols to generate the first to fourth sync symbols. 2. A synchronization word generator of an asynchronous code division multiple access communication system, wherein the second sequence generators generate four sequences of the first sequence S1 and the second sequence S2, respectively, as shown in Table 10 below. 34. The apparatus of claim 33, wherein the frame sync word has first and eight sync symbols for each slot, and generates first sequence generator, third and fourth sync symbols to generate the first and second sync symbols, respectively. A second sequence generator, a third sequence generator for generating fifth and sixth synchronous symbols, and a fourth sequence generator for generating seventh and eighth synchronous symbols, respectively, are shown in Table 1 below. An apparatus for synchronizing words in an asynchronous code division multiple access communication system for generating two sequences each of four sequences S4. 47. The apparatus according to any one of claims 44 to 46, wherein the channel using the frame synchronization word is a DPCH channel of the downlink. 47. The apparatus of any one of claims 44 to 46, wherein the channel using the frame synchronization word is an SCCPCH channel of the downlink. Each frame of a series of frames is divided into a plurality of given slots, each slot having a plurality of sync bits, and a sync word of the frame consists of sync bits of the respective slots. In the channel transmitter, The start of each received frame has a first correlation when the reference frame is synchronized with two received frames, and each of at least two slot splitting points divided at predetermined intervals of a given plurality of slots of each reference frame. Multiplexing sequence generators for generating sequences of at least two sync bits each having a second correlation value different from the first correlation value each time a slot is located; A sync word generator comprising a selector for each slot of slots having the multiplexed sync bits corresponding thereto; A first selector for multiplexing the synchronization bits output from the synchronization word generator and the pilot bits not used in the frame synchronization word and inserting them in a set bit position of a pilot period in each slot; And a second selector for generating channel data to be transmitted by selecting data different from the pilot bits output from the first selector. Each frame of the series of reference sync frames and the receive sync frames is divided into a plurality of given slots, each slot is divided into a plurality of bits, each frame has a sync word and the series of reference sync frames A method for synchronizing the series of receive synchronization frames at Each received at each of at least two slot splitting points having a first correlation when the reference synchronization frames are synchronized with the reception synchronization frames, and divided at regular intervals of a given plurality of slots of each reference synchronization frame. Method of generating a frame synchronization word in a code division multiple access communication system for providing the frame synchronization word so as to have second correlation values different from the first correlation value whenever the start frame of the synchronization frame is located. Each frame of the series of reference sync frames and the receive sync frames is divided into a plurality of given slots, each slot is divided into a plurality of bits, each frame has a sync word and the series of reference sync frames An apparatus for synchronizing the series of receive synchronization frames at Each received at each of at least two slot splitting points having a first correlation value when the reference synchronization frames are synchronized with the reception synchronization frames, and divided at predetermined intervals of a given plurality of slots of each reference synchronization frame. A sync word generator for providing the frame sync word so as to have second correlation values different from the first correlation value whenever the start frame of the synchronization frame is located; A sync word extractor for extracting a frame sync word from received frame information; And a frame synchronization verifier configured to verify frame synchronization by calculating a correlation value between the extracted frame synchronization word and the provided synchronization word. Each frame of a series of reference sync frames and receive sync frames is divided into a plurality of given slots, each slot is divided into a plurality of bits, each frame has a sync word, and the frame sync word is a reference. When each synchronization frame is synchronized with the reception synchronization frames, the first synchronization value has a first correlation value, and each of the reception synchronization frames is divided into at least two slot division points divided at predetermined intervals of a given plurality of slots of the respective reference synchronization frames. A frame synchronization method of an asynchronous code division multiple access communication system having a sync word generator for providing a sync word having a second correlation value different from the first correlation value whenever a start frame of the position is located, Extracting a frame sync word from the received frame information; Calculating a correlation value between the extracted frame sync word and the generated sync word; Processing the frame synchronization state when the calculated correlation value has a first correlation value; When the calculated correlation value has a second correlation value, moving the frame synchronization word generated by the synchronization word generator by a set slot period, and returning to the correlation value calculation process; When the calculated correlation value has a value other than the first and second correlation values, shifting the frame synchronization word by one slot interval and returning to the correlation value calculation process. A method for determining synchronization of a received frame by calculating a correlation value between a reference sync word and a sync word in a received frame, Determining that the correlation value is synchronized when the reference synchronization word exceeds a first preset reference value indicating that the received synchronization word is synchronized; And determining a shift step of the received sync word when the correlation value exceeds a second set reference value.