KR100394876B1 - method of fabricating ultrasonic wave probe - Google Patents

Abstract

The ultrasonic probe includes a substrate having a CMOS, an insulating layer formed on the substrate, a membrane layer formed on the insulating layer, a lower electrode formed on the membrane layer, a piezoelectric layer formed on the lower electrode, and formed on the piezoelectric layer. Comprising an upper electrode and a bonding layer formed on the upper electrode, it is possible to implement a two-dimensional array (N x M) ultrasonic transducers applied to high-quality three-dimensional ultrasound diagnostics.

Description

Method of fabricating ultrasonic wave probe

The present invention relates to an ultrasonic transducer using an ultrasonic vibrator, and more particularly, to a manufacturing method of a two-dimensional array (N x M) ultrasonic transducers applied to a real-time, high-quality three-dimensional ultrasonic diagnostic apparatus.

The ultrasonic transducer converts electrical energy into sound waves and receives reflected sound, and then converts the electrical energy back into electrical energy. The transducer is an ultrasonic diagnostic device (medical frequency band: 1 to 10 MHz), an ultrasonic therapy device (frequency band: 1 MHz, 6). ~ 7cm subcutaneous), ultrasonic flaw detection (a type of non-destructive test for detecting discontinuities on the surface or inside, thickness measurement available. 500kHz to 25MHz), ultrasonic welder (using ultrasonic vibration energy to provide instantaneous frictional heat at the joint surface of the deposit) Dissolves and bonds plastics for strong molecular bonds, 15k to 28 kHz), ultrasonic cleaners (using sound pressure and cavitation effects, 28 k to 40 kHz), ultrasonic flowmeters and sensing sensors.

According to the configuration of the ultrasonic probe used in the three-dimensional ultrasonic diagnostics that are currently commercially available, the linear piezoelectric element array can be moved repeatedly in a certain range in the lateral direction to enable two-dimensional ultrasonic scanning. The dimension is implemented.

However, this does not realize true real-time three-dimensional ultrasound, and this technique, which uses bulk piezoelectric materials, uses mechanical methods of separation for the construction of elements. As the number of devices forming ultrasonic waves per unit area is low, the degree of integration is low and many limitations are revealed to increase the resolution.

In other words, when the number of devices is increased to increase the resolution, the size of the ultrasonic transducer becomes very large, and thus it is difficult to operate it. Also, since the driving of the system is managed externally, the connection between the ultrasonic scanner and the transducer is performed. Problems such as oversizing of cables occur.

On the other hand, there are limitations in manufacturing and designing a two-dimensional array using a bulk piezoelectric material that has been proposed to overcome the problems of the linear array.

For example, when two-dimensional ultrasonic waves are implemented by laminating piezoelectric materials polished to a fine thickness using an adhesive, the adhesiveness of the adhesive used as a structural stabilizer is deteriorated, and the degree of integration resulting from mechanical processing is reduced, and The circuit connection for independent oscillation and detection of each device is limited in increasing the number of devices.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to use a technique for depositing a thin film or a thick film of a piezoelectric material in bulk form, and using the ultrasonic wave on a substrate. The present invention provides a method for manufacturing a two-dimensional array (N x M) ultrasonic probes applied to a high-quality three-dimensional ultrasound diagnostic apparatus by forming a piezoelectric member.

In order to achieve the above object of the present invention, the ultrasonic probe according to the present invention is a substrate having a CMOS, an insulating layer formed on the substrate, a membrane layer formed on the insulating layer, a lower electrode formed on the membrane layer and And a piezoelectric layer formed on the lower electrode, an upper electrode formed on the piezoelectric layer, and a bonding layer formed on the upper electrode.

1 (a) is a partial plan view of an ultrasonic probe according to a first embodiment of the present invention, and FIG. 1 (b) is a sectional view taken along the line A-A of FIG. 1 (a).

2 is a flowchart illustrating a method of manufacturing an ultrasonic probe according to a first embodiment of the present invention.

3 (a) is a partial plan view of the ultrasonic transducer according to the second embodiment of the present invention, and FIG. 3 (b) is a sectional view taken along the line B-B of FIG. 3 (a).

4 is a flowchart illustrating a method of manufacturing an ultrasonic probe according to a second embodiment of the present invention.

FIG. 5 (a) is a partial plan view of the ultrasonic transducer according to the third embodiment of the present invention, and FIG. 5 (b) is a sectional view taken along the line C-C of FIG. 5 (a).

6 is a flowchart illustrating a method of manufacturing an ultrasonic probe according to a third embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10 ----- substrate 13 ----- common electrode pad

15 ----- Transistor Pad 16 ----- Air Layer

17, 18 ----- Insulation layer 19 ----- Membrane layer

21 ----- lower electrode 23 ----- piezoelectric layer

25 ----- Upper electrode 27 ----- Metal

C1 ~ C8 ----- Contact Hole

The ultrasonic probe according to the present invention omits the configuration of the ultrasonic insulator, the damping layer, and the like, and only discusses the configuration formed between the piezoelectric materials.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

1 (a) is a partial plan view of an ultrasonic probe according to a first embodiment of the present invention, and FIG. 1 (b) is a sectional view taken along the line A-A of FIG. 1 (a).

As shown, the ultrasonic probe according to the present invention includes a substrate 10 having a complementary metal oxide semiconductor (CMOS), an insulating layer 17 formed on the substrate 10 for interlayer insulation, and the insulating layer. A membrane layer 19 formed on the layer 17 to control interlayer stress, a lower electrode 21 formed on the membrane layer 19, a piezoelectric layer 23 formed on the lower electrode 21, and the piezoelectric element. And an upper electrode 25 formed on the layer 23 and a bonding layer (not shown) formed on the upper electrode 25.

FIG. 2 is a flowchart illustrating a method of manufacturing an ultrasonic probe according to a first embodiment of the present invention. As shown in the drawing, a method of manufacturing an ultrasonic probe according to the present invention is, first, an independent piezoelectric body consisting of (N × M) pieces. LPCVD, APCVD, or PECVD method of SiOx or SiNx for electrical insulation on a CMOS-embedded substrate (10) consisting of (N x M) transistors (not shown) to enable electrical regulation and sensing of materials. By depositing to form an insulating layer 17 (S101). At this time, the thickness of the insulating layer 17 is preferably 8,000 to 10,000 kPa.

In the drawing, reference numeral 13 denotes a common electrode pad, and 15 denotes a transistor pad.

In the case of CMOS using general semiconductor technology, it is impossible to use it because it shows the deterioration of characteristics in the subsequent process of 300 to 400 ° C. or higher. It is used to secure the margin of design and the depth of diffusion. That is, in the general semiconductor, the metal material uses aluminum, aluminum alloy or copper, but the present invention enables the characteristics of the MOS at high temperature by using a film laminated in the order of TiN-Ti-TiON-W as a metal layer.

Subsequently, silicon nitride or silicon oxide is deposited on the insulating layer 17 by LPCVD, APCVD, or PECVD to form a membrane layer 19 (S103). At this time, the thickness of the membrane layer 19 is preferably 2,000 to 4,000 Pa.

Thereafter, a metal is stacked on the membrane layer 19 to form a lower electrode 21 (S105). Platinum, aluminum, or RuO is used as the lower electrode 21, and a multilayer is formed using titanium, tantalum, or the like as a buffer layer to improve adhesion and properties of the film. do. At this time, the lower electrode 21 is deposited by a sputtering method or a metal CVD method, and the thickness thereof is preferably 1,000 to 2,000 mW.

Subsequently, a piezoelectric material is stacked on the lower electrode 21 to form a piezoelectric layer 23 (S107). Bulk piezoelectric materials currently used include ZnO, AlN, PZT (PbZrTiO3), PLZT (PbLaZrTiO3), BT (BaTiO3), and the like. This material is formed using a deposition method to form a thin film (thickness: 0.1um to 1um) or a thick film (thickness: 2 to several hundredum), and the deposition of the piezoelectric layer 23 is performed by sputtering, reactive sputtering, sol- The deposition is carried out by a sol-gel process or MOCVD.

Next, a metal is stacked on the piezoelectric layer 23 to form an upper electrode 25 (S109). Platinum, aluminum, or RuO is used as the upper electrode 21, and a multilayer is formed using titanium, tantalum, or the like as a buffer layer to improve adhesion and properties of the film. At this time, the upper electrode 25 is deposited by a sputtering method or a metal CVD method, and the thickness thereof is preferably 1,000 to 1500 mW.

Subsequently, the upper electrode 25 or the lower electrode 21 is continuously patterned by photolithography and etching (S111), and the membrane layer 19 and the insulating layer 17 are simultaneously patterned to form a contact hole. C1 and C2 are formed (S113).

Next, the metal 27 is stacked and patterned such that the common electrode pad 13 is electrically connected to the upper electrode 25, and the transistor pad 15 is electrically connected to the lower electrode 21 (S115). .

Although not shown in the drawings, a matching layer is formed on the metal 27 and the upper electrode 25 to reduce a difference in acoustic impedance with a subject such as skin.

3 (a) is a partial plan view of the ultrasonic transducer according to the second embodiment of the present invention, and FIG. 3 (b) is a sectional view taken along the line B-B of FIG. 3 (a).

As shown, in the configuration of the second embodiment of the present invention, an additional insulating layer 20 is formed between the insulating layer 17 and the membrane layer 19 as compared with the configuration of the first embodiment described above, and the insulating film ( It is possible to improve the degree of integration of the device per unit area by forming the double contact holes C3 to C6 through the layers 17 and 20 and the membrane layer 19.

4 is a flowchart illustrating a method of manufacturing an ultrasonic probe according to a second embodiment of the present invention. In the manufacture of the ultrasonic probe according to the present invention, first, an independent piezoelectric material consisting of (N × M) pieces is electrically adjusted and Insulating layer by depositing SiOx or SiNx by LPCVD, APCVD, or PECVD method for electrical insulation on a substrate (10) containing CMOS composed of (N x M) transistors (not shown) for sensing (17) is formed (S201).

In the drawing, reference numeral 13 denotes a common electrode pad, and 15 denotes a transistor pad.

Subsequently, the insulating layer 17 is patterned by a photo process and an etching process to form contact holes C3 and C4 (S203), and then the metal 18 is laminated and patterned (S205).

Next, SiOx or SiNx is deposited on the insulating layer 17 and the metal 18 by LPCVD, APCVD, or PECVD to laminate the insulating layer 20 (S207), and silicon nitride or silicon oxide is deposited thereon. The membrane layer 19 is formed by deposition by LPCVD, APCVD, or PECVD (S209).

Subsequently, the insulating layer 20 and the membrane layer 19 are patterned by a photo process and an etching process to form a contact hole C5 (S211), and then a metal is laminated on the membrane layer 19 to form a lower electrode 21. ) Is formed (S213).

Subsequently, the piezoelectric material is laminated on the lower electrode 21 to form the piezoelectric layer 23 (S215), and then the upper electrode 25 is formed by laminating the metal on the lower electrode 21 by sputtering or metal CVD. S217).

Subsequently, the upper electrode 25 or the lower electrode 21 is successively patterned by a photo process and an etching process (S219), and the membrane layer 19 and the insulating layer 20 are simultaneously patterned to form a contact hole C6. It is formed (S221).

Next, the metal 27 is stacked and patterned such that the common electrode pad 13 is electrically connected to the upper electrode 25, and the transistor pad 15 is electrically connected to the lower electrode 21 (S223). .

Although not shown in the drawings, this embodiment also serves to reduce the difference in acoustic impedance with a subject such as skin by forming a bonding layer on the metal 27 and the upper electrode 25 as in the first embodiment. do.

FIG. 5 (a) is a partial plan view of the ultrasonic transducer according to the third embodiment of the present invention, and FIG. 5 (b) is a sectional view taken along the line C-C of FIG. 5 (a).

As shown, the configuration according to the third embodiment of the present invention is a sacrificial layer 16 for forming an air gap between the insulating layer 17 and the membrane layer 19 as compared with the configuration of the first embodiment. ) And an additional insulating layer 18 for structurally supporting the same, to more effectively improve the ultrasonic resonance of the piezoelectric element.

FIG. 6 is a flowchart illustrating a method of manufacturing an ultrasonic probe according to a third embodiment of the present invention. In the manufacture of the ultrasonic probe according to the present invention, first, an independent piezoelectric material consisting of (N × M) pieces is electrically adjusted and SiOx or SiNx was deposited by LPCVD, APCVD, or PECVD method for electrical insulation on a substrate (10) having a CMOS including (N x M) transistors (not shown) which can be sensed, and then an insulating layer ( 17) is formed (S301).

In the drawing, reference numeral 13 denotes a common electrode pad, and 15 denotes a transistor pad.

Subsequently, poly-silicon is deposited on the insulating layer 17 by LPCVD, APCVD, or PECVD to form a sacrificial layer 16 for forming an air layer (S303).

Next, the sacrificial layer 16 is patterned by a photo process and an etching process to form the support part 31 for connecting and fixing the insulating layer 17 and the membrane layer 19 (S305).

Subsequently, after the insulating layer 18 is laminated and chemical mechanical polishing (CMP) for planarization of the surface (S307), the silicon layer or silicon oxide is converted into the membrane layer 19 by LPCVD, APCVD, or PECVD. To deposit (S309).

Subsequently, after depositing a metal on the membrane layer 19 to form a lower electrode 21 (S311), a piezoelectric material is laminated on the lower electrode 21 to form a piezoelectric layer 23 (S313). The upper electrode 25 is formed by stacking metal on the sputtering method or the metal CVD method (S315).

Next, the upper electrode 25, the piezoelectric layer 23, the lower electrode 21, and the membrane layer 19 are successively patterned by the photo process and the etching process (S317), the membrane layer 19 and the insulation The layer 18 and the insulating layer 17 are simultaneously patterned to form contact holes C7 and C8 (S319).

Subsequently, after the metal 27 is stacked and patterned, the common electrode pad 13 is electrically connected to the upper electrode 25, and the transistor pad 15 is electrically connected to the lower electrode 21 (S321). ), An etching process for removing the sacrificial layer is performed. The etching process uses an XeF2 etch to vaporize the solid XeF2 at low pressure at room temperature and to remove polysilicon formed as a sacrificial layer (S323).

Although not shown in the drawings, a bonding layer is formed on the metal 27 and the upper electrode 23 to reduce a difference in acoustic impedance with a subject such as skin.

According to the present invention, by using a technique for depositing a thin film or a thick film of the piezoelectric material in bulk form and forming a piezoelectric material used for ultrasound on a substrate to enable a two-dimensional array, two-dimensional applied to high-quality three-dimensional ultrasound diagnostics It becomes possible to manufacture an array (N x M) ultrasonic transducers.

Claims (4)

Forming an insulating layer 17 on a substrate 10 having a CMOS embedded therein and having a common electrode pad 13 and a transistor pad 15 formed thereon; Forming a membrane layer 19 on the insulating layer 17; Stacking a metal on the membrane layer 19 to form a lower electrode 21; Stacking a piezoelectric material on the lower electrode 21 to form a piezoelectric layer 23; Stacking a metal on the piezoelectric layer 23 to form an upper electrode 25; Continuously patterning the upper electrode 25, the piezoelectric layer 23, and the lower electrode 21 by photo process and etching; Simultaneously patterning the membrane layer 19 and the insulating layer 17 to form a contact hole; Stacking and patterning a metal 27 to electrically connect the common electrode pad 13 to the upper electrode 25, and electrically connect the transistor pad 15 to the lower electrode 21; Ultrasonic probe manufacturing method comprising the step of forming a bonding layer on the metal (27) and the upper electrode (25). Forming an insulating layer 17 on a substrate 10 having a CMOS embedded therein and having a common electrode pad 13 and a transistor pad 15 formed thereon; Patterning the insulating layer 17 to form contact holes C3 and C4; Stacking and patterning a metal 18 on the insulating layer 17; Stacking the insulating layer 20 on the insulating layer 17 and the metal 18; Forming a membrane layer 19 on the insulating layer 20; Patterning the insulating layer 20 and the membrane layer 19 to form a contact hole C5; Stacking a metal on the membrane layer 19 to form a lower electrode 21; Stacking a piezoelectric material on the lower electrode 21 to form a piezoelectric layer 23; Stacking a metal on the piezoelectric layer 23 to form an upper electrode 25; Continuously patterning the upper electrode 25, the piezoelectric layer 23, and the lower electrode 21; Simultaneously patterning the membrane layer 19 and the insulating layer 20 to form a contact hole C6; Stacking and patterning a metal 27 to electrically connect the common electrode pad 13 to the upper electrode 25, and electrically connect the transistor pad 15 to the lower electrode 21; Ultrasonic probe manufacturing method comprising the step of forming a bonding layer on the metal (27) and the upper electrode (25). Forming an insulating layer 17 on a substrate 10 having a CMOS embedded therein and having a common electrode pad 13 and a transistor pad 15 formed thereon; Forming a sacrificial layer 16 on the insulating layer 17; Patterning the sacrificial layer (16), Stacking and planarizing the insulating layer 18 on the sacrificial layer 16; Forming a membrane layer 19 on the insulating layer 18; Stacking a metal on the membrane layer 19 to form a lower electrode 21; Stacking a piezoelectric material on the lower electrode 21 to form a piezoelectric layer 23; Stacking a metal on the piezoelectric layer 23 to form an upper electrode 25; Continuously patterning the upper electrode 25, the piezoelectric layer 23, the lower electrode 21, and the membrane layer 19; Simultaneously patterning the membrane layer 19, the insulating layer 18, and the insulating layer 17 to form contact holes C7 and C8; Stacking and patterning a metal 27 to electrically connect the common electrode pad 13 to the upper electrode 25, and electrically connect the transistor pad 15 to the lower electrode 21; Removing the sacrificial layer 16; Ultrasonic probe manufacturing method comprising the step of forming a bonding layer on the metal (27) and the upper electrode (25). The ultrasonic probe manufacturing method according to any one of claims 1 to 3, wherein the metal layer of the CMOS is a metal layer laminated in the order of TiN-Ti-TiON-W.