KR100384699B1 - IP Frame Switching Device and Method - Google Patents

Abstract

The present invention relates to IPC frame switching in an IPC system (Interprocess Communication System), and in particular, to configure the IPC system via the D-bus only when necessary when switching between the IPC frame in the IPC system high-speed IPC frame An IPC frame switching apparatus and method for providing switching are provided.

In the conventional IPC system, since all processors are connected to the D-bus through respective U-links and nodes, bottlenecks frequently occur when IPC frames are transmitted from the corresponding D-bus through each node and U-link. In addition, there is a problem that the node of each processor cannot switch the IPC frame without passing through the D-bus.

The present invention configures the IPC system via the D-bus only when necessary to switch between the processors in the IPC system, so that IPC frame switching between the processors is possible without passing through the D-bus. IPC frame switching speed and switching efficiency can be improved.

Description

IP Frame Switching Device and Method

The present invention relates to IPC frame switching in an IPC system (Interprocess Communication System), and in particular, to configure the IPC system via the D-bus only when necessary when switching between the IPC frame in the IPC system high-speed IPC frame An IPC frame switching apparatus and method for providing switching are provided.

The configuration of the IPC system in the conventional switching system is a D-bus 10 implemented on the backplane (Plane) of the corresponding switching system, as shown in Figure 1 attached to the IPC frame through the U-link It includes a processor unit 30 for transmitting and receiving, and a node unit 20 for connecting the D-bus 10 and the processor unit 30 by providing a U-link matching function and a D-bus matching function.

Each node 20-1 to 20-n of the node unit 20 will be described in more detail with reference to the first node 20-1, for example, as shown in FIG. 2. 21, a reception buffer section 22, a parallel / serial converter 23, a serial / parallel converter 24 and a transmission buffer section 25, the comparator 21 having a D-bus. (10), the destination address information included in the header of the IPC frame on the corresponding D-bus 10 is checked, and the IPC frame matching the address information stored therein is selected to the reception buffer unit 22. The reception buffer unit 22 stores the IPC frame recorded by the comparator 21. The parallel / serial converter 23 reads the parallel IPC frame stored in the reception buffer unit 22, converts the read parallel IPC frame into a serial IPC frame, and transmits the serial IPC frame to the processor unit 30. 24 converts a serial IPC frame received through the U-link from the processor unit 30 into a parallel IPC frame and records the same in the transmission buffer unit 25. The transmission buffer unit 25 stores the serial IPC frame recorded by the serial / parallel converter 24 and transmits the same to the D-bus 10.

The IPC frame switching operation in the conventional IPC system configured as described above is performed as follows.

First, when a specific processor of the processor unit 30 applies the serial IPC frame to the node unit 20 through the U-link, the node unit 20 converts the serial IPC frame into a parallel IPC frame to convert the D-bus ( 10), the serial / parallel converter 24 of the node connected to the corresponding U-link converts the serial IPC frame applied through the corresponding U-link into a parallel IPC frame and converts the converted parallel IPC frame into a transmission buffer unit ( 25). Accordingly, when the storage of the parallel IPC frame is terminated in the transmission buffer unit 25, the node reads the parallel IPC frame stored in the transmission buffer unit 25 and transmits the parallel IPC frame to the D-bus 10. All nodes connected to 10) can receive the corresponding IPC frame, wherein the matching between the D-bus 10 and each node 20-1 to 20-n is a 16-bit or 8-bit serial data bus structure. It is.

On the other hand, when the parallel IPC frame is sent to the D-bus 10, each node checks the destination address information included in the header of the parallel IPC frame to receive the corresponding IPC frame, the comparator 21 of each node is D- Only when the destination address information included in the header of the parallel IPC frame transmitted on the bus 10 is compared with the address assigned to the node itself, that is, the address information stored in itself, and the corresponding destination address information is matched. The IPC frame is recorded in the reception buffer unit 22. That is, when one node sends a parallel IPC frame to the D-bus 10, all nodes connected to the corresponding D-bus 10 check their destination address information included in the header of the corresponding parallel IPC frame to check their own addresses and addresses. If there is a match, the parallel IPC frame is received and recorded in the reception buffer unit 22. If it does not match, the parallel IPC frame is not received.

The parallel / serial converter 23 of the node receiving the parallel IPC frame reads the stored parallel IPC frame and transmits the stored parallel IPC frame to the processor when the storage of the parallel IPC frame ends in the reception buffer unit 22. The converter 23 reads the parallel IPC frame stored in the reception buffer unit 22, converts the serial IPC frame into a serial IPC frame, and transmits the converted serial IPC frame to the corresponding processor through a U-link connected to the corresponding node.

The conventional IPC system as described above is used as a communication method for exchanging information between processors in a local exchange system, wherein an IPC frame includes HDLC (High-level Data Link Control) including address information of a destination processor in a header part. Format), the IPC system performs the switching operation with this destination address. The destination address is also assigned to each of the processors 30-1 to 30-n, but is also assigned to each of the nodes 20-1 to 20-n and used for switching the IPC frame using the D-bus 10.

As described above, in the conventional IPC system, since all processors are connected to the D-bus through respective U-links and nodes, IPC frames are transmitted from the corresponding D-bus through each node and U-link. Bottlenecks frequently occur, and there is a problem that the nodes of each processor cannot switch IPC frames unless they pass through the D-bus.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to configure an IPC system to pass through a D-bus only when necessary for switching between processors in an IPC system. It is possible to switch IPC frames between processors without increasing the IPC frame switching speed and switching efficiency between the processors.

A feature of the present invention for achieving the above object is a D-bus implemented on the backplane of the exchange system; An IPC frame switching device having a plurality of processor units for transmitting and receiving an IPC frame through a U-link, comprising: a plurality of switching means for providing a D-bus matching function and a U-link matching function to connect the D-bus and a processor unit; The switching means includes a D-bus node connected to the D-bus to provide an IPC frame switching function between the switching means; A plurality of U-link nodes providing an IPC frame switching function between the processors of the processor unit connected through a U-link and at the same time providing an IPC frame switching function with the D-bus node; And a switching matrix for switching an IPC frame between the D-bus node and the U-link node or the U-link node.

According to another aspect of the present invention, in an IPC frame switching method for switching an IPC frame without passing through a D-bus between processors connected to one switching means in an IPC system, a serial IPC frame transmitted through a U-link is paralleled. Converting to an IPC frame; Checking the destination address information of the parallel IPC frame and writing an IPC frame to a buffer output to a U-link node for address information corresponding to the corresponding destination address information; And converting the parallel IPC frame recorded in the buffer into a serial IPC frame by the U-link node and transmitting the serial IPC frame to the processor through the U-link.

According to another aspect of the present invention, in an IPC frame switching method for switching an IPC frame via a D-bus between processors respectively connected to different switching means in an IPC system, a parallel IPC frame transmitted through a U-link is paralleled. Converting to an IPC frame; Checking the destination address information of the parallel IPC frame and writing an IPC frame to a buffer outputted to a D-bus node for address information corresponding to the corresponding destination address information; Reading the parallel IPC frame recorded in the buffer by the D-bus node and converting the size of the parallel IPC frame into a parallel data size used in the D-bus; Transmitting the converted parallel IPC frame to a D-bus; Converting the parallel IPC frame sent to the D-bus into the parallel data size used by the corresponding switching means; Checking the destination address information of the converted parallel IPC frame and if there is address information that matches the destination address information, recording the IPC frame in a buffer output to the U-link node for the address information; And reading the parallel IPC frame recorded in the buffer by the U-link node and transmitting the parallel IPC frame to the processor through the U-link.

1 is a block diagram of an IPC system in a conventional switching system.

FIG. 2 is a detailed block diagram of a node in FIG. 1; FIG.

3 is a block diagram of an IPC system in a switching system according to the present invention;

FIG. 4 is a detailed block diagram of the switching means in FIG. 3; FIG.

5 is a flowchart of an IPC frame switching operation in an IPC system according to the present invention;

Explanation of symbols on the main parts of the drawings

40: D-bus 50-1 to 50-n: switching means

51: D-bus node 51a: data converter

51b, 52-1b, 52-2b: comparators 51c, 52-1c, 52-2c: memory

51d, 52-1d, 52-2d: Buffer part 51e, 52-1e, 52-2e: Buffer lead part

52-1 to 52-n: U-link node 52-1a, 52-2a: serial / parallel converter

52-1f, 52-2f: Parallel to Serial Converters

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The configuration of the IPC system in the switching system according to the present invention, as shown in Figure 3 attached to the D-bus 40 implemented on the backplane of the switching system, and transmits and receives IPC frames over the U-link Provides a plurality of processor units 60-1 to 60-n, a D-bus matching function and a U-link matching function to connect the corresponding D-bus 40 and the processor units 60-1 to 60-n. It consists of a plurality of switching means (50-1 ~ 50-n).

Each of the switching means 50-1 to 50-n includes a D-bus node 51 connected to the D-bus 40, and each of the processor units 60-1 to 60-n through the U-link. And a plurality of U-link nodes 52-1 to 52-n connected to the processors 61-1 to 61-n, and a switching matrix 53 for switching IPC frames between the nodes. The D-bus node 51 is connected to the D-bus 40 to provide an IPC frame switching function between the switching means 50-1 to 50-n, and each corresponding U-link node 52-1 to 52-. n) provides an IPC frame switching function between the processors 61-1 to 61-n of the processor units 60-1 to 60-n connected through the U-link, and simultaneously with the corresponding D-bus node 51. IPC frame switching function, the corresponding switching matrix 53 is the corresponding D-bus node 51 and the U-link node (52-1 to 52-n) or the corresponding U-link node (52-1 to 52-) Switch IPC frames between n).

On the other hand, the D-bus node 51 and each of the U-link nodes 52-1 to 52-n configured in the respective switching means 50-1 to 50-n are connected to the switching means # 1 50-1. For example, with reference to the accompanying drawings, Figure 4 will be described in more detail as follows.

First, the D-bus node 51 includes a data converter 51a, a comparator 51b, a memory unit 51c, a buffer unit 51d, and a buffer lead unit 51e. The data converter 51a mutually converts the size of the parallel IPC frame to the size of the parallel data used in the corresponding D-bus 40 or the corresponding switching means 50-1. The comparator 51b converts the size of the parallel IPC frame. The destination address information included in the header of the IPC frame applied through 51a) is compared with the address information stored in the memory unit 51c, and the IPC frame is recorded in the corresponding buffer of the buffer unit 51 according to the comparison result. The memory unit 51c stores a routing table indicating address information for each U-link node 52-1 to 52-n, and the buffer unit 51d stores the U-link node 52 of the switching means. It is composed of a buffer corresponding to the number of -1 to 52-n), and stores the IPC frame recorded by the comparator 51b in the buffer. The buffer read section 51e reads the IPC frame stored in the corresponding buffer among the buffer sections 52-1d of the U-link nodes 52-1 to 52-n and applies it to the data converter 51a.

Then, the configuration of each of the U-link nodes 52-1 to 52-n will be described using the U-link node # 1 52-1 as an example. The serial / parallel converter 52-1a and the comparator (52-1b), a memory unit 52-1c, a buffer unit 52-1d, a buffer lead unit 52-1e, and a parallel / serial converter 52-1f. The serial / parallel converter 52-1a converts the serial IPC frame input through the U-link into a parallel IPC frame and applies it to the input terminal of the comparator 52-1b, and the comparator 52-1b is serial / parallel. The corresponding buffer of the buffer unit 52-1d according to the result of comparing and comparing the destination address information included in the header of the IPC frame applied from the converter 52-1a with the address information stored in the memory unit 52-1c. Record the IPC frame. The memory unit 52-1c stores a routing table indicating address information for the D-bus node 51 and address information for each of the U-link nodes 52-1 to 52-n, and the corresponding buffer unit. 52-1d is composed of a buffer corresponding to the sum of the number of D-bus nodes 51 and the number of U-link nodes 52-1 to 52-n of the switching means, and the comparator 52-1b. Stores IPC frames recorded by the corresponding buffer. The buffer lead section 52-1e is an IPC frame stored in a corresponding buffer among the D-bus nodes 51 or the buffer sections 51d and 52-1d of each of the U-link nodes 52-1 to 52-n. Is read and applied to the parallel / serial converter 52-1f, and the parallel / serial converter 52-1f converts the parallel IPC frame applied from the buffer read section 52-1e into a serial IPC frame to obtain U-. It transmits to the processor unit 60-1 to 60-n through a link.

The IPC frame switching operation in the IPC system according to the present invention configured as described above is performed in the same order as shown in FIG. 5. In this case, for convenience of description, the U-link node # 1 (52-5) shown in FIGS. A reference numeral will be described as transmitting an IPC frame from processor # 1 61-1 connected to 1) to processor # 2 61-2 connected to U-link node # 2 52-2.

First, when a specific processor 61-1 of the processor unit 60-1 which wants to transmit an IPC frame sends out a serial IPC frame to the U-link node 52-1 via the U-link (step S51), The U-link node 52-1 writes the serial IPC frame transmitted through the U-link to the buffer unit 52-1d, and the serial / parallel converter 52 of the U-link node 52-1. -1a) converts the received serial IPC frame into a parallel IPC frame (step S52), and applies the converted parallel IPC frame to the input terminal of the comparator 52-1b.

Accordingly, the comparator 52-1b compares the destination address information included in the header of the authorized parallel IPC frame with the address information of the routing table stored in the memory unit 52-1c, and according to the result of the comparison, the buffer unit 52. -1d), where the first column of the routing table contains address information for U-link node # 1 (52-1), and the second column contains information about U-link node # 2 (52-2). In the same way, address information for U-link node #n (52-n) is stored in the nth column, and address information for D-link node 51 is stored in the n + 1th column. Address information for each U-link node (52-1 to 52-n) is each processor (61-1 to 61) connected to the corresponding U-link node (52-1 to 52-n) through the U-link -n) is associated with the address. On the other hand, the comparator 52-1b checks whether there is address information that matches the destination address information of the corresponding IPC frame (step S53), and if there is no address information that matches the destination address information, that is, The buffer unit 52-1d outputted to the D-bus node 51 when the destination address information of the IPC frame is not the address information of the processor of the processor unit 60-1 connected to the corresponding switching means 50-1. The parallel IPC frame is recorded in the corresponding buffer (step S54).

At this time, the buffer read section 51e of the D-bus node 51 reads out parallel IPC frames stored in the corresponding buffers among the buffer sections 52-1d of the U-link node 52-1 (step). S55) The read parallel IPC frame is applied to the data converter 51a.

Accordingly, the data converter 51a converts the applied parallel IPC frame into the parallel data size used by the D-bus 40 and sends it to the D-bus 40 (step S56).

Subsequently, when the parallel IPC frame is sent to the D-bus 40 and input to the data converter 51a configured at the D-bus node 51 of each switching means 50-1 to 50-n, the corresponding data converter ( 51a) converts the input parallel IPC frame into the parallel data size used by the switching means 50-1 (step S57), and applies the converted parallel IPC frame to the input terminal of the comparator 51b.

Accordingly, the comparator 51b compares the destination address information included in the header of the applied parallel IPC frame with the address information of the routing table stored in the memory unit 51c, and records the result in the buffer unit 51d according to the comparison result. If there is no address information that matches the destination address information of the parallel IPC frame (step S58), the address information corresponding to the destination address information does not exist, that is, the destination address information of the corresponding IPC frame corresponds to the corresponding address information. If it is not the address information of the processor of the processor unit 60-1 connected to the switching means 50-1, the IPC frame switching operation is terminated without receiving the corresponding parallel IPC frame, and if the destination address information and That is, when there is matching address information, that is, the destination address information is associated with the processor of the processor unit 60-1 connected to the switching means 50-1. If the address information, the comparator (51b) records the IPC parallel to the frame buffer of the buffer unit (51d) that is output to the U- bus node 51-2 (step S59).

At this time, the buffer lead portion 52-2e of the U-bus node 51-2 reads the parallel IPC frame stored in the buffer configured in the buffer portion 51d of the D-link node 51 (step). S60), the read parallel IPC frame is applied to the parallel / serial converter 52-2f.

Accordingly, the parallel / serial converter 52-2f converts the applied parallel IPC frame into a serial IPC frame and transmits the same to the corresponding processor 61-1 of the processor unit 60-1 through the corresponding U-link. (Step S61), the IPC frame switching operation ends.

On the other hand, in step S53, if there is address information that matches the corresponding destination address information, that is, the destination address information of the IPC frame is sent to the processor of the processor unit 60-1 connected to the switching means 50-1. In case of the address information, the comparator 52-1b writes the parallel IPC frame to the corresponding buffer of the buffer unit 51d outputted to the U-bus node 51-2 (step S62), and then starts the operation of step S60. This operation ends the IPC frame switching operation.

In the IPC system according to the present invention as described above, each switching means 50-1 to 50-n has n U-link interface functions by each of the U-link nodes 52-1 to 52-n, The n-processors 61-1n to 61-n provided in the processor units 60-1 to 60-n connected through the corresponding U-links may be matched, respectively. That is, the number of U-link nodes 52-1 to 52-n is the same as the number of processors 61-1 to 61-n connected to the respective switching means 50-1 to 50-n.

In addition, the buffer sections 52-1d, 52-2d, ... of the U-link nodes 52-1 to 52-n each comprise a U-link node 52-1 constituting the corresponding switching means 50-1. Since the number of buffers is larger than the number of ˜52-n), the IPC frame output to the D-bus node 51 can be recorded, so that the switching means 50-1 performs the corresponding D-bus node 51. FIG. D-bus matching is enabled, and the corresponding processor can be expanded accordingly.

The D-bus nodes 51 and the plurality of U-link nodes 52-1 to 52-n constituting each switching means 50-1 to 50-n can switch IPC frames by themselves. If switching of the IPC frame is required from U-link node # 2 52-2 to U-link node # 1 52-1, the corresponding U-link node # 2 52-2 is buffered. When the IPC frame is recorded in # 21, the U-link node # 1 (52-1) reads the IPC frame recorded in the buffer # 21 of the U-link node # 2 (52-2) and sends it to the U-link. do. That is, the IPC frame input to U-link node # 2 (52-2) is recorded in buffer # 2x (x is 1, 2, ..., n, n + 1), and U-link node # 1 (52-). 1) to U-Link Node # 2 (52-2), and to U-Link Node #n (52-n) in the same way. When sending, the corresponding IPC frame is recorded in the buffer # 2n, and when the U-link node to send the corresponding IPC frame does not exist in the switching means 50-1 to which it belongs, that is, the memory unit 52 If there is no address information of the U-link node to be transmitted in the routing table stored at -2c), the corresponding IPC frame is recorded in the buffer # 2n + 1, which is a buffer output to the D-bus node 51.

Accordingly, the buffer lead portions 51e, 52-1e, 52-2e, ... of the D-bus node 51 or the U-link node portions 52-1 to 52-n have their own buffers, that is, themselves. If an IPC frame is recorded in the buffer to be read, the IPC frame recorded in the buffer is read and sent to the U-link or D-bus 40. For example, the buffer lead portion 52-1e of the U-link node # 1 52-1 is the buffer # 1 of the D-bus node 51 or the other U-link nodes 52-2 to 52-. The IPC frame recorded in buffer # y1 (y is 2, 3, ..., n) of n) is read.

In addition, when an IPC frame having a broadcast function is received through the D-bus 40 or the U-link, the destination address information of the corresponding IPC frame includes all the address information of the routing table stored in the memory unit of each node. Since it matches, the corresponding IPC frame is recorded in all buffers configured in the buffer unit.

As described above, the present invention configures the IPC system to pass through the D-bus only when necessary for switching between the processors in the IPC system, thereby enabling IPC frame switching between processors without passing through the D-bus. Therefore, the IPC frame switching speed and switching efficiency between the processors can be improved.

Claims (5)

A D-bus implemented on the backplane of the switching system; An IPC frame switching device having a plurality of processor units for transmitting and receiving an IPC frame through a U-link, And a plurality of switching means for providing a D-bus matching function and a U-link matching function to connect the D-bus and the processor unit, wherein the switching means is connected to the D-bus to provide an IPC frame switching function between switching means. Providing a D-bus node; A plurality of U-link nodes providing an IPC frame switching function between the processors of the processor unit connected through a U-link and at the same time providing an IPC frame switching function with the D-bus node; And a switching matrix for switching the IPC frame between the D-bus node and the U-link node or the U-link node. The method of claim 1, The D-bus node comprises: a data converter for converting a size of a parallel IPC frame into a size of parallel data used in the D-bus or the switching means; A memory unit for storing a routing table indicating address information for the U-link node; A buffer unit configured of a buffer corresponding to the number of U-link nodes of the switching means and storing the recorded IPC frame in a corresponding buffer; A comparator for comparing the destination address information of the IPC frame applied through the data converter with the address information stored in the memory unit and recording the IPC frame in a corresponding buffer of the buffer unit according to a result of the comparison; And a buffer read part configured to read an IPC frame stored in a buffer of the U-link node. The method of claim 1, The U-link node includes a serial / parallel converter for converting a serial IPC frame input through a U-link into a parallel IPC frame; A memory unit for storing a routing table indicating address information for the D-bus node and address information for the U-link node; A buffer unit configured of a buffer corresponding to the sum of the number of D-bus nodes and the number of U-link nodes of the switching means, and storing the recorded IPC frame in a corresponding buffer; A comparator for comparing the destination address information of the IPC frame applied from the serial / parallel converter with the address information stored in the memory unit and recording the IPC frame in a corresponding buffer of the buffer unit according to the comparison result; A buffer read section for reading an IPC frame stored in a buffer of the D-bus node or a U-link node; And a parallel / serial converter for converting a parallel IPC frame applied from the buffer read part into a serial IPC frame. In the IPC frame switching method for switching the IPC frame between each processor connected to one switching means in the IPC system without passing through the D-bus, Converting the serial IPC frame transmitted through the U-link into a parallel IPC frame; Checking the destination address information of the parallel IPC frame and writing an IPC frame to a buffer output to a U-link node for address information corresponding to the corresponding destination address information; And reading the parallel IPC frame recorded in the buffer by the U-link node, converting the parallel IPC frame into a serial IPC frame, and then transmitting the serial IPC frame to the processor through the U-link. In the IPC frame switching method for switching the IPC frame via the D-bus between the processors respectively connected to different switching means in the IPC system, Converting the serial IPC frame transmitted through the U-link into a parallel IPC frame; Checking the destination address information of the parallel IPC frame and writing an IPC frame to a buffer outputted to a D-bus node for address information corresponding to the corresponding destination address information; Reading the parallel IPC frame recorded in the buffer by the D-bus node and converting the size of the parallel IPC frame into a parallel data size used in the D-bus; Transmitting the converted parallel IPC frame to a D-bus; Converting the parallel IPC frame sent to the D-bus into the parallel data size used by the corresponding switching means; Checking the destination address information of the converted parallel IPC frame and if there is address information that matches the destination address information, recording the IPC frame in a buffer output to the U-link node for the address information; And reading the parallel IPC frame recorded in the buffer from the U-link node and transmitting the parallel IPC frame to the processor through the U-link.