KR100384212B1 - Conditional Access information arrangement - Google Patents

Abstract

For processing the transmitted entitlement control information, an apparatus in the receiver may include a packet transport processor 13 for selecting signal packets having payloads including a conditional access payload header and the remaining payload of the entitlement data. -15, 19). Each payload header includes groups of bytes coded in a manner that allows each receiver to process or disallow entitlement data. Conditional access filter 30 preprogrammed with a subscriber specific conditional access codeword checks the byte groups in the conditional access header for matching with the subscriber specific conditional access codeword. Only when a match occurs, the processor is allowed to process the entitlement data (17, 18, 21-24). The entitlement data is then used to generate 31 decryption keys for descramble 16 portions of the transmitted signal.

Description

Conditional Access Information Arrangement

For example, US Pat. No. 5,168,356 and US Pat. No. 5,289,276 are known to transmit compressed video signals in packets with means of error prevention / correction. The systems in the aforementioned patents have multiple program components from respective transport channels, but transmit and process a single television program. These systems use inverse transport processors to further extract the video signal component of each program and adjust the video component for playback.

For example, in "THE SATELLITE BOOK, A COMPLETE GUIDE 70 SATELLITE TV THEORY AND PRACTICE" published by Swift TV in Crickclade, Pittsfield 17, UK, the transmitted television signal reception scrambles the signal, It is known that these may be limited. These restrictions can be changed at will of the broadcaster by periodically transmitting different entitlement data. Entitlement data is processed by smart cards located at the respective receivers to generate decryption or descrambling keys, which are just their receivers entitled to play associated program material. Used by decryption or descrambling devices. In a packet video system of the type described above, entitlement data may be included in certain packets that can be recognized as containing such data for easy access by a smart card circuit.

Wide area broadcast systems, such as direct broadcast satellite systems used in North America, have a very large number of subscribers. The number of these subscribers is too large to change the entitlement data of certain receivers in a very short notice. For example, if tickets for sporting events are not sold, assume that the station needs to stop broadcasting for the area confined to the sports stadium. Such information may not be available until just before the event. Of course, the station will want to wait for the last few minutes possible before making a decision to stop broadcasting in the area. The present invention provides a method and apparatus for stratifying entitlement data to negate entitlements for receiving program material in a short time.

FIELD OF THE INVENTION The present invention relates to an apparatus for processing packets of program component data from a packet video signal, in particular circuitry for detecting packet payloads in which a subscriber has conditional access to entitlement information. It is about.

1 shows a time division multiplexed packet television signal;

2 shows respective signal packets.

Figure 3 is a block diagram illustrating a receiver for selecting and processing packets of multiplexed component signals embodying the present invention.

4 is a block diagram illustrating a conditional access filter / start code detector.

5 is a flow diagram illustrating conditional access filter operation.

6 is a block diagram of an alternative conditional access filter.

FIG. 7 is a block diagram illustrating an exemplary memory management circuit that may be implemented for the element 17 of FIG.

Fig. 8 shows memory address information for service channel data.

Fig. 9 is a flowchart showing the operation of memory address control.

The present invention relates to a system and method for transmitting / receiving layered entitlement data. In one embodiment, the receiver comprises a packet transport processor for selecting packets having payloads comprising a conditional access payload header and a remaining payload of entitlement data. Each payload header includes groups of bytes coded in such a way as to allow or not process each receiver's entitlement data. The conditional access filter, preprogrammed with the subscriber specific conditional access codeword, checks each byte groupings of the conditional access header for matching with the subscriber specific conditional access codeword. Only when a match occurs, the processor is allowed to process the entitlement data.

1 shows a packet signal stream consisting of a series of boxes representing signal packets, the signal packets comprising components of a number of different television programs or interactive television programs. It is assumed that these program components are formed of compressed data, and the amount of video data for each image can be varied. These packets are of fixed length. Packets with characters with the same subscripts represent single program components. For example, V _i , A _i , D _i represent video, audio and data packets, and packets designated V ₁ , A ₁ , D ₁ represent video, audio and data components for program 1, and V ₃ , A ₃₁ , A ₃₂ , and D ₃ represent the video, audio1, audio2 and data components of program 3. The data packets D _i may comprise control data for initiating some action in the receiver, for example, and also form an application to be executed by a microprocessor located in or associated with the receiver, for example. May contain executable code.

In the upper line of the row of packets, the respective components of a particular program are shown grouped together. However, packets of the same program do not necessarily have to be grouped as indicated by the entire row of packets. In addition, the sequence for the generation of the individual components need not be in any particular order.

Each packet is arranged to include a prefix and a payload as shown in FIG. The prefix of this example includes two 8-bit bytes containing five fields, where four of the five fields (P, BB, CF, CS) are 1-bit fields and the other one (SCID) Is a 12-bit field. The SCID field is a signal component identifier. The field CF includes a flag to indicate whether the payload of the packet is scrambled, and the field CS is used to unscramble packets with which of two alternative unscrambling keys is scrambled. Contains a flag indicating whether it should be. The prefix of all packets is packet aligned, whereby the location of each field can be easily identified.

Within every payload is a header that contains the program component properties, continuous count CC, modulo 16, and TOGGLE flag bits. Consecutive count is the successive numbering of sequential packets of the same program component. The TOGGLE flag bit is a 1-bit signal that changes or toggles the logic level when a picture layer start code occurs in the MPEG compressed video component.

3 shows in block form a portion of a digital television signal receiver including elements of an inverse transport processor. The signal detected by the antenna 10 is applied to the tuner detector 11, which extracts a particular frequency band of the received signals and provides a baseband compressed signal in binary format. The frequency band is selected by the user through the microprocessor 19 by conventional methods. Typically, broadcast digital signals have been error encoded using Reed Solomon Forward Error Correction (FEC) coding, for example. As such, band signals will be applied to the FEC decoder 12. The FEC decoder 12 synchronizes the received video and provides an error corrected stream of signal packets of the type shown in FIG. FEC 12 may provide packets at regular intervals or as needed, for example by memory controller 17. In any case, a packet framing or synchronization signal is provided by the FEC circuit, which indicates the number of times each packet information is transmitted from the FEC 12.

The detected frequency band may include a plurality of time division multiplexed programs in a packet form. For usability, only packets from a single program must be passed to other circuit elements. In this example, it is assumed that the user does not know the packets to select. This information is included in a program guide, which is itself a program that contains data that correlates program signal components via SCIDs, and may include, for example, information relating to subscriber entitlements. Can be. The program guide is a listing of SCIDs for each program, which are for the components of each program, such as audio, video, data, and so on. The program guide (packets D4 of FIG. 1) is assigned a fixed SCID. When the receiver is powered up, the microprocessor 19 is programmed to load the SCID associated with the program guide into one of the banks of similar programmable SCID registers 13. SCID fields of the prefix portion of each detected packets of the signal from FEC 12 are successively loaded into the other SCID register 14. The programmable registers and the received SCID register are coupled to respective input ports of comparator circuit 15 and the received SCID is compared with the program guide SCID. If the SCID for the packet matches the program guide SCID, the comparator 15 adjusts the memory controller 17 to route the packet to a predetermined location in the memory 18 for use by the microprocessor. If the received SCID does not match the program guide SCID, the corresponding packet is only dumped.

The microprocessor waits for programming instructions from the user through the interface 20, which is shown as a computer keyboard but can be a conventional remote controller or receiver front panel switches. The user may request to watch the program provided on channel 4 (in the native language of analog TV systems). The microprocessor 19 scans the program guide list that has been loaded into the memory 18 for each SCID of the channel 4 program components, and the corresponding component signal processing path of the programmable registers of the bank of registers 13. Are programmed to load these SCIDs into each of the other registers associated with them.

As a result, received packets of audio, video or data program components for the desired program must be routed to audio 23, video 22 or auxiliary data 21 and 24, signal processors respectively. Data is received at a relatively constant rate, but signal processors typically require input data in bursts (eg, depending on the type of decompression). The exemplary system of FIG. 3 first routes each packet to predetermined memory locations in common memory 18. Thereafter, each of the processors 21 to 24 requests component packets from the memory 18. Routing components through common memory provides a means of buffering or throttling the desired signal data rate.

Audio, video and data packets are loaded into respective predetermined memory locations for easy buffered access to component data by signal processors. In order for the payloads of each component packet to be loaded into the appropriate memory regions, each SCID comparators are associated with those memory regions. This association may be connected by wiring at the memory controller 17 or the association may be programmable. In the former case, certain of the programmable registers 13 will always be assigned audio, video and data SCIDs, respectively. In the latter case, the audio, video and data SCIDs can be loaded into any of the programmable registers 13 and an appropriate association is programmed into the memory controller 17 when each SCID is loaded into the programmable registers. Will be.

In the normal state, after the SCIDs of the program are stored in the programmable registers 13, the SCIDs of the received signal packets are compared with all SCIDs in the programmable SCID registers. Upon matching with any of the stored audio, video or data SCIDs, the corresponding packet payload will be stored in an audio, video or data memory area or block respectively.

Each signal packet is coupled from the FEC 12 to the memory controller 17 via a signal decryptor 16. Only signal payloads are scrambled, and packet headers are passed through the decryptor without modification. Whether the packet is to be descrambled is determined by the CF flag in the packet prefix, and how the packet is descrambled (one of two alternative descrambling keys) by the CS flag. If no SCID matching is done for each packet, the decryptor can simply be disabled to not pass all the data.

The decryptor is programmed with decryption keys provided by the smart card device 31. The smart card generates appropriate decryption keys in response to the entitlement information contained in the particular packets of the program announcement. The system of this example includes two levels of encryption or program access, namely entitlement control messages (ECMs) and entitlement management messages (EMMs). Program entitlement control and management information is transmitted regularly in packets that can be identified with specific SCIDs included in the packet stream containing the program announcement. The ECM information contained in these packets is used by the smart card to generate decryption keys for use by the decryptor. The EMM information contained in these packets is used by the subscriber's specific smart card to determine the program material to which the subscriber is entitled. The EMM entitlement information in these packets may be geographically specific, or may be group specific or subscriber specific. For example, the system may include a modem (not shown) for communicating toll information from a smart card to a program provider, such as a satellite station. Smart cards can be programmed, for example, with area codes and telephone exchanges of receiver locations. The EMM, when processed by a smart card, may contain data that entitles or denies reception of certain programs with specific area codes.

The program provider may want the ability to entitle to some subscribers in a very short lead time, such as, for example, a pay-per view program. Identification of certain subscribers may not be available until immediately before the broadcast of a particular program. With such a short lead time, it may not be possible to program EMMs on a subscriber basis. Another layer of coding can be instantaneously provided on entitlement information by including in each packet a conditional access code that allows / prohibit the receipt of EMM and ECM data, thereby substantially eliminating certain programs. Enables instant permission / prohibition

Packet payloads containing EMM and ECM entitlement data include a 128-bit payload header arranged in four groups of specifically coded 32 bits. Each of the groups is coded with a conditional access code, and each conditional access code can be coded differently. Each subscriber is assigned a specific conditional access code. The matched filter or E-code decoder 30 is arranged to detect the subscriber specific bit pattern in the 128 bit header. If a match is detected, the decoder communicates with the memory controller 17 and the smart card 31 so that the remainder of the entitlement payload is utilized for the smart card (via memory 18). If no match is detected, the payload is not accepted by the particular receiver. Conditional access codes can be changed periodically if the matched filter 30 becomes programmable. These codes may be provided periodically by the smart card. See section 25 of "THE SATELLITE BOOK, A COMPLETE GUIDE TO SATELLITE THEORY AND PRACTICE" for a more detailed description of smart card operation related to viewer entitlements.

The matched filter or E-code decoder is arranged to perform a second function of detecting certain MPEG video headers. These headers are 32 bits of start codes (this is why the headers of entitlement payloads are coded into 32 bit groups). In the case where video data is lost, the MPEG video decoder can only resume decompression of the video data at certain data entry points. These entry points match the MPEG start codes. The decoder controls the memory controller 17 to prevent video data from flowing into the memory after the video packet is lost and to resume writing the video payload into the memory only after the next MPEG start code is detected by the decoder 30. May be arranged to communicate.

4 shows an example of an exemplary apparatus for detecting packets containing conditional access information or MPEG start codes (decoder 30 of FIG. 3). Whether decoder 30 has been adjusted to detect entitlement payloads or MPEG start codes is a function of the currently received SCID. In FIG. 4, it is assumed that the data provided from the decryptor 16 is 8-bit bytes and is packet aligned. That is, the first byte of the entitlement payload or the first byte of the MPEG start code is aligned precisely with a specific byte position, e.g., the beginning of the packet payload, to detect specific header or start code words. Know exactly where they are in the byte stream. Data from the decryptor 16 is applied to an 8 bit register 250, which has an 8 bit parallel output port coupled to respective first input connections of the comparator 254, the comparator being AND For example, it may consist of a bank of circuits of eight two-input exclusive NOR (XNOR) with respective output connections coupled to the gate and latch. The latch may be a data latch arranged to latch the results of the AND gate at each byte interval.

The 32 bit MPEG start code is stored as 4 bytes in the 8 bit register bank 265. Conditional access codes are stored as 8-bit bytes in a bank of sixteen 8-bit registers 251. The loading of register banks 251 and 265 is controlled by microprocessor 19 and / or smart card. Start code registers 265 are coupled to a 4 to 1 multiplexer 266, and conditional access code registers are coupled to a 16 to 1 multiplexer 257. Output ports of the multiplexers 257 and 266 are coupled to a two-to-one multiplexer 249. Respective output connections of multiplexer 249 are coupled to respective corresponding second input terminals of comparator 254. [Note that the input and output connections of the multiplexers 249, 257 and 266 are 8 bit buses]. If the respective values appearing at the respective output connections of register 250 are correspondingly identical to the output values represented by the respective output connections of multiplexer 249, then the comparator 254 circuit is then updated for the corresponding data byte. This produces a true signal.

For start code detection, multiplexer 266 is scanned by counter 258 to write four different registers 265 to the comparator concurrently with the generation of the first four payload data bytes from decryptor 16. Combine sequentially. Alternatively, for conditional access code detection, multiplexer 257 is scanned by counter 258 to sequentially combine different ones of registers 265 into comparator circuit 254.

The output of the comparator circuit is applied to the accumulation and test circuit 255. This circuit 255 determines what predetermined number of byte matching conditions have been generated and, if those conditions are generated, generates a write enable signal for the entitlement data in the remainder of the particular payload under inspection. do. In the present system, the entitlement payload header includes 128 bits arranged in four 32-bit conditional access codes. Conditional access filters 30 of different subscribers will be arranged to find different byte combinations of 128 bits. For example, one subscriber device may be arranged to match the first 4 bytes of conditional access codes. Another subscriber device may be arranged to match a second four bytes, such as conditional access codes. In any of these typical cases, circuit 255 will determine whether a match has occurred for the appropriate four consecutive bytes.

The use of 16 registers in the bank for subscriber specific conditional access codes simplifies the circuit structure. Since each subscriber has a four byte conditional access code, this code can be loaded four times in a set of sixteen registers. As such, at the transmitter, the broadcaster does not have to worry about the relative location of the conditional access codes transmitted for four groups of 4 bytes. An alternative apparatus may include only a single group of four registers holding a subscriber specific conditional access code, which registers may be repeatedly examined modulo 4, through the 128 bits of the entitlement payload header. .

Sending each of the 2 ³² possible entitlement codes for all functions is impractical, because it undesirably limits the system bandwidth for other services and also takes too much time. This restriction can be somewhat mitigated by arranging the conditional access code according to some logical groupings, where groupings are defined as 3 bytes of each 4 byte conditional access codes. In this way, all subscribers in the group can be addressed by adjusting the respective receivers of the group to ignore one byte of the four byte conditional access code. In this example, each four byte access code will represent 256 subscribers. Filter adjustment is performed, for example, by sending all zeros at the first four byte positions and arranging the conditional access filter to detect this condition. If this condition is met, the conditional access filter is electrically reconfigured to detect a match of only 3 bytes of each group of 4 bytes.

A third variant is provided to allow conditional access of all subscribers. This is done by coding the entitlement payload header all zeros (or all 1s). Therefore, the conditional access filter is also arranged to include all zero detectors (elements 261 to 263).

The bits of each arriving byte of data are coupled to respective terminals of the 8 bit OR gate 263. If any one of the bits is logic one, OR gate 263 generates the output of logic one. An output of the OR gate 263 is coupled to a first input of a two input OR gate 262 having an output and a second input coupled to the data-input and Q-output terminals of the D-type latch 261, respectively. . The D-type latch is clocked by the timing circuit 259 simultaneously with the arrival of incoming data bytes. If any bit in any data bytes that occur after the latch is reset, latch 261 will indicate logic 1 at the Q-output until the next reset pulse. The Q-output of latch 261 is coupled to an inverter representing zero output level whenever the latch represents one output level. Thus, after the 128 bits (16 bytes) of the header pass through the register 250, if the output of the inverter goes high, the 128 bits become zero values. The latch is reset prior to the receipt of each new payload. In response to detection of the high output level from the inverter after passing the entitlement payload header, circuit 255 will generate a data write enable signal.

5 is a flowchart of the operation of conditional access filter 30. This process is started by the detection of the associated SCID. Once the appropriate SCID is detected, the payload is applied to the filter 30 {300}. A comparison of the subscriber specific conditional access code and the first 4 bytes of the header is made {302}. If a match occurs, an entitlement data write enable is generated (310). Otherwise, the first 4 bytes are all checked for zero (306). If all are not detected as zeros, the second 4 bytes of the header are compared with the subscriber specific conditional access code {308}. If they match {312}, write enable is generated {310}. Otherwise, the third set of 4 bytes is compared with the subscriber specific conditional access code {314}. If they match {316}, a write enable occurs {310}. Otherwise, the fourth set of 4 bytes is compared with the subscriber specific conditional access code {317}. If they match 318, a write enable occurs {310}. Otherwise, the last 12 bytes of the header are all checked for zero (320). If the last 12 bytes are all detected as zeros, a write enable is generated (310), otherwise no write enable is generated, and the process waits for the next packet (300). In an alternative apparatus, at step 320, the system may be programmed to check that all 16 bytes of the header are all zeros. It can also be seen that any other fixed pattern other than zeros, for example all 1's, or patterns with alternating zeros and ones, may be used.

In step 306, if the first four bytes are all zero, three of the second four bytes of the header are compared with the subscriber specific conditional access code {354}. In the apparatus of FIG. 4, this can be accomplished by arranging element 255 to find three matches for exclusive groups of four bytes. If three of the four bytes match {326}, a write enable is generated {322}, otherwise three of the four sets of four header bytes are compared with a subscriber specific conditional access code {330}. If three of the four bytes match {332}, a write enable is generated {322}, otherwise three of the last four bytes are compared with a subscriber specific conditional access code {336}. If they match, write enable is generated (322), otherwise all zero conditions are checked (320).

Note that other levels of detection may be included, similar to steps {324-340} where only two of each group of 4 bytes are matched. This can be adjusted, for example, by arranging the first eight bytes to be all zeros or by arranging the first four bytes to be all ones. In this example, the respective groups enabled by the conditional access codes are much larger.

Regarding storing the entitlement payloads in memory 18, the system writes the payload header into the memory when received and checked for conditional access codes. If a conditional access code is detected, the detected write enable causes memory control to continue writing the payload. Conversely, if a conditional access code is not detected within the first 16 bytes of the payload, the remaining payload is not written to the memory and the memory address for the conditional access payload is set to the payload conditional access header. Reset to overwrite 16 bytes.

6 is an alternative conditional access filter comparing 32 bits (4 bytes) at a time. This makes it possible to detect start codes without prior knowledge of the byte position of the start code. The start code is stored in 8-bit registers 265. (8-bit registers are used because an 8-bit μPC bus is used.) The output ports of the registers are coupled to the inputs of the first set of multiplexer 298. The subscriber specific conditional access code is stored in a second register bank 299 having respective output ports coupled to inputs of the second set of multiplexer 298. Multiplexer 298 has a set of outputs connected to each of the first 8-bit input ports of comparators 270-273. Whether the output ports of registers 265 or 299 are coupled to the comparators is controlled by the accumulation and test circuit 297 responsive to μPC.

Input bytes from decryptor 16 are coupled to parallel / serial registers 274-277. Each register 274-277 has parallel output ports coupled to the second 8-bit input ports of the comparators 270-273, respectively. The system is timed such that four consecutive bytes of the input signal are currently loaded into registers 274-277. Output terminals of the comparators are coupled to the accumulation and test circuit 297 through respective OR gates 278-281. Second input terminals of the OR circuits are coupled to respective control output connections of the accumulation and test circuit 297.

Like the apparatus of FIG. 4, the apparatus of FIG. 6 includes an all zero detector 261-263 for detecting that the first 4 bytes and all 16 bytes are all zero.

For four byte conditional access code detection, consecutive exclusive groups of four bytes are loaded into registers 274-277 and tested for subscriber specific conditional access code included in registers 299. If all four comparators detect a match, AND gate 283 generates a logic one indicating the match. If one of the comparators fails to detect a match, the AND gate generates a logic zero. To detect three of the four input byte conditional access code sets, the accumulation and test circuit 297 applies a logic 1 value to one of the control lines coupled to the OR gates. This causes the output of the OR gate to be logic 1, effectively forcing matching from the associated comparator. As such, conditional access code detection is performed on successive exclusive 4-byte groups such as 4-byte detection.

For start code detection, the control lines of all OR gates remain at logic zero. Input bytes are applied sequentially to the cascade connection of registers 274-277, and a test to match the start code stored in registers 265 is performed for each successive comprehensive set of 4 input bytes. .

FIG. 7 shows a typical device for the memory controller 17 shown in FIG. Each program component is stored in a different contiguous block of memory 18. In addition, other data such as data generated by the microprocessor 19 or a smart card (not shown) may be stored in the memory 18.

Addresses are applied to the memory 18 by the multiplexer 105 and input data is applied to the memory 18 by the multiplexer 99. Output data from the memory management circuitry is provided to signal processors by another multiplexer 104. Output data provided by the multiplexer 104 is derived directly from the microprocessor 19, memory 18, or multiplexer 99. Program data is assumed to be at standard image resolution and quality, and occur at a particular data rate. On the other hand, high-definition television signals, HDTVs, which can be provided by the receiver, occur at significantly higher data rates. Substantially, all data provided by the FEC is coupled to the multiplexer 99 and the memory I / O circuit 102, except for higher speed HDTV signals that can be routed directly from the multiplexer 99 to the multiplexer 104. It will be routed through the memory 18 via it. Data is provided to the multiplexer 99 from the decryptor 16, the smart card circuit, the microprocessor 19, and the source 100 of media error codes. As used herein, the term "media error codes" refers to special codewords to be inserted into a data stream, by adjusting each signal processor (decompressor) to determine a predetermined code such as a start code. The processing is stopped until a code word is detected, after which the processing is restarted according to, for example, a start code.

Memory addresses are provided to the multiplexer 105 from the program addressing circuit 79-97, from the microprocessor 19, from the smart card device 31, and from the auxiliary packet address counter 78. The selection of a particular address at any particular time interval is controlled by the direct memory access (DMA) circuit 98. SCID control signals from comparator 15 and " data needed " signals from respective signal processors are applied to DMA 98, and in response, memory access contention is established. Mediated. DMA 98 cooperates with service pointer controller 93 to provide appropriate read or write addresses for each program signal component.

Respective addresses for the various signal component memory blocks are generated by four groups of program component or service pointer registers 83, 87, 88 and 92. Start pointers for the respective blocks of the memory where the respective signal components are stored are included in registers for the respective signal components. The start pointers may be fixed values or may be calculated by conventional memory management methods in the microprocessor 19.

Pointers to the final address of each block are stored in a bank of service registers 88, one pointer for each potential program component. Similar to the start addresses, the end or final addresses may be fixed values or may be calculated values provided by the microprocessor 19. It is desirable to use calculated values for the start and end pointers, because it provides a more versatile system while using less memory.

Memory write pointers or head pointers are generated by adder 80 and service head registers 83. There is a service head register for each potential program component. The write or head pointer value is stored in register 83 and provided to address multiplexer 105 during a memory write cycle. The head pointer is also coupled to the adder 80, where the head point is incremented by one unit and the incremented pointer is stored in the appropriate register 83 for the next write cycle. Register 83 is selected by service pointer controller 93 for the appropriate program component that is currently being serviced.

In this example, the start and end pointers are assumed to be 16-bit pointers. Registers 83 provide 16 bit write or head pointers. Sixteen bit pointers are selected to facilitate the use of 16-bit or 8-bit buses for loading start and end pointers into registers 87 and 88. On the other hand, memory 18 has 18-bit addresses. The 18-bit write addresses are formed by concatenating the two most significant bits of the start pointers to the 16-bit head pointers, which start pointer bits are at the most significant bit positions of the combined 18-bit write address. Start pointers are provided to the service pointer controller 93 by respective registers 87. The service pointer controller parses the upper start pointer bits from the start points stored in registers 87 and associates these bits with the 16-bit head pointer bus. This is illustrated by the bold arrows in FIG. 8, shown as bus 96 shown in combination with a head pointer bus exiting to multiplexer 85.

In Figure 8, the top, middle and bottom rows of boxes represent the bits of the start pointer, address and head or tail pointer, respectively. Larger numbered boxes indicate higher bit positions. The arrows indicate that each bit of the address is derived from the bit positions of the start or head / tail pointers. In this derivation, the bold arrows indicate steady state operation.

Similarly, memory read pointers or tail pointers are generated by adder 79 and service tail registers 92. There is a service tail register for each potential program component. The read or tail pointer value is stored in register 92 and provided to address multiplexer 105 during a memory read cycle. The tail pointer is also coupled to the adder 79, incremented by one unit, and the incremented pointer is stored in the appropriate register 92 for the next read cycle. Registers 92 are selected by the service pointer controller 93 for the appropriate program component that is currently being serviced.

Registers 92 provide 16 bit tail pointers. The 18-bit read addresses are formed by concatenating the two most significant bits of the start pointers to the 16-bit tail pointers, which are within the most significant bit positions of the combined 18-bit write address. The service pointer controller analyzes the upper start pointer bits from the start pointers stored in registers 87 and associates these bits with the 16-bit tail pointer bus. This is illustrated by the bus 94 shown in combination with a tail pointer bus that exits to the multiplexer 90.

The data is stored in memory 18 at the calculated address. After storing one byte of data, the head pointer is incremented by 1 and compared to the end pointer for this program element, and if they are the same, the upper bits of the head pointer are replaced by the lower 14 bits of the start pointer. The zeros are placed in the lower two bit positions of the head pointer portion of this address. This is illustrated in FIG. 8 with respect to the hatched arrows between the start pointers and the address. This operation is illustrated by arrow 97 pointing at the service pointer controller 93 to the head pointer bus from the multiplexer 85. It is assumed that the application of the lower 14 start pointer bits ignores the head pointer bit. By replacing the head pointer bits at the address with the lower start pointer bits for one write cycle, the memory scrolls through the memory block designated by the upper two start pointer bits, thereby writing at the beginning of each packet. Prevents reprogramming of addresses into unique memory locations within a block.

If the head pointer is always the same as the tail pointer (used to indicate the position to read data from memory 18), a signal is sent to the interrupt section of the microprocessor, so that a head-tail crash Indicates that it occurred. Further writing from this program channel to memory 18 is disabled until the microprocessor enables the channel again. This is very rare and does not occur in normal operation.

Data is retrieved from memory 18 at the request of respective signal processors at the addresses computed by adder 79 and registers 92. After reading one byte of stored data, the tail pointer is incremented by one and compared with the end pointer for the logical channel in the service pointer controller 93. If the tail and end pointers are the same, the upper bits of the tail pointer are replaced by the lower 14 bits of the start pointer, and the zeros are placed at the two bit positions below the tail pointer portion of the address. This is illustrated by arrow 95 coming out of controller 93 and pointing to tail pointer bus from multiplexer 90. If the tail pointer is identical to the current head pointer, each memory block is defined as empty and no more bytes will be sent to the associated signal processor until more data is received from the FEC for this program channel. Substantially replacing the head or tail pointer portions of each of the write or read addresses with the lower 14 bits of the start pointer can be accomplished by proper multiplexing or by the use of three state interconnections.

Memory read / write control is performed by the service pointer controller and direct memory access, ie DMA elements 93 and 94. The DMA is programmed to schedule read and write cycles. Scheduling depends on whether the FEC 12 provides data to be written to memory. FEC data write operations are prioritized so that no incoming signal component data is lost. In the typical device shown in FIG. 7, there are four forms in which the memory can be accessed. These are application devices such as smart cards, FEC 12 (more precisely decryptor 16), microprocessor 19 and audio and video processors. Memory contention is handled in the following manner. The DMA allocates memory blocks for the respective program components in response to data requests from the various processing elements listed above. Access to the memory is provided in 95 nS time slots, during which one byte of data is read from or written to memory 18. There are two main access assignment modes, each defined as "FEC Providing Data (FEC) that provides data" or "FEC Not Providing Data (FEC) that does not provide data". For each of these modes, time slots are allocated and prioritized as follows, assuming the maximum FEC data rate is 5M bytes / second, or 1 byte for each 200 nS. These are:

FEC provides data

1) write FEC data;

2) application device read / microprocessor read / write;

3) write FEC data;

4) Read / write microprocessor.

FEC not providing data

1) smart card read / write;

2) application device read / microprocessor read / write;

3) smart card read / write;

4) Read / write microprocessor.

Since FEC data writes cannot be delayed, the FEC (more precisely the decryptor) must guarantee memory access for each 200 nS interval when providing the data. Alternate time slots are shared by application devices and microprocessors. When there is no data available to the requesting devices, the microprocessor uses application time slots.

Controller 93 communicates with the SCID detector to determine which of the respective start, head and end pointer registers for access to memory write operations. The controller 93 communicates with the DMA to determine which of the start, end and tail registers for access to the memory read operations. DMA 98 controls the selection of corresponding addresses and data by multiplexers 99, 104 and 105.

9 shows an exemplary flow diagram of a memory access process of the DMA 98. The DMA responds to the detection or non-detection of the received packet via detection of SCIDs {200}. If the SCID is detected to indicate the presence of data from the decryptor 16 to be written to the memory, one byte of program data from the decryptor is written to the buffer memory 18 {201}. The block of memory to be written is determined by the processor 93 in response to the current SCID. The DMA then determines which of the program component processors, including the smart card and [mu] PC, requests data or read / write (R / W) access to the memory 18 (202). If no data request is made for the DMA, the process returns to step 200. When the data R / W request is executed, the DMA determines the request priority {203}. This may be accomplished by conventional interrupt routines or, alternatively, by one byte of service sequentially in any order of program processors requesting data. For example, assume that any order of access priority is video, audio I, audio II, smart card and μPC. In addition, assume that only video, Audido II and μPC require memory access. During the current operation of step {203}, one byte of video will be read from the memory. During the next operation of step {203}, one byte of Audio II will be read from the memory, and during the next operation of step {203}, one byte of μPC data is written to or written to memory 18 or the like. Will be read from. Note that addresses for smart card and μPC access are provided by the smart card and μPC respectively, but addresses for video, audio and program guides may be available from the address pointer device 80-93.

Once priority access is established {203}, the necessary program processor is serviced with one byte of data written to or read from memory 18 (204). Next, one byte of data from the decryptor 16 is written into the memory {205}. A check is made to determine whether the μPC is requesting access {206}. If the μPC requests access, one byte of data is served {207}. If the μPC does not request access, the process jumps to step {202} to determine which of the program processors is requesting access. do. In this way, incoming data is always guaranteed to be accessed in all other memory access periods, and arbitration memory access periods are spread between program processors.

If data is not currently used from decryptor 16, that is, no SCID is currently detected, process {208-216} follows. First, the smart card is checked to determine whether it is requesting memory access {208}. If so, one byte of memory access is provided {209}, otherwise a check is made to determine which of the program processors is requesting the memory access {210}. When a data R / W request is made, the DMA determines the priority of the request {211}. Appropriate processors are serviced with one byte of memory read or write access. If a data R / W request is not made by the program processors, the process jumps to step 203, where a test is performed to determine if the smart card requests memory access. If so, one byte of memory access is served {216}, otherwise the process jumps to step {200}.

In this example, when in FEC Not Providing Data (FEC) mode, the smart card is provided with two-to-one access precedence for all other program processors. It should be recognized. This priority is programmed into a programmable state machine in the DMA device and changed by μPC. As mentioned at the outset, the present system is intended to provide interaction services, and the μPC 19 will respond to the interaction data to perform at least partially interactive operations. In this role, μPC 19 will use memory 18 for application storage and working memory. In these examples, the system operator can change the memory access priority to provide more number of memory accesses to μPC. Reprogramming the memory access priority may be included as a subset of interactive application instructions.

There is an advantage to inserting media error codes into the video component signal stream when packets are lost, thereby adjusting the video signal decompressor to stop decompression until a particular signal entry point occurs in the data stream. It is impractical to predict where the next entry point will occur in the video packet. In order to find the next entry point as fast as possible, it is necessary to include a media error code at the beginning of the first video packet after detecting that the packet has been lost. The circuit of Figure 7 places a media error code at the beginning of every video packet and deletes the media error code from each packet if no preceding packet is lost. The media error code is inserted in the first M memory address locations held for the current video packet payload by writing to memory 18 during M write cycles prior to the video payload arriving from the decryptor. At the same time, the multiplexer 99 is adjusted by the DMA 98 to apply a media error code from the source 100 to the memory 18 I / O. M is just an integer of the memory locations needed to store the media error code. Assuming the memory stores 8-bit bytes and the media error code is 32 bits, M will be equal to four.

Addresses for loading the media error code into memory are provided by the respective video component service registers 83 through multiplexer 82 and multiplexer 85. The first M addresses provided from the pointer register 83 for loading the media error code into memory locations (otherwise the video component data) are typically the next M sequential generated by the video head pointer. It will be appreciated that the addresses will be. These same addresses are coupled to the M-stage delay element 84 such that immediately after the last byte of the media error code is stored in the memory 18, the first of the M addresses is the output of the delay element 84. To be used in.

The timing of loading the medium error code into memory is consistent with the determination of the lost packet. Packet error or loss detection is performed by the error detector 101 responsive to the CC and HD data of the current packet.

If a packet loss is detected, the video component of the current packet is stored in memory 18 starting at the next or (M + 1) th address location. This is accomplished by adjusting the multiplexer 85 to continue passing non-delayed head pointers from the appropriate register 83. Alternatively, if no packet loss is detected, the first M bytes of the video component of the current packet are stored in memory locations where the media error code was stored just before.

Packet error or loss detection is performed by the error detector 101 responsive to the CC and HD data of the current packet. Detector 101 checks the continuity count CC in the current packet by one unit to determine if it is different from the CC of the previous packet. In addition, it is checked to determine if the TOGGLE bit of the current packet indicates an appropriate state for each video frame. If the CC value is not correct, the state of the toggle bit is checked. Depending on whether one or both of the CC and TOGGLE bits are in error state, error correction in the first or second mode is performed respectively. In a second mode in which both the CC and TOGGLE bits begin with an error, the system is adjusted to reset to a packet containing a picture layer header. In the first mode where only CC has an error, the system is adjusted to reset to the packet containing the slice layer head. (The slice layer is a subset of the compressed data in the frame.) In both the first and second modes, media error codes written to the memory are held in each payload to inform the decompressor to perform a corrective operation.

It has been found that it is particularly efficient to partition the system so that the SCID detector, decryptor, addressing circuitry, conditional access filter and smart card interface are all contained in a single integrated circuit. This limits the number of external paths that can lead to significant timing limitations.

Claims (7)

A method of transmitting conditional access information including entitlement management and control data, the method comprising: Forming a plurality of N-byte conditional access codes of the same type, wherein each of the plurality of N-byte conditional codes a has the same length as the MPEG start code; Concatenating M of the N-byte conditional access codes, wherein M and N are integers greater than 1, and concatenating different N-byte conditional access codes; Selecting one of the N-byte conditional access codes or a particular N-byte conditional access code having an already determined logical state; a) comprising the selected one of the N-byte conditional access codes or the specific N-byte code, b) concatenating the selected code to a concatenation of the M different N-byte conditional access codes, M Forming a concatenation of +1 N-byte conditional access codes, c) forming a payload, connecting the concatenated codes to the entitlement management and control data; a) a header identifying a transport packet as containing entitlement data, and b) forming a transport packet with the payload. The method of claim 1, All of the R groups of N-bytes have (M + 1) x N byte codes [R, M, N all being integers, with bits of logical state already determined, and R x N is greater than Less than or equal to], Forming the payload is: a) selecting one of said N-byte conditional access codes or an N-byte code that is all in one logical state; b) connecting the selected code to the M different N-byte conditional access codes; c) selecting the (M + 1) x N byte code or the concatenated code; d) concatenating said entitlement management and control data with a last selected code. A payload header comprising a header identifying the packets as containing entitlement data and a plurality of contiguously concatenated N-byte conditional access codes (where N is an integer greater than 1) and a payload containing the entitlement data An apparatus in a packet signal receiver for processing a packet signal comprising the entitlement data contained in signal packets having a load, the apparatus comprising: Means for applying the packet signal; A transport processor for responsive to the packet signal, identifying signal packets containing entitlement data, and extracting entitlement data payloads from the identified packets; Memory means for storing the extracted entitlement data payloads; A conditional access filter arranged to examine payload header data of extracted entitlement data payloads for subscriber specific or subscriber group N-byte conditional access codes, wherein, in exclusive N-byte data groups, the plurality of Comparing the payload header data including adjacently coupled N-byte conditional access codes with the N-byte conditional access code stored in the receiver, one of the exclusive N-byte groups and the N-byte conditional access And a conditional access filter having a comparator for generating an enable signal to write the entitlement data to the memory means once a code is matched. The method of claim 3, wherein The conditional access filter, A register that stores an N-byte conditional access code, Means for including a comparator, The comparator, a) determining whether the first N-bytes of the entitlement data payload include a conditional access code that is all in one logical state, b) if the first N-bytes contain a code that is all in one logical state, compare the N-1 bytes of the subscriber specific conditional access code with the entitlement data payload of exclusive N-byte groups, If the N-1 bytes of the subscriber specific conditional access code match the N-1 bytes of any of the exclusive N-byte groups, apply the entitlement data to the entitlement data processor. Generate an enable signal, c) otherwise, compare the entitlement data payload in exclusive N-byte groups with the N-byte subscriber specific conditional access code contained in the register, and wherein the subscriber specific conditional access code is And if the match is with any one of the N-byte groups, apply the entitlement data to the entitlement data processor. The method of claim 4, wherein The conditional access filter detects whether a predetermined number of N-byte groups of the conditional access code in the entitlement data payload are in the same logical state and, if the same logical state, recalls the entitlement data payload. And a detector for applying to an entitlement data processor. The method of claim 4, wherein The conditional access filter detects whether a predetermined number of N-byte groups of the conditional access code in the entitlement data payload are all in a zero logical state and, if it is in a zero logical state, the entitlement data payload. And a detector for applying to the entitlement data processor. The method of claim 4, wherein The register storing an N-byte subscriber specific conditional access code comprises N one byte registers, The conditional access filter, A multiplexer having N input ports each coupled to the N one byte registers, And a counting circuit that adjusts the multiplexer to scan its input ports to sequentially provide data to the comparator from the N one byte registers.