KR100381379B1 - Semiconductor Device Manufactoring Method - Google Patents
Semiconductor Device Manufactoring Method Download PDFInfo
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- KR100381379B1 KR100381379B1 KR10-2001-0037797A KR20010037797A KR100381379B1 KR 100381379 B1 KR100381379 B1 KR 100381379B1 KR 20010037797 A KR20010037797 A KR 20010037797A KR 100381379 B1 KR100381379 B1 KR 100381379B1
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- Prior art keywords
- drain
- semiconductor device
- source
- film
- boron
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- -1 LDD ions Chemical class 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052796 boron Inorganic materials 0.000 abstract description 18
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- KPSZQYZCNSCYGG-UHFFFAOYSA-N [B].[B] Chemical compound [B].[B] KPSZQYZCNSCYGG-UHFFFAOYSA-N 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910008310 Si—Ge Inorganic materials 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 208000022010 Lhermitte-Duclos disease Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 description 1
- QVMHUALAQYRRBM-UHFFFAOYSA-N [P].[P] Chemical compound [P].[P] QVMHUALAQYRRBM-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
본 발명은 P-MOS 타입의 반도체 소자를 제조하는 경우에 이온 주입 공정에서 P형 도우핑 불순물로서 주입한 붕소(Boron)가 소오스와 드레인에서의 확산됨을 방지하도록 하는 반도체 소자 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device for preventing the diffusion of boron (boron) implanted as a P-type doping impurity in the ion implantation process in the manufacturing of a P-MOS type semiconductor device.
종래의 P-MOS 타입의 반도체 소자에서는 붕소가 소오스와 드레인의 좌,우 측면으로 확산하는 것은 방지할 수 있으나 소오스와 드레인의 하단부로의 확산은 방지하지 못한다는 문제점이 있었다.In the conventional P-MOS type semiconductor device, boron may be prevented from diffusing to the left and right sides of the source and drain, but may not be prevented from diffusing to the lower end of the source and drain.
본 발명은 P-MOS 타입의 반도체 소자를 제조하는 경우에 이온 주입 공정에서 P형 도우핑 불순물로서 주입한 붕소(Boron)가 소오스와 드레인에서 좌, 우 측면 뿐만 아니라 하단부로 확산되는 것을 방지함과 아울러 쇼트 채널 효과(Short Channel Effect)를 방지하기 위한 LDD(Lightly Doped Drain)에 대한 붕소의 측면 확산을 제어하므로, 전기적으로 양호한 특성을 갖는 반도체 소자를 제조하게 된다.According to the present invention, when a P-MOS type semiconductor device is manufactured, boron implanted as a P-type doping impurity in an ion implantation process is prevented from being diffused from the source and drain to the lower and left sides as well as the left and right sides. In addition, since lateral diffusion of boron to LDD (Lightly Doped Drain) to prevent short channel effects is controlled, a semiconductor device having excellent electrical properties can be manufactured.
Description
본 발명은 반도체 소자에 관한 것으로, 특히 P-MOS 타입의 반도체 소자를 제조하는 경우에 이온 주입 공정에서 P형 도우핑 불순물로서 주입한 붕소(Boron)가소오스와 드레인에서의 확산됨을 방지하도록 하는 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. In particular, when a P-MOS type semiconductor device is manufactured, a semiconductor which prevents boron implanted as a P-type doping impurity in an ion implantation process from diffusing in a source and a drain. It relates to a device manufacturing method.
일반적으로 P-MOS 타입의 반도체 소자를 제조하는 경우에 이온 주입 공정에서 붕소를 P형 불순물로 주입하고 있으며, 이 붕소는 반도체 소자의 소오스와 드레인에서 확산되어 반도체 소자의 전기적인 특성에 영향을 주고 있는데, 붕소는 펀치 드루우(Punch-through) 현상을 유발하고 있다.In general, in the case of manufacturing a P-MOS type semiconductor device, boron is implanted as a P-type impurity in an ion implantation process, and the boron diffuses from the source and drain of the semiconductor device to affect the electrical characteristics of the semiconductor device. Boron causes a punch-through phenomenon.
이와같은 문제점을 해결하기 위해 종래에는 P-MOS 타입의 반도체 소자를 제조하는 경우 인(Phosphorus) 등을 이온 주입함으로써 붕소의 확산을 방지하는 할로(Halo) 공정이 사용되고 있다. 이와 같은 할로 공정을 적용하면 붕소가 소오스와 드레인의 좌,우 측면으로 확산하는 것은 방지할 수 있으나 소오스와 드레인의 하단부로의 확산은 방지하지 못한다는 문제점이 있다.In order to solve such a problem, a halo process for preventing diffusion of boron by ion implantation of phosphorus (Phosphorus) or the like is conventionally used in manufacturing a P-MOS type semiconductor device. By applying such a halo process, it is possible to prevent boron from diffusing to the left and right sides of the source and drain, but there is a problem in that the diffusion of the source and drain to the lower end of the source and drain is not prevented.
또한, 반도체 소자의 소오스와 드레인에 대한 붕소 확산을 방지하기 위하여 소오스와 드레인 영역을 실리콘 오버 애칭한 후 산화막을 소오스와 드레인의 좌,우 양측면에 형성하고 SEG(Selective Epitexial Growing)를 사용하여 소오드와 드레인을 채우는 하는 공정을 사용하기도 하였는데, 이와 같은 공정을 적용하면 붕소가 소오스와 드레인의 좌,우 측면으로 확산하는 것은 방지할 수 있으나, 소오스와 드레인의 하단부로의 확산은 방지하지 못한다는 문제점이 있다.In addition, in order to prevent the diffusion of boron into the source and drain of the semiconductor device, the source and drain regions are silicon-over-etched, and an oxide film is formed on both left and right sides of the source and drain, and the SEG (Selective Epitexial Growing) is used. Although the process of filling the and drain is used, it is possible to prevent boron from diffusing to the left and right sides of the source and the drain, but this does not prevent the diffusion of the source and drain to the lower end of the source and the drain. There is this.
본 발명은 상술한 바와 같은 문제점을 해결하기 위하여 안출된 것으로, P-MOS 타입의 반도체 소자를 제조하는 경우에 이온 주입 공정에서 P형 도우핑 불순물로서 주입한 붕소(Boron)가 소오스와 드레인에서 좌, 우 측면 뿐만 아니라 하단부로 확산되는 것을 방지함과 아울러 쇼트 채널 효과(Short Channel Effect)를 방지하기 위한 LDD(Lightly Doped Drain)에 대한 붕소의 측면 확산을 제어함으로써 전기적으로 양호한 특성을 갖는 반도체 소자를 제조하도록 하는 반도체 소자 제조방법을 제공함에 목적이 있다.The present invention has been made to solve the problems described above, in the case of manufacturing a P-MOS type semiconductor device, boron implanted as a P-type doping impurity in an ion implantation process is left in the source and drain. In addition, the semiconductor device having excellent electrical characteristics can be obtained by controlling lateral diffusion of boron to LDD (Lightly Doped Drain) to prevent short channel effect from being spread to the lower side as well as the right side. An object of the present invention is to provide a method for manufacturing a semiconductor device.
도 1 내지 도 12는 본 발명에 따른 반도체 소자 제조 공정을 도시한 도.1 to 12 illustrate a semiconductor device manufacturing process according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1: 실리콘 기판 2: 산화막1: silicon substrate 2: oxide film
3: 다결정 실리콘막 4: 버퍼 산화막3: polycrystalline silicon film 4: buffer oxide film
5: 희생 다결정 실리콘막 6: 스페이서5: sacrificial polycrystalline silicon film 6: spacer
7a, 7b: 호올 8 : SiXGe1-X막7a, 7b: Hool 8: Si X Ge 1-X film
9: 산화막 10: 도핑된 Ge9: oxide film 10: doped Ge
11: 에피텍셜 성장된 실리콘11: epitaxially grown silicon
이상과 같은 목적을 달성하기 위한 본 발명의 특징은, 반도체 소자 제조 방법에 있어서, 실리콘 기판 상에 게이트를 형성하고 상기 게이트 상단에 버퍼 산화막과 희생 다결정 실리콘막을 형성하는 공정과; 상기 희생 다결정 실리콘막과 상기 실리콘 기판을 동시에 오버 에칭하여 게이트의 옆에 소오스와 드레인을 형성하기 위한 호올을 형성하는 공정과; 상기 실리콘 기판 상의 호올에 SiXGe1-X(x는 조성비)을 에피텍셜 성장시켜 SiXGe1-X막을 형성하는 공정과; 상기 SiXGe1-X막을 산화시켜서 제1 산화막을 형성하고 Ge를 도핑하는 공정과; 상기 버퍼 산화막과 제1 산화막을 이방성 에칭하되 상기 호올의 하단부 및 좌, 우측면의 LDD 채널 깊이까지 에칭하는 공정과; 상기 호올의 하단에 노출된 실리콘 기판과 LDD 영역 부분으로부터 SEG방식으로 실리콘을 에피텍셜 성장시켜 소오스와 드레인을 형성하는 공정과; 상기 소오스와 드레인에 이온을 주입한후 열처리를 시행하는 공정을 포함하는데 있다.A feature of the present invention for achieving the above object is a semiconductor device manufacturing method comprising: forming a gate on a silicon substrate and forming a buffer oxide film and a sacrificial polycrystalline silicon film on the gate; Simultaneously over-etching the sacrificial polycrystalline silicon film and the silicon substrate to form a hole for forming a source and a drain next to the gate; Epitaxially growing Si X Ge 1-X (x is a composition ratio) on the hool on the silicon substrate to form a Si X Ge 1-X film; Oxidizing the Si X Ge 1-X film to form a first oxide film and doping Ge; Anisotropically etching the buffer oxide layer and the first oxide layer, but etching to the depths of the LDD channels of the lower end and the left and right sides of the hole; Forming a source and a drain by epitaxially growing silicon from the silicon substrate and the LDD region exposed at the bottom of the hole by SEG; And implanting ions into the source and drain and then performing a heat treatment.
이하 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명에서는 P-MOS 타입의 반도체 소자 제조시 P+ 소오스/드레인을 형성하기 전에 Si-Ge 조성의 SEG에 의한 SiXGe1-X막층을 형성하여 산화와 동시에 Ge를 소오스와 드레인 영역에 확산시켜 LDD, 소오스 및 드레인의 좌,우 측면 및 하단부에서의 붕소 확산을 방지한다.In the present invention, prior to forming a P + source / drain in forming a P-MOS type semiconductor device, a Si X Ge 1-X film layer formed by SEG having a Si-Ge composition is formed to diffuse Ge into a source and a drain region simultaneously with oxidation. Prevents boron diffusion from the left, right and bottom sides of LDDs, sources and drains.
본 발명에 따른 반도체 소자의 제조 과정은 다음과 같이 이루어 진다.The manufacturing process of the semiconductor device according to the present invention is made as follows.
먼저, 도1에 도시된 바와 같이 실리콘 기판(1)의 위에 게이트의 형성을 위한 산화막(2)을 형성한다. 그리고, 도2에 도시된 바와 같이 산화막(2)의 위에 게이트의 형성을 위한 다결정 실리콘막(3)을 형성하고, 도3에 도시된 바와 같이 다결정 실리콘막(3)의 위에 버퍼 산화막(4)을 형성한다. 그후에, 도4에 도시된 바와 같이 버퍼 산화막(4)의 위에 희생 다결정 실리콘막(5)을 형성하고, 도5에 도시된 바와 같이 실리콘 질화물로 이루어진 스페이서(6)를 형성한다.First, as shown in FIG. 1, an oxide film 2 for forming a gate is formed on the silicon substrate 1. 2, a polycrystalline silicon film 3 for forming a gate is formed on the oxide film 2, and a buffer oxide film 4 is formed on the polycrystalline silicon film 3, as shown in FIG. To form. Thereafter, as shown in Fig. 4, a sacrificial polycrystalline silicon film 5 is formed on the buffer oxide film 4, and as shown in Fig. 5, a spacer 6 made of silicon nitride is formed.
또한, 게이트 패턴의 상단에 있는 희생 다결정 실리콘막(5)과 실리콘 기판(1)을 동시에 오버 에칭하되, 도6에 도시된 바와 같이 실리콘 기판(1)에 대해서는 원하는 깊이로 정하여 에칭함으로써 호올(7a, 7b)을 형성하는데, 게이트 다결정 실리콘막(3)은 호올(7a, 7b)에 상응하는 두께로 형성하여야 한다.Further, the sacrificial polycrystalline silicon film 5 and the silicon substrate 1 at the top of the gate pattern are simultaneously overetched, but as shown in FIG. , 7b), and the gate polycrystalline silicon film 3 should be formed to a thickness corresponding to the homools 7a and 7b.
그리고, 도7에 도시된 바와 같이 실리콘 기판(1) 상에 SiXGe1-X(여기서, x는 조성비)을 에피텍셜 성장시켜 SiXGe1-X막(8)을 형성하고, 해당 SiXGe1-X막(8)을 산화시켜서 도8에 도시된 바와 같이 산화막(9)을 형성한 후, 도9에 도시된 바와 같이Ge(10; 게르마늄)를 도핑(doping)하되 해당 Ge(10)는 소오스용 호올(7a)과 드레인용 호올(7b)의 좌, 우측면 및 하단부와 LDD영역 까지 도핑된다.As shown in FIG. 7, Si X Ge 1-X (where x is the composition ratio) is epitaxially grown on the silicon substrate 1 to form a Si X Ge 1-X film 8, and the Si After oxidizing the X Ge 1-X film 8 to form an oxide film 9 as shown in FIG. 8, doping Ge (10; germanium) as shown in FIG. 9 is performed. 10) is doped to the left, right and bottom surfaces and the LDD region of the source foil 7a and the drain foil 7b.
한편, 버퍼 산화막(4)과 실리콘 기판(1)의 산화막(9)을 이방성 에칭하여 도10에 도시된 바와 같이 호올(7a, 7b)의 하단부 및 좌, 우측면의 LDD 채널 깊이까지 에칭을 실시한다. 그리고, 도11에 도시된 바와 같이 소오스가 형성될 호올(7a)과 드레인이 형성될 호올(7b)의 하단에 노출된 실리콘 기판(1)과 LDD 영역 부분으로부터 SEG방식으로 실리콘(11)을 에피텍셜 성장시켜 소오스와 드레인을 형성한다.On the other hand, the buffer oxide film 4 and the oxide film 9 of the silicon substrate 1 are anisotropically etched and etched to LDD channel depths of the lower ends and left and right sides of the holes 7a and 7b as shown in FIG. . As shown in Fig. 11, the silicon 11 is epitaxially etched from the silicon substrate 1 and the LDD region portion exposed at the lower end of the hool 7a where the source is to be formed and the hool 7b where the drain is to be formed. Tactical growth forms a source and a drain.
그리고, 도12에 도시된 바와 같이 소오스와 드레인에 P+ 이온을 주입하되 P형 도우핑 불순물로서 붕소를 주입한후 열처리를 시행한다. 이때, 스페이서(6)의 근처 부근에는 실리콘이 두꺼우므로 소오스/드레인에 대한 이온 주입후 LDD 영역 부분은 농도가 적게 되며, 별도로 LDD 이온 주입은 하지 않는다.As shown in FIG. 12, P + ions are implanted into the source and drain, but boron is implanted as a P-type doping impurity, followed by heat treatment. At this time, since the silicon is thick in the vicinity of the spacer 6, the concentration of the LDD region after ion implantation into the source / drain is low, and LDD ion implantation is not performed separately.
이상과 같이, 본 발명에서는 P-MOS 타입의 반도체 소자 제조시 P+ 소오스/드레인을 형성하기 전에 Si-Ge(실리콘-게르마늄) 조성의 SEG에 의한 SiXGe1-X막층을 형성하여 산화와 동시에 Ge를 소오스와 드레인 영역에 확산시켜 주는데, Ge는 붕소의 실리콘 침입을 억제하여 주므로 LDD, 소오스 및 드레인의 좌,우 측면 및 하단부에서의 붕소 확산을 효율적으로 방지한다.As described above, in the present invention, the Si X Ge 1-X film layer formed by the SEG of Si-Ge (silicon-germanium) composition is formed before the formation of the P + source / drain when the P-MOS semiconductor device is manufactured. Ge is diffused into the source and drain regions, and Ge suppresses boron silicon intrusion, thereby effectively preventing boron diffusion from the left, right, and bottom portions of the LDD, the source and the drain.
이상 설명한 바와 같이, 본 발명은 P-MOS 타입의 반도체 소자를 제조하는 경우에 이온 주입 공정에서 P형 도우핑 불순물로서 주입한 붕소(Boron)가 소오스와 드레인에서 좌, 우 측면 뿐만 아니라 하단부로 확산되는 것을 방지함과 아울러 쇼트 채널 효과(Short Channel Effect)를 방지하기 위한 LDD(Lightly Doped Drain)에 대한 붕소의 측면 확산을 제어하므로, 전기적으로 양호한 특성을 갖는 반도체 소자를 제조하게 된다.As described above, in the case of manufacturing a P-MOS type semiconductor device, boron implanted as a P-type doping impurity in an ion implantation process diffuses from the source and drain to the lower and right sides as well as the left and right sides. In addition to controlling the side diffusion of boron to LDD (Lightly Doped Drain) to prevent the short channel effect (Short Channel Effect), thereby producing a semiconductor device having an electrically good characteristics.
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