KR100380037B1 - Method for manufacturing semiconductor sensor - Google Patents
Method for manufacturing semiconductor sensor Download PDFInfo
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- KR100380037B1 KR100380037B1 KR1019980015396A KR19980015396A KR100380037B1 KR 100380037 B1 KR100380037 B1 KR 100380037B1 KR 1019980015396 A KR1019980015396 A KR 1019980015396A KR 19980015396 A KR19980015396 A KR 19980015396A KR 100380037 B1 KR100380037 B1 KR 100380037B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 41
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 229910052804 chromium Inorganic materials 0.000 claims description 18
- 239000011651 chromium Substances 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 51
- 239000000758 substrate Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000004809 Teflon Substances 0.000 description 3
- 229920006362 Teflon® Polymers 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006355 external stress Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Pressure Sensors (AREA)
- Measuring Fluid Pressure (AREA)
Abstract
Description
본 발명은 반도체 센서의 제조방법에 관한 것으로, 상세하게는 반도체 센서를 제조시 구조물을 형성하기 위하여 에칭을 할 때 에칭되는 반대면에 크롬을 증착시키고 증착된 크롬을 열처리하여서 구조물을 비등방성 에칭용액에 의하여 에칭할 때 에칭되는 반대면을 보호할 수 있는 반도체 센서의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor sensor, and more particularly, to anisotropic etching solution by depositing chromium on the opposite side to be etched when etching to form a structure in the manufacturing of the semiconductor sensor and heat-treating the deposited chromium The present invention relates to a method for manufacturing a semiconductor sensor capable of protecting the opposite surface to be etched when etching by.
반도체 센서에는 여러 가지 종류가 있는데 가속도 센서, 각속도센서, 압력센서등이 있다. 먼저 반도체 압력센서는 엔진으로 흡입되는 공기량을 다기관의 압력과 엔진회전수로 추정 산출하는 스피드 덴시티 방식의 연료 분사장치용 흡기관 내 압력센서나 터보 과급기압 센서 등에 사용된다There are many types of semiconductor sensors, including acceleration sensors, angular velocity sensors, and pressure sensors. First, the semiconductor pressure sensor is used in the pressure sensor or turbocharger pressure sensor in the intake pipe for a speed density fuel injector which estimates the amount of air sucked into the engine by the pressure of the manifold and the engine speed.
반도체 압력센서는 칩을 받침대에 접착 고정하고 전체를 케이스로 감싸서 내부를 진공으로 만들어 포트를 흡기관에 연결되어 있으며 흡기관 내의 압력에 의하여 다이아프램이 응력을 받아서 압력센서의 압저항체의 저항 값이 변하게 된다.The semiconductor pressure sensor is adhesively fixed to the base of the chip, the whole is wrapped in a case, and the inside is vacuumed, so that the port is connected to the intake pipe. Will change.
가속도 센서는 관성센서의 일종으로서 연구, 군사용 등의 특수용도 시장과 더불어 최근에는 자동차 및 가전 제품의 성능향상이나 신 기능 추가의 요구에 따라서 그 적용 분야가 확대되고 있다.Accelerometer is a kind of inertial sensor, and its application field is expanding according to the demand for the improvement of performance of automobiles and home appliances and the addition of new functions in addition to the special use market such as research and military use.
근래에 들어서는 직접회로 기술을 기반으로 하여 물리량 감지를 위한 미세 구조물과 감지회로의 보정, 증폭처리를 위한 전자회로를 하나의 칩으로 집적시킨 가속도 센서가 개발되고 있다.In recent years, based on integrated circuit technology, acceleration sensors have been developed that integrate microstructures for physical quantity sensing, electronic circuits for correction and amplification of sensing circuits into one chip.
도 1은 종래의 반도체 센서의 공정 흐름도이다.1 is a process flowchart of a conventional semiconductor sensor.
전술한 종래의 반도체 센서들은 유사한 제조공정에 의하여 제조되는데 그 중에서 압력센서의 제조공정은 다음과 같다.The above-mentioned conventional semiconductor sensors are manufactured by a similar manufacturing process, among which the manufacturing process of the pressure sensor is as follows.
일단 기판 웨이퍼가 될 실리콘웨이퍼를 준비한다.First, prepare a silicon wafer to be a substrate wafer.
그리고 준비된 실리콘웨이퍼에 산화막(SiO2)을 형성시킨다.An oxide film (SiO 2 ) is formed on the prepared silicon wafer.
실리콘 산화막이 형성된 실리콘웨이퍼에 또 다른 실리콘웨이퍼를 접합시키는데 그 웨이퍼는 압력센서의 다이아프램 부분이 된다. 그것은 곧 실리콘 직접접합 웨이퍼(Silicon direct bonding wafer, SDB wafer)가 된다(S1).Another silicon wafer is bonded to the silicon wafer on which the silicon oxide film is formed, which becomes the diaphragm portion of the pressure sensor. It soon becomes a silicon direct bonding wafer (SDB wafer) (S1).
실리콘 직접접합 웨이퍼가 완성되고 나면 그 위에 산화막을 성장시킨다. 산화막을 성장시키고 나면 사진공정을 통하여 압저항 패턴의 위치를 결정하고, 결정된 압저항 패턴의 위치에 산화막을 에칭한다.After the silicon direct-junction wafer is completed, an oxide film is grown thereon. After the oxide film is grown, the position of the piezoresistive pattern is determined through a photographic process, and the oxide film is etched at the determined position of the piezoresistive pattern.
산화막을 에칭하고 나면 압저항 패턴이 형성되는데, 압저항 패턴이 형성되고 나면 압저항 패턴이 있는 곳의 실리콘웨이퍼에 이온주입을 하여 압저항체를 형성한다(S2). 압저항체는 응력변형이 가해지면 저항값이 변하는 성질을 가지고 있는데 이것을 반도체 피에조 효과라고 한다.After the oxide film is etched, a piezoresistive pattern is formed. After the piezoresistive pattern is formed, an piezo resistor is formed by ion implantation into a silicon wafer where the piezoresistive pattern is present (S2). The piezoresistor has a property that the resistance value changes when stress deformation is applied, which is called semiconductor piezo effect.
압저항체가 형성된 다음에는 산화막을 에칭하여 제거한다.After the piezoresistor is formed, the oxide film is etched and removed.
그런 다음에는 실리콘 직접접합 웨이퍼의 기판 웨이퍼를 에칭하여 다이아프램을 형성하기 위하여 기판 웨이퍼면에 실리콘 산화막을 형성시킨다. 또한 이때 에칭을 하지 않는 상부웨이퍼를 보호하기 위하여 왁스를 코팅하거나 혹은 테프론지그(Tefron Jig)를 사용한다(S3).Then, a silicon oxide film is formed on the surface of the substrate wafer to etch the substrate wafer of the silicon direct bonded wafer to form a diaphragm. In addition, at this time, in order to protect the upper wafer which is not etched, wax is coated or Tefron Jig (Tefron Jig) is used (S3).
그런 다음 다이아프램을 형성하기 위하여 에칭할 면에 실리콘 산화막을 형성시킨다. 기판 웨이퍼면에 실리콘 산화막이 형성되고 나면 실리콘 산화막을 패터닝한다(S4). 패터닝후에는 비등방성 에칭을 한다(S5).Then, a silicon oxide film is formed on the surface to be etched to form the diaphragm. After the silicon oxide film is formed on the substrate wafer surface, the silicon oxide film is patterned (S4). After patterning, anisotropic etching is performed (S5).
기판 웨이퍼의 에칭과정이 종료를 하면 기판 웨이퍼에 남아있는 잔류 산화막을 제거한다(S6). 그리하여 다이아프램이 형성된다.When the etching process of the substrate wafer is finished, the residual oxide film remaining on the substrate wafer is removed (S6). Thus a diaphragm is formed.
외부에서 응력이 가해지면 다이아프램이 힘을 받게된다. 다이아프램은 외부 응력에 의하여 힘을 받게되면 힘이 가해지는 반대방향으로 휘게된다.When stress is applied from the outside, the diaphragm is forced. The diaphragm bends in the opposite direction to which force is applied when it is forced by an external stress.
다이아프램의 끝 부분에는 압저항체가 마련되어 있는데, 압저항체는 외부 응력에 의한 다이아프램의 휨에 따라서 저항값의 변화를 일으킨다.A piezoresistor is provided at the end of the diaphragm, which causes a change in resistance value according to the bending of the diaphragm due to external stress.
다이아프램을 형성하기 위하여 기판웨이퍼를 에칭할 때 상부웨이퍼를 보호하기 위하여 테프론지그를 이용하는데, 테프론지그의 경우에는 테프론재질 자체가 에칭용액의 온도를 흡수하여 열팽창을 하기 때문에 그에 따른 응력으로 인하여 실리콘웨이퍼에 균열이 발생할 수 있다.Teflon jig is used to protect the upper wafer when etching the substrate wafer to form the diaphragm. In the case of the teflon jig, because Teflon material itself absorbs the temperature of the etching solution and thermally expands, Cracks may occur in the wafer.
그리고 또한 상부 웨이퍼를 보호하기 위하여 상부웨이퍼에 왁스를 코팅하는 경우도 있는데, 에칭을 하게 되면 왁스코팅이 오래 견디지 못하여 에칭공정 도중에 왁스를 재차 코팅해주어야 하여 공정이 복잡하고 번거로운 문제점이 있다.In addition, there is a case in which wax is coated on the upper wafer to protect the upper wafer. If the etching is performed, the wax coating does not last long, so the wax must be coated again during the etching process, which causes a complicated and cumbersome problem.
본 발명은 전술한 문제를 해결하기 위하여, 반도체 센서를 제조시 구조물을 형성하기 위하여 에칭을 할 때 에칭되는 반대면에 크롬을 증착시키고 증착된 크롬을 열처리하여서 구조물을 비등방성 에칭용액에 의하여 에칭할 때 에칭되는 반대면을 보호할 수 있는 반도체 센서의 제조방법을 제공하는데 있다.In order to solve the above-described problem, the present invention provides a method for etching a structure by anisotropic etching solution by depositing chromium on the opposite side to be etched during etching to form a structure in manufacturing a semiconductor sensor and heat-treating the deposited chromium. It is to provide a method of manufacturing a semiconductor sensor that can protect the opposite surface when etched.
도 1은 종래의 반도체 센서의 공정 흐름도이다.1 is a process flowchart of a conventional semiconductor sensor.
도 2는 본 발명에 따른 반도체 센서의 공정 흐름도이다.2 is a process flow diagram of a semiconductor sensor according to the present invention.
도 3은 본 발명에 따른 반도체 센서의 공정도이다.3 is a process diagram of the semiconductor sensor according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10:실리콘직접접합웨이퍼 11:기판웨이퍼10: Silicon Direct Wafer 11: Substrate Wafer
12:산화막 13:상부웨이퍼12: oxide film 13: upper wafer
20:압저항체 30:크롬20: piezoresistor 30: chrome
상기 목적을 달성하기 위한 본 발명은, 실리콘직접접합웨이퍼의 상부웨이퍼에 압저항을 형성하는 압저항형성단계와, 압저항형성단계후 잔류산화막을 에칭하여 제거하는 산화막에칭단계와, 실리콘웨이퍼를 에칭하여 구조물을 형성하는 구조물형성단계를 포함하는 반도체 센서의 제조방법에 있어서, 구조물형성단계를 실시하기 전에 에칭을 하고자 하는 면의 타측면에 크롬을 증착시키는 크롬증착단계, 크롬증착단계 후 증착된 크롬을 열처리하는 열처리단계를 포함하는 것을 특징으로 하는방법이다.The present invention for achieving the above object, the piezoresistance forming step of forming a piezoresistance on the upper wafer of the silicon direct bonded wafer, the oxide film etching step of etching to remove the residual oxide film after the piezoresistance forming step, and etching the silicon wafer In the method of manufacturing a semiconductor sensor comprising a structure forming step of forming a structure, the chromium deposition step of depositing chromium on the other side of the surface to be etched before performing the structure forming step, the chromium deposited after the chromium deposition step It characterized in that it comprises a heat treatment step of heat treatment.
이하에서는 첨부한 도면을 참조하여 양호한 실시 예를 상세하게 설명하겠다.Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체 센서의 공정 흐름도이다.2 is a process flow diagram of a semiconductor sensor according to the present invention.
도 3은 본 발명에 따른 반도체 센서의 공정도이다.3 is a process diagram of the semiconductor sensor according to the present invention.
일단 기판 웨이퍼(11)가 될 실리콘웨이퍼를 준비한다(도3 a).First, a silicon wafer to be the substrate wafer 11 is prepared (FIG. 3A).
그리고 준비된 실리콘웨이퍼에 산화막(SiO2)(12)을 형성시킨다(도3 b).Then, an oxide film (SiO 2 ) 12 is formed on the prepared silicon wafer (Fig. 3b).
실리콘 산화막(12)이 형성된 실리콘웨이퍼에 또 다른 실리콘 웨이퍼인 상부 웨이퍼(13)를 접합시키는데 그 상부 웨이퍼(13)는 후에 다이아프램 부분이 된다. 그리하여 실리콘 직접접합 웨이퍼(Silicon direct bonding wafer, SDB wafer)(10)가 완성된다(도3 c)(S11).The upper wafer 13, which is another silicon wafer, is bonded to the silicon wafer on which the silicon oxide film 12 is formed. The upper wafer 13 later becomes a diaphragm portion. Thus, a silicon direct bonding wafer (SDB wafer) 10 is completed (Fig. 3c) (S11).
실리콘 직접접합 웨이퍼(10)는 비록 두 장의 웨이퍼가 겹쳐져 있는 형태이지만 서로 다른 물질이 접합되었을 때와 같은 문제점이 없다. 즉, 열 팽창 등에 의한 부정합이나 결합제에 의한 약화로 인한 기계적, 전기적 불안정 등과 같은 현상이 없다.Although the silicon direct bonded wafer 10 has two wafers stacked on top of each other, there is no problem such as when different materials are bonded to each other. That is, there is no phenomenon such as mechanical or electrical instability due to mismatch due to thermal expansion or weakening by the binder.
실리콘 직접접합 웨이퍼(10)가 완성되고 나면 그 위에 산화막(14)을 성장시킨다(도3 d)(S12). 산화막(14)을 성장시키고 나면 사진공정을 통하여 압저항 패턴의 위치를 결정하고(S13), 결정된 압저항 패턴의 위치(가)의 산화막을 에칭한다(도3 e)(S14).After the silicon direct bonding wafer 10 is completed, an oxide film 14 is grown thereon (Fig. 3D) (S12). After the oxide film 14 is grown, the position of the piezoresistive pattern is determined through a photographic process (S13), and the oxide film at the position (a) of the determined piezoresistive pattern is etched (FIG. 3E) (S14).
산화막을 에칭하고 나면 압저항 패턴이 형성되는데, 압저항 패턴이 형성되고나면 압저항 패턴이 있는 곳의 실리콘웨이퍼(13)에 이온주입을 하여 압저항체(20)를 형성한다(도3 f)(S15). 압저항체(20)는 응력변형이 가해지면 저항값이 변하는 성질을 가지고 있는데 이것을 반도체 피에조 효과라고 한다.After the oxide film is etched, a piezoresistive pattern is formed. After the piezoresistive pattern is formed, ions are implanted into the silicon wafer 13 where the piezoresistive pattern is present to form the piezoresistor 20 (Fig. 3F) ( S15). The piezoresistor 20 has a property that the resistance value changes when stress deformation is applied, which is called a semiconductor piezo effect.
압저항체(20)가 형성된 다음에는 산화막을 에칭하여 제거한다(도3 g)(S16).After the piezoresistor 20 is formed, the oxide film is etched and removed (FIG. 3g) (S16).
산화막이 제거되고 나면 실리콘 직접접합 웨이퍼(10)의 기판 웨이퍼(11)를 에칭하여 다이아프램을 형성해야 되는데 에칭하기 이전에 에칭할 면의 반대면인 상부웨이퍼(13)에 크롬(30)을 증착시킨다(도3 h)(S17). 이때 크롬(20)은 약 2000 ~ 3000Å정도 증착한다. 크롬(20)을 증착시키고 나면 약 400 ~ 450℃의 온도에서 약 30분간 열처리를 한다(S18).After the oxide film is removed, the substrate wafer 11 of the silicon direct-junction wafer 10 must be etched to form a diaphragm. The chromium 30 is deposited on the upper wafer 13 opposite to the surface to be etched before etching. (Fig. 3h) (S17). At this time, the chromium 20 is deposited about 2000 ~ 3000Å. After depositing the chromium 20 is heat-treated for about 30 minutes at a temperature of about 400 ~ 450 ℃ (S18).
그런 다음 다이아프램을 형성하기 위하여 에칭할 면에 실리콘 산화막(40)을 형성시킨다(도3 i)(S19). 기판 웨이퍼(11)면에 실리콘 산화막(40)이 형성되고 나면 실리콘 산화막(40)을 패터닝한다(도3 j)(S20). 패터닝후에는 비등방성 에칭을 한다(도3 k)(S21).Then, a silicon oxide film 40 is formed on the surface to be etched to form the diaphragm (Fig. 3i) (S19). After the silicon oxide film 40 is formed on the surface of the substrate wafer 11, the silicon oxide film 40 is patterned (FIG. 3J) (S20). After patterning, anisotropic etching is performed (FIG. 3K) (S21).
에칭을 할 때에는 실리콘 비등방성 에칭용액인 수산화칼륨용액에서 에칭을 한다. 비등방성 에칭용액에 의한 에칭에서는 실리콘의 결정면에 따른 에칭률이 크게 다르며 [100]방향이 [111]방향 보다 에칭률이 최고 400배 이상이고, [110]방향보다는 200배 크다. 즉, 실리콘웨이퍼의 두께방향으로 빨리 에칭된다. 또한 실리콘(Si)과 실리콘 산화막(SiO2)의 에칭률은 거의 400:1 정도이다.When etching, etching is performed in a potassium hydroxide solution, which is a silicon anisotropic etching solution. In the etching by an anisotropic etching solution, the etching rate according to the crystal surface of the silicon is significantly different, and the etching rate of the [100] direction is at least 400 times higher than that of the [111] direction and 200 times larger than the [110] direction. That is, it is quickly etched in the thickness direction of the silicon wafer. In addition, the etching rate of silicon (Si) and silicon oxide film (SiO 2 ) is about 400: 1.
기판 웨이퍼(11)의 에칭과정이 종료를 하면 기판 웨이퍼의 에칭후 남아있는잔류 산화막(41)을 제거한다(도3 l)(S22). 그리하여 다이아프램(라)이 형성된다(도2b h).When the etching process of the substrate wafer 11 is completed, the residual oxide film 41 remaining after the etching of the substrate wafer is removed (FIG. 3L) (S22). Thus, a diaphragm la is formed (Fig. 2b h).
그리고 나서 상부웨이퍼(13)에 증착시켰던 크롬(30)을 에칭하여 제거한다(도3 m)(S22).Then, the chromium 30 deposited on the upper wafer 13 is removed by etching (Fig. 3 m) (S22).
그리고 나서 웨이퍼를 칩으로 분리한다(S23). 웨이퍼를 칩으로 분리하고 나면 패키지를 하여 제품을 완성한다(S24).Then, the wafer is separated into chips (S23). After the wafer is separated into chips, the package is completed (S24).
본 발명에 따른 반도체 센서의 제조방법에 의하여 반도체 센서를 제조시, 압저항체를 형성하고 나서 실리콘웨이퍼를 에칭하여 구조물을 형성할 때 구조물을 형성하기 위하여 에칭을 하기전에 에칭하고자 하는 면의 타측면에 크롬을 증착시키고 증착된 크롬을 소정온도에서 열처리하여 구조물을 형성하기 위하여 에칭을 할 때 그 에칭에 의하여 에칭되는 타측면이 손상되는 것을 막을 수 있다.When manufacturing a semiconductor sensor by the method of manufacturing a semiconductor sensor according to the present invention, when forming a structure by etching the silicon wafer after forming a piezoresistor on the other side of the surface to be etched before etching to form the structure When the chromium is deposited and etched to form a structure by heat-treating the deposited chromium at a predetermined temperature, it is possible to prevent the other side etched by the etching from being damaged.
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