KR100379334B1 - Clock generating circuit - Google Patents

Clock generating circuit Download PDF

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KR100379334B1
KR100379334B1 KR10-2000-0054189A KR20000054189A KR100379334B1 KR 100379334 B1 KR100379334 B1 KR 100379334B1 KR 20000054189 A KR20000054189 A KR 20000054189A KR 100379334 B1 KR100379334 B1 KR 100379334B1
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clock
output signal
clock output
amplifier
output signals
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KR10-2000-0054189A
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KR20020021469A (en
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오명규
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Dram (AREA)

Abstract

본 발명은 클럭 발생회로에 관한 것으로, 종래 클럭 발생회로는 위상이 완전히 반대인 두 클럭출력신호를 생성하여 두 클럭출력신호의 중복구간이 없어야 하나, 이를 위해서는 두 클럭출력신호의 부하 커패시턴스가 다른 경우 항상 일정한 비중복구간을 유지할 수 없어 그 신뢰성이 저하되는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 발진부에서 발진된 특정 주파수의 신호를 증폭하는 증폭부와; 상기 증폭부의 출력신호와 지연반전된 제2클럭출력신호를 논리조합하여 제1클럭출력신호를 생성하는 제1클럭발생부와; 반전된 증폭부의 출력신호와 상기 제1클럭발생부의 제1클럭출력신호를 논리조합하여 상기 제2클럭출력신호를 생성하는 제2클럭발생부와; 상기 제1 및 제2클럭출력신호를 인가받아 그 클럭출력신호의 중복구간을 검출하여 부하커패시턴스 값을 예측하고, 그 부하 커패시턴스값을 보상하여 상기 중복구간을 비중복구간으로 복원하는 비중복보정부로 구성하여 두 클럭출력신호의 로딩 커패시턴스를 검출하여 그 커패시턴스의 차를 보상함으로써, 주파수가 동일한 두 클럭출력신호가 위상이 정확하게 출력될 수 있도록 하여, 그 동작을 신뢰성을 향상시키는 효과가 있다.The present invention relates to a clock generation circuit, and a conventional clock generation circuit generates two clock output signals having completely opposite phases, so that there is no overlapping interval between the two clock output signals. To this end, the load capacitance of the two clock output signals is different. There was a problem that the reliability cannot be maintained at all times because it is not possible to maintain a constant non-overlap period. In view of the above problems, the present invention includes an amplifier for amplifying a signal of a specific frequency oscillated by the oscillator; A first clock generator for generating a first clock output signal by logically combining the output signal of the amplifier and the delayed second clock output signal; A second clock generator configured to logically combine the output signal of the inverted amplifier and the first clock output signal of the first clock generator to generate the second clock output signal; The non-overlapping section which receives the first and second clock output signals, detects the overlapping section of the clock output signal, predicts the load capacitance value, compensates the load capacitance value, and restores the overlapping section to the non-overlapping section. By detecting the loading capacitance of the two clock output signals and compensating the difference of the capacitances, the two clock output signals having the same frequency can be outputted correctly in phase, thereby improving the reliability of the operation.

Description

클럭 발생회로{CLOCK GENERATING CIRCUIT}Clock Generation Circuit {CLOCK GENERATING CIRCUIT}

본 발명은 클럭 발생회로에 관한 것으로, 특히 두 클럭신호의 부하 커패시턴스를 일정하게 하여 두 클럭신호가 중복되지 않는 구간이 항상 일정하도록 하는 클럭 발생회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly, to a clock generation circuit in which a load capacitance of two clock signals is constant so that a section in which two clock signals do not overlap is always constant.

도1은 종래 클럭 발생회로도로서, 이에 도시한 바와 같이 특정한 주파수의 신호를 발진하는 발진부(1)와; 상기 발진부(1)의 출력신호를 증폭하는 증폭부(2)와; 상기 증폭부(2)의 출력신호와 지연반전된 클럭출력신호(CLK2)를 논리조합하여 클럭출력신호(CLK1)를 생성하는 제1클럭발생부(3)와; 반전된 증폭부(2)의 출력신호와 상기 제1클럭발생부(3)의 클럭출력신호(CLK2)를 논리조합하여 상기 클럭출력신호(CLK2)를 생성하는 제2클럭발생부(4)로 구성된다.Fig. 1 is a conventional clock generation circuit diagram, and as shown therein, an oscillator 1 for oscillating a signal of a specific frequency; An amplifier 2 for amplifying the output signal of the oscillator 1; A first clock generator (3) for generating a clock output signal (CLK1) by logically combining the output signal of the amplifier (2) and the delayed inverted clock output signal (CLK2); The second clock generator 4 generates the clock output signal CLK2 by logically combining the inverted output signal of the amplifier 2 and the clock output signal CLK2 of the first clock generator 3. It is composed.

상기 제1클럭발생부(3)는 상기 증폭부(2)의 출력신호를 일측입력단에 인가받고, 타측입력단에 직렬접속된 인버터(INV1~INV3)를 통해 반전지연된 클럭출력신호(CLK2)를 인가받아 앤드조합하여 클럭출력신호(CLK1)를 출력하는 앤드게이트(AND1)로 구성된다.The first clock generator 3 receives the output signal of the amplifier 2 to one input terminal and applies the clock output signal CLK2 that is inverted through the inverters INV1 to INV3 connected in series with the other input terminal. And an AND gate AND1 for outputting the clock output signal CLK1 by AND combining.

상기 제2클럭발생부(4)는 인버터(INV4)를 통해 반전된 상기 증폭부(2)의 출력신호를 일측입력단에 인가받고, 직렬접속된 인버터(INV5~INV7)를 통해 반전지연된 상기 클럭출력신호(CLK1)를 인가받아 앤드조합하여 클럭출력신호(CLK2)를 출력하는 앤드게이트(AND2)로 구성된다.The second clock generator 4 receives the output signal of the amplifier 2 inverted through the inverter INV4 to one input terminal and the clock output inverted through the inverters INV5 to INV7 connected in series. The AND gate AND2 is configured to receive the signal CLK1 and output the clock output signal CLK2 through an AND combination.

이하, 상기와 같이 구성된 종래 클럭 발생회로의 동작을 설명한다.The operation of the conventional clock generation circuit constructed as described above will be described below.

먼저, 발진부(1)에 구비된 오실레이터(OS)에서 발진을 개시하면 이는 그 오실레이터(OS)의 양측단과 접지사이에 각각 접속된 커패시터(C1,C2)에 의해 유지되어 출력된다.First, when oscillation is started in the oscillator OS provided in the oscillator 1, it is held and output by the capacitors C1 and C2 respectively connected between both ends of the oscillator OS and the ground.

그 다음, 상기 발진부(1)의 출력신호를 인가받은 증폭부(2)는 그 발진부(1)의 출력주파수에 따르는 소정전압 레벨의 클럭신호를 출력한다.Next, the amplifying unit 2 receiving the output signal of the oscillating unit 1 outputs a clock signal having a predetermined voltage level corresponding to the output frequency of the oscillating unit 1.

그 다음, 상기 증폭부(2)의 클럭출력신호를 인가받은 제1클럭발생부(3)는 인버터(INV1~INV3)를 통해 반전지연된 제2클럭발생부(4)의 출력신호인 클럭출력신호(CLK2)를 귀환받아 앤드게이트(AND1)를 통해 앤드조합하여 클럭출력신호(CLK1)를 출력한다.Next, the first clock generator 3 receiving the clock output signal of the amplifying unit 2 is a clock output signal which is an output signal of the second clock generator 4 which is delayed inverted through the inverters INV1 to INV3. The clock output signal CLK1 is output through the AND gate AND1 through the AND gate AND1.

또한, 제2클럭발생부(4)는 상기 증폭부(2)의 클럭출력신호를 인버터(INV4)를 통해 반전하고, 상기 제1클럭발생부(3)의 클럭출력신호(CLK1)를 인버터(INV5~INV7)를 통해 반전지연하여, 그 두 신호를 앤드게이트(AND2)에서 앤드조합하여 클럭출력신호(CLK2)를 생성함으로써, 상기 두 클럭출력신호(CLK1,CLK2)는 상호 위상이 반대로 출력되어, 위상이 상호 반대인 두 클럭신호를 얻을 수 있게 된다.In addition, the second clock generator 4 inverts the clock output signal of the amplifier 2 through the inverter INV4 and converts the clock output signal CLK1 of the first clock generator 3 into the inverter ( By inverting the delay through INV5 to INV7, the two signals are AND-combined at the AND gate AND2 to generate the clock output signal CLK2, so that the two clock output signals CLK1 and CLK2 are outputted with opposite phases. As a result, two clock signals having opposite phases can be obtained.

그러나, 상기와 같은 종래 클럭 발생회로는 위상이 완전히 반대인 두 클럭출력신호를 생성하여 두 클럭출력신호의 중복구간이 없어야 하나, 이를 위해서는 두 클럭출력신호의 부하 커패시턴스가 다른 경우 항상 일정한 비중복구간을 유지할 수 없어 그 신뢰성이 저하되는 문제점이 있었다.However, the conventional clock generation circuit as described above should generate two clock output signals that are completely opposite in phase so that there is no overlapping interval between the two clock output signals. There was a problem that can not maintain the reliability is lowered.

이와 같은 문제점을 감안한 본 발명은 부하 커패시턴스의 차이를 감지하여 클럭출력신호의 비중복구간을 보상하여 완전히 위상이 반대인 클럭출력신호를 출력할 수 있는 클럭 발생회로를 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a clock generation circuit capable of detecting a difference in load capacitance to compensate for a non-overlap period of a clock output signal and outputting a clock output signal that is completely out of phase.

도1은 종래 클럭 발생회로도.1 is a conventional clock generation circuit diagram.

도2는 본 발명 클럭발생회로도.2 is a clock generation circuit diagram of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1:발진부 2:증폭부1: Oscillator 2: Amplifier

3:제1클럭발생부 4:제2클럭발생부3: first clock generator 4: second clock generator

5:비중복보정부5: non-redundant government

상기와 같은 목적은 발진부에서 발진된 특정 주파수의 신호를 증폭하는 증폭부와; 상기 증폭부의 출력신호와 지연반전된 제2클럭출력신호를 논리조합하여 제1클럭출력신호를 생성하는 제1클럭발생부와; 반전된 증폭부의 출력신호와 상기 제1클럭발생부의 제1클럭출력신호를 논리조합하여 상기 제2클럭출력신호를 생성하는 제2클럭발생부와; 상기 제1 및 제2클럭출력신호를 인가받아 그 클럭출력신호의 중복구간을 검출하여 부하커패시턴스 값을 예측하고, 그 부하 커패시턴스값을 보상하여 상기 중복구간을 비중복구간으로 복원하는 비중복보정부로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is an amplifier for amplifying a signal of a specific frequency oscillated in the oscillator; A first clock generator for generating a first clock output signal by logically combining the output signal of the amplifier and the delayed second clock output signal; A second clock generator configured to logically combine the output signal of the inverted amplifier and the first clock output signal of the first clock generator to generate the second clock output signal; The non-overlapping section which receives the first and second clock output signals, detects the overlapping section of the clock output signal, predicts the load capacitance value, compensates the load capacitance value, and restores the overlapping section to the non-overlapping section. It is achieved by the configuration as described in detail with reference to the accompanying drawings, the present invention as follows.

도2는 본 발명 클럭 발생회로도로서, 이에 도시한 바와 같이 특정한 주파수의 신호를 발진하는 발진부(1)와; 상기 발진부(1)의 출력신호를 증폭하는 증폭부(2)와; 상기 증폭부(2)의 출력신호와 지연반전된 클럭출력신호(CLK2)를 논리조합하여 클럭출력신호(CLK1)를 생성하는 제1클럭발생부(3)와; 반전된 증폭부(2)의 출력신호와 상기 제1클럭발생부(3)의 클럭출력신호(CLK1)를 논리조합하여 상기 클럭출력신호(CLK2)를 생성하는 제2클럭발생부(4)와; 상기 두 클럭출력신호(CLK1,CLK2)의 출력신호를 인가받아 그 클럭출력신호(CLK1,CLK2)의 중복구간을 검출하여 그 중복구간을 비중복구간으로 복원하는 비중복보정부(5)로 구성된다.Fig. 2 is a clock generation circuit diagram of the present invention, and as shown therein, an oscillator 1 for oscillating a signal of a specific frequency; An amplifier 2 for amplifying the output signal of the oscillator 1; A first clock generator (3) for generating a clock output signal (CLK1) by logically combining the output signal of the amplifier (2) and the delayed inverted clock output signal (CLK2); A second clock generator 4 for generating the clock output signal CLK2 by logically combining the inverted output signal of the amplifier 2 and the clock output signal CLK1 of the first clock generator 3; ; A non-overlap compensation unit 5 which receives the output signals of the two clock output signals CLK1 and CLK2 and detects the overlapping section of the clock output signals CLK1 and CLK2 and restores the overlapping section to the non-overlapping section. do.

상기 비중복보정부(5)는 상기 클럭출력신호(CLK1,CLK2)를 인가받아 그 차이를 증폭하여 출력하는 차동증폭기(DAMP)와; 상기 차동증폭기(DAMP)의 부출력신호에 따라 도통제어되며, 드레인이 상기 제1클럭발생부(3)의 출력단에 접속된 엔모스 트랜지스터(NM1)와; 상기 엔모스 트랜지스터(NM1)의 소스와 접지사이에 접속된 커패시터(C4)와; 상기 차동증폭기(DAMP)의 정출력신호에 따라 도통제어되며, 드레인이 상기 제2클럭발생부(4)의 출력단에 접속되는 엔모스 트랜지스터(NM2)와; 상기 엔모스 트랜지스터(NM2)의 소스와 접지사이에 접속된 커패시터(C3)로 구성된다.The non-overlapping compensation unit 5 includes a differential amplifier DAMP receiving the clock output signals CLK1 and CLK2 and amplifying the difference and outputting the difference; An NMOS transistor NM1 whose conduction is controlled according to the negative output signal of the differential amplifier DAMP, and whose drain is connected to an output terminal of the first clock generator 3; A capacitor C4 connected between the source of the NMOS transistor NM1 and ground; An NMOS transistor NM2 whose conduction is controlled in accordance with the constant output signal of the differential amplifier DAMP and whose drain is connected to an output terminal of the second clock generator 4; And a capacitor C3 connected between the source of the NMOS transistor NM2 and ground.

이하, 상기와 같이 구성된 본 발명 클럭발생회로의 동작을 설명한다.Hereinafter, the operation of the clock generation circuit of the present invention configured as described above will be described.

먼저, 발진부(1)에서 발진된 소정 주파수의 출력신호를 인가받은 증폭부(2)는 이를 증폭하여 소정 전압 레벨의 클럭신호를 출력한다.First, the amplifier 2 receiving the output signal of a predetermined frequency oscillated by the oscillator 1 amplifies it and outputs a clock signal having a predetermined voltage level.

그 다음, 상기 증폭부(2)의 클럭출력신호를 인가받은 제1클럭발생부(3)는 인버터(INV1~INV3)를 통해 반전지연된 제2클럭발생부(4)의 출력신호인 클럭출력신호(CLK2)를 귀환받아 앤드게이트(AND1)를 통해 앤드조합하여 클럭출력신호(CLK1)를 출력하며, 제2클럭발생부(4)는 상기 증폭부(2)의 클럭출력신호를 인버터(INV4)를 통해 반전하고, 상기 제1클럭발생부(3)의 클럭출력신호(CLK1)를 인버터(INV5~INV7)를 통해 반전지연하여, 그 두 신호를 앤드게이트(AND2)에서 앤드조합하여 클럭출력신호(CLK2)를 생성한다.Next, the first clock generator 3 receiving the clock output signal of the amplifying unit 2 is a clock output signal which is an output signal of the second clock generator 4 which is delayed inverted through the inverters INV1 to INV3. The clock output signal CLK1 is output through the AND gate AND1 through the AND gate AND1, and the second clock generator 4 outputs the clock output signal of the amplifier 2 to the inverter INV4. Inverts the clock output signal CLK1 of the first clock generator 3 through an inverter INV5 to INV7, and combines the two signals at the AND gate AND2 to perform a clock output signal. Create (CLK2).

이때의 두 클럭출력신호(CLK1,CLK2)는 주파수가 동일하고 위상이 상호 반대이다.At this time, the two clock output signals CLK1 and CLK2 have the same frequency and opposite phases.

그 다음, 상기 두 클럭출력신호(CLK1,CLK2)를 인가받은 차동증폭기(DAMP)는 그 두 클럭출력신호(CLK1,CLK2)가 부하 커패시턴스의 차이에 의해 중복되는 구간이 있는 것으로 판단되면, 부하 커패시턴스가 큰쪽의 엔모스 트랜지스터(NM1 또는 NM2)에 인가되는 전압을 낮추게 되며, 이에 따라 부하 커패시턴스가 줄어들어 두 클럭출력신호(CLK1,CLK2)에 걸리는 부하 커패시턴스가 균등하게 제어되어 두 클럭출력신호(CLK1,CLK2)는 중복되는 구간이 발생하지 않게 된다.Next, when the differential amplifiers DAMP receiving the two clock output signals CLK1 and CLK2 have a section in which the two clock output signals CLK1 and CLK2 overlap by the difference in the load capacitance, the load capacitance is determined. Lowers the voltage applied to the larger NMOS transistor NM1 or NM2. As a result, the load capacitance is reduced, so that the load capacitance applied to the two clock output signals CLK1 and CLK2 is equally controlled, so that the two clock output signals CLK1, CLK2) does not cause overlapping sections.

상기한 바와 같이 본 발명 클럭 발생회로는 두 클럭출력신호의 로딩 커패시턴스를 검출하여 그 커패시턴스의 차를 보상함으로써, 주파수가 동일한 두 클럭출력신호가 위상이 정확하게 출력될 수 있도록 하여, 그 동작을 신뢰성을 향상시키는 효과가 있다.As described above, the clock generation circuit of the present invention detects the loading capacitance of the two clock output signals and compensates the difference of the capacitances, so that the two clock output signals having the same frequency can be outputted correctly in phase, thereby making the operation reliable. It is effective to improve.

Claims (2)

발진부에서 발진된 특정 주파수의 신호를 증폭하는 증폭부와; 상기 증폭부의 출력신호와 지연반전된 제2클럭출력신호를 논리조합하여 제1클럭출력신호를 생성하는 제1클럭발생부와; 반전된 증폭부의 출력신호와 상기 제1클럭발생부의 제1클럭출력신호를 논리조합하여 제2클럭출력신호를 생성하는 제2클럭발생부와; 상기 제1 및 제2클럭출력신호를 인가받아 그 차이를 증폭하여 출력하는 차동증폭기와, 상기 차동증폭기의 부출력신호에 따라 도통제어되며, 드레인이 상기 제1클럭발생부의 출력단에 접속된 제1엔모스 트랜지스터와, 상기 제1엔모스 트랜지스터의 소스와 접지사이에 접속된 제1커패시터와, 상기 차동증폭기의 정출력신호에 따라 도통제어되며, 드레인이 상기 제2클럭발생부의 출력단에 접속되는 제2엔모스 트랜지스터와, 상기 제2엔모스 트랜지스터의 소스와 접지사이에 접속된 제2커패시터를 포함하여, 클럭출력신호의 중복구간을 검출하여 부하 커패시턴스를 예측하고, 그 부하 커패시턴스값을 보상하여 상기 중복구간을 비중복구간으로 복원하는 비중복보정부로 구성하여 된 것을 특징으로 하는 클럭 발생회로.An amplifier for amplifying a signal of a specific frequency oscillated by the oscillator; A first clock generator for generating a first clock output signal by logically combining the output signal of the amplifier and the delayed second clock output signal; A second clock generator for generating a second clock output signal by logically combining the output signal of the inverted amplifier and the first clock output signal of the first clock generator; A differential amplifier that receives the first and second clock output signals and amplifies the difference and outputs the difference; and a first control in which a drain is connected to an output terminal of the first clock generator. An NMOS transistor, a first capacitor connected between the source and the ground of the first NMOS transistor, and conductively controlled according to a constant output signal of the differential amplifier, and a drain connected to an output terminal of the second clock generator. A second capacitor connected between the source and the ground of the second NMOS transistor and a ground, and detecting an overlapping section of a clock output signal to estimate a load capacitance, and compensate for the load capacitance value A clock generation circuit comprising a non-redundancy unit for restoring a redundant section to a non-redundant section. 삭제delete
KR10-2000-0054189A 2000-09-15 2000-09-15 Clock generating circuit KR100379334B1 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047659A (en) * 1989-09-22 1991-09-10 Deutsche Itt Industries Gmbh Non-overlapping two-phase clock generator utilizing floating inverters
JPH05122018A (en) * 1991-10-29 1993-05-18 Olympus Optical Co Ltd Two-phase pulse generation circuit
KR940005876Y1 (en) * 1991-12-17 1994-08-26 금성일렉트론 주식회사 Non-superimposed clock pulse generating circuit
JPH07154223A (en) * 1993-11-29 1995-06-16 Nippondenso Co Ltd Two phase clock generator
JPH11150457A (en) * 1997-11-19 1999-06-02 Nec Eng Ltd Two-phase clock generating circuit
KR20000044168A (en) * 1998-12-30 2000-07-15 전주범 Non-overlapping clock generator circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047659A (en) * 1989-09-22 1991-09-10 Deutsche Itt Industries Gmbh Non-overlapping two-phase clock generator utilizing floating inverters
JPH05122018A (en) * 1991-10-29 1993-05-18 Olympus Optical Co Ltd Two-phase pulse generation circuit
KR940005876Y1 (en) * 1991-12-17 1994-08-26 금성일렉트론 주식회사 Non-superimposed clock pulse generating circuit
JPH07154223A (en) * 1993-11-29 1995-06-16 Nippondenso Co Ltd Two phase clock generator
JPH11150457A (en) * 1997-11-19 1999-06-02 Nec Eng Ltd Two-phase clock generating circuit
KR20000044168A (en) * 1998-12-30 2000-07-15 전주범 Non-overlapping clock generator circuit

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