KR100379284B1 - (A fast variable-length decodeer using plane separation - Google Patents

Abstract

The present invention relates to a fast variable length code decoder using plane division. In particular, the present invention relates to a fast variable length decoder that improves the decoding processing speed of a variable length code by separating a plane of data input unit and simultaneously performing a code length of a variable length code, a code judgment, and a code to be processed in the next step.

The decoding process in the conventional variable length decoder performs the decoding process of the next stage only when the total execution time of the decoder structure representing the decoding process in time at the present stage is performed, whereas the present invention provides the data input plane as the input plane. And a control signal for controlling whether or not a bitstream is supplied to the input plane and the logical sum plane by two moving processes in the divided data input plane and the addition and subtraction operations of the code length signal in the adder and the subtractor. By performing the decoding process, which shows the decoding process in time, the time that is finally completed in each of Tips, Tops, and Td is a one-step decoding completion time, which can be applied to real-time storage, editing, or HDTV of multimedia. We present a fast variable length code decoder with reduced execution time.

Description

Fast fast variable-length decoder using plane separation

The present invention relates to a fast variable length code decoder using plane division. In particular, the present invention relates to a fast variable length decoder that improves the decoding processing speed of a variable length code by separating a plane of data input unit and simultaneously performing a code length of a variable length code, a code judgment, and a code to be processed in the next step.

Recently, multimedia products such as multimedia PCs, video on demand (VOD), and high definition TVs have been in the spotlight. When processing the video and sound, which are the main contents of the multimedia products, by Pulse Code Modulation for storing or transmitting, the amount of data to be stored is large and the transmission time is also consumed. The same information signals are stored or transmitted by compression.

In addition, various methods using a parallel or pipe-line structure of the decoder for reproducing the compressed information have been proposed.

In this case, the variable length code / decoding method using the bias of the generation probability of the original data is generally used.

1 is a circuit diagram of a variable-length decoder based on a programmable logic array (PLA) developed by prior art lines Sun and Lei.

As shown in FIG. 1, a conventional circuit diagram of a variable long length signal includes an input buffer 1 to which a bitstream to be decoded is supplied, and a register unit to receive a bitstream from the input buffer. 2, 3, a first barrel shifter 4, and data supplied from the first barrel shifter 4 are code word table 5a and code length table. a programmable logic array 5 for decoding using the table 5b, a decoded word table 5c, a second barrel shifter 6 for determining whether to supply a new bitstream, It consists of an AND gate 10 that controls the supply of a new bitstream.

Here, the input buffer 1, the register parts 2 and 3, and the first barrel shifter 4, which are the movement paths of the bit stream to be decoded, are referred to as a data input plane.

In the bitstream to be decoded supplied from the input buffer 1, a 16-bit bitstream is first input to the first register 2, and a 16-bit bitstream input to the first register 2. Is supplied to the second register (3) and another 16-bit bitstream from the input buffer (1) is supplied to the first register.

Here, the code length signal Code length of the decoded information stored in the third register 8 is reset, and the second barrel shifter 6 is 0 bits.

The code length signal is a code length signal generated during the decoding process in the programmable logic array 5 and indicates a length of a bitstream to be decoded in a next step.

The first barrel shifter 4 is programmable with the length of the code length signal supplied from the third register 8 to the input data which is a bitstream stored in the first register 2 and the second register 3. The codeword table 5a of the logic array 5 is moved.

In this case, the input data to be decoded from the first barrel shifter 4 is most significant 16 bits.

The codeword table 5a of the programmable logic array 5 has parallel data matching to find the data to be decoded at this stage with the input data which is the bitstream supplied from the first barrel shifter 4. Perform the process.

The data to be decoded from the codeword table 5a is decoded by a code length signal and a decoded data indicating a length of a bitstream to be decoded in a next step in a code length table 5b. do.

Here, the code length signal is supplied to the second barrel shifter 6, and the decoded data is output via the decoded word table 5c.

In addition, the supplied code length signal is calculated as follows in the second barrel shifter 6 to determine the number of cases in which the decoding process or the read signal will be generated.

Where D2 is the third register (8). n is a sequence number of the data to be decoded.

When D2 (n-1) + L <16 (bit) in Equation 1, it means that the amount of the bitstream capable of decoding in the next step is stored in the second register.

By the calculation of Equation 1, the code length signal is supplied to the first barrel shifter 4 to inform the length of the bitstream to be decoded in the next step.

That is, it is configured to perform the decoding process of the second step without the next 16-bit bitstream from the input buffer (1).

However, when D2 (n-1) + L &gt; 16 (bit) in Equation 1, the logic sum gate 7 supplies the bitstream supply signal for supplying the 16-bit bitstream to the first register 2; It is supplied to the fourth register 9 via.

The bitstream supply signal supplied to the fourth register 9 is configured to be supplied to the first register 2 by generating a read signal from the logical multiplication gate 10.

The 16-bit bitstream stored in the first register 2 is supplied to the second register by the supplied read signal, and a new 16-bit bitstream is supplied from the input buffer 1.

In addition, among the decoded information stored in the third register 8, a code length signal Codelength is reset, and the second barrel shifter 6 is 0 bits.

By repeatedly performing the above steps, the encoded variable length signal performs a decoding process.

Here, the execution time Tsl of the decoder structure of the variable-length-length signal based on the parallel programmable logic array 5 to be decoded is defined as follows.

① When receiving a new bit stream from the input buffer,

Tsl = Tpm + Tsu + Tcd + Tiu + Tis

② In case of not receiving new bit stream from input buffer,

Tsl = Tpm + Tsu + Tcd + Tis

As described above, the execution time Tsl of the conventional decoder structure is defined.

Here, Tpm is a time for performing parallel pattern matching in the programmable logic array 5, Tsu is a time for performing equation (1) in the second barrel shifter (2),

Tcd is the time taken to determine whether to supply a new bitstream from the second barrel shifter 2 to the first register, and when Tiu supplies a new bitstream to the first register 2, the first register 2 And a time required for updating the bitstream in the second register, Tis is an execution time of the first barrel shifter 4.

As described above, the execution time for decoding one bitstream of the variable length signal encoded is configured to perform the decoding process of the next step only when the execution time of the decoder structure is sequentially completed.

However, in the decoding process of the variable length signal based on the conventional parallel programmable logic array 5, the decoding process of the next stage is performed only when the execution time of the decoder structure indicating the time of performing the current decoding process is completed sequentially. There is a problem that the decoding processing speed is limited.

The present invention is to solve the problem that the decoding processing speed of the variable length signal based on the parallel programmable logic array (5) is limited, the object of the present invention is the decoding process of the variable length signal based on the parallel programmable logic array (5) In addition, the present invention provides a structure for improving the overall decoding processing speed by separating the plane of the input unit of the data to be decoded and simultaneously performing the parallel matching process of the data to be decoded and the input of the code length signal to be decoded in the next step.

As a technical idea for achieving the object of the present invention, a decoding process is performed on an input plane and a logical sum plane to which a bitstream to be decoded is supplied, and a bit length supplied from the logical sum plane to a code length signal and decoded data. A programmable logic array, an adder and a subtractor for controlling the bitstream by adding and subtracting a code length signal supplied from the programmable logic array, to simultaneously perform two shift processes and a code determination process. A fast variable length decoder is proposed to shorten the decoding time.

1 is a circuit diagram of a variable length signal decoder based on a conventional programmable logic array (PLA).

2 is a circuit diagram of an embodiment of the present invention in which a variable length signal decoder is plane-divided to improve decoding speed.

3 is a table showing an embodiment of performing a decoding process using the present invention divided two planes.

<Description of Major Symbols in Drawing>

1,1 ′: Input buffer 2: First register

3: 2nd register 4,4 ′: 1st barrel shifter

5,5 ′: programmable logic array

5a, 5a ′: Codeword Table 5b, 5b ′: Code Length Table

5c, 5c ': Decryptor table 6,6': Second barrel shifter

7: logical sum gate 8: third register

9: 4th register 10: Logical gate

11,11 ': input plane 12: first multiplexer

13: input register 14: logic gate portion

15: second multiplexer 16: output register

17,17 ': logical sum plane 18: fifth register

19: Subtractor 20: Adder

21: 6th register

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment of the present invention will be described in detail.

2 is a circuit diagram in which a variable length signal decoder is divided into planes to improve decoding processing speed.

Except for the same components and interactions of Figure 1 except for the core of the present invention will be omitted.

As shown in FIG. 2, the first bitstream supplied from the input buffer 1 ′ is configured to be supplied to the output register 16.

In addition, the second bitstream is sequentially configured to be supplied to the input register 13.

Here, the 32-bit bitstream is latched in the output register 16, and the 16-bit bitstream is latched in the input register 13.

The 32-bit bitstream latched in the output register 16 is supplied to a code word table 5a 'of the programmable logic array 5'.

A parallel pattern matching process is performed to find data to be decoded at this stage using input data which is a 32-bit bitstream supplied to the code word table 5a '.

A code length table 5b of the programmable logic array 5 'is a code length signal representing a length equal to the number of bits decoded with data to be decoded from the codeword table 5a' and The decoding process is performed with the decoded data.

For example, if two bits of a 32-bit bitstream are decoded, a code length signal representing a length equal to the number of decoded bits may be respectively transmitted by the first barrel shifter 4 'and the second barrel shifter 6'. Each bit stream is configured to rotate by movement.

In addition, the data moved to rotate two bits to the second barrel shifter 6 ′ is configured to be output from the output register 16 and supplied to the second multiplexer 15.

In addition, the second multiplexer 15 having a signal output from the logic sum gate unit 14 and a signal output from the output register 16 as an input terminal outputs an input of the output register 16 to output the input register 16. The 32-bit bitstream remaining in the input stream is input to the second barrel shifter 6 'so that the 32-bit bitstream supplied in the first stage is input to the second barrel shifter 6'. By shifting 2 bits to the left in the shifter 6 ', the bitstream is cut.

The process of rotating by moving two bits to the first barrel shifter 4 'is also configured to be the same as the rotation process of the second barrel shifter 6'.

That is, the 32-bit bitstream output from the input register 13 is configured to be supplied to the first barrel shifter 4 '.

In addition, because of the 32-bit bitstream supplied from the input register 13, the first multiplexer 12 is configured to output a bitstream in which two bits are rotated to the input register 13.

In addition, the amount of data rotated in the first barrel shifter 4 'and the second barrel shifter 6' is generated by the decoding process in the code length table 5b 'of the programmable logic array 5'. It is configured to be determined by the length signal CL (n).

In addition, the amount of data lost by moving left in the second barrel shifter 6 ′ of the logic sum plane 17 is configured to be filled with least significant bits in the input plane 11.

The amount of bits remaining in the input plane 11 is calculated as follows.

RL (n) = CRL (n-1)-CL (n)

If CRL (n) = CRL (n-1)-CL (n) <Lmax,

CRL (n) = CRL (n-1)-CL (n) + Lmax

Here, CRL (n) is the number of bits remaining in each input plane, CL (n) is a decoded code length signal, and Lmax is a maximum code length signal to be decoded, and is defined as 16 bits in the present invention. N is a sequence number of the data to be decoded.

In the case of 1), when the remaining bits except the bits shifted for rotation in the output register 16 are 16 bits or more, since the maximum number of bits to be decoded is defined as 16 (Lmax) bits, It is configured to perform the decoding process of the next step in the code length table 5b 'of the programmable logic array 5' without operation.

In the case of ②, if the remaining bits excluding the bits shifted for rotation in the output register 16 are 16 bits or less, the programmable logic array 5 'with the existing rotated bitstream in the logic sum plane 17 is present. In the code length table 5b ', the decoding process is continued.

The remaining number of bits is configured to be controlled by the sum of the input register 13 and the output register 16 inputted to the logic sum gate portion 14.

That is, when performing the decoding process step by step, the number of lower bits latched in the output register 16 is gradually filled with '0' bits by rotation, and the number of bits latched in the output register 16 is 16 bits. In the following case, the logical sum gate portion 14 is configured to yield a meaningful output value.

The meaningful output value generated by the logic sum gate unit 14 means that the number of bits of the output register 16 is lost due to the rotation of the second barrel shifter 6 ', and the first bit shifter 4' also has the same bit. The number of bits is also rotated in the input register 13 because the number of bits is rotated. If the number of bits is 16 bits or less, the logical sum gate unit 14 rewrites the bit stream on the logical sum plane 17 as a result of performing the logical sum. This means that you get a meaningful output to save.

In this case, when the output value of the meaningful bitstream is output from the logical sum gate, the adder 20 and the subtractor 19 are configured to generate a signal indicating that more than 16 bits are generated by adding or subtracting the number of bits. .

By controlling the first multiplexer 12 and the second multiplexer 15 by the signals generated by the adder 20 and the subtractor 19, the bitstream is input to the respective registers in the input buffer 1 '. Lose.

The decoding process is configured to be repeatedly performed as described above.

3 is a table illustrating an embodiment of performing a decoding process using two divided planes.

As shown in FIG. 3, n, a sequence number of data to be decoded, a symbol representing decoded data, a CL representing a code length signal among decoded information, and a number of bits remaining OR-plane (17 ') consisting of CRL, Carry indicating whether bit stream is supplied from input buffer, number of bits stored in sequential number order of data, and decoding N, which is a sequential number of data, a symbol representing decoded data, a CW word represented by a binary number, CL indicating a code length signal among decoded information, and a number of bits stored in the sequence number of data. It consists of an input plane (11 ') composed of alignment.

At n = 0 of the OR-plane 17 ', the output register 16 is supplied with two 16 bits.

Here, the CRL is 32 bits, and the next 16 bits are stored in the upper 16 bits of the input register 13.

The decoding process is performed in the programmable logic array 5 'without input of an additional bitstream until n = 4.

When n = 5, the input register 13 rotates by 18 bits in the left direction.

That is, since the remaining bit length is smaller than 16 bits, the output register 16 is re-stored and the input buffer is simultaneously stored as a result of performing the logical sum of the input register 13 and the output register 16 in the logic sum gate unit 14. The bitstream is configured to be supplied from 1 'to the input plane 11.

In the supply of the bitstream of the input plane 11, the most significant bit 32-CRL (n) first inputted is shifted to the least significant bit 32-CRL (n) of the input plane 11 and secondly inputted. The bits are configured to move to the most significant bit of the input plane 11.

That is, in the logical sum plane 17 'of FIG. 3, the CRL 6 is 27 bits, the most significant 5 bits of the supplied bitstream are shifted to the least significant 5 bits of the input plane 17', and the remaining 11 bits of the bitstream. Is shifted to the most significant 11 bits of the input plane 17 '.

Here, the input alignment process in the first barrel shifter 4 'of the input plane 17' is a secondary process, and the codeword table 5a of the input logic process and the programmable logic array 5 is performed. ′) Does not affect the overall decoding execution time as it occurs simultaneously with the process of examining the data to be decoded.

As described above, the variable-length code decoder based on the programmable logic array of the present invention simultaneously performs two shifts in each input plane 11 and the logic sum plane 17 by using a code length CL (n) signal. .

In addition, CRL (n) is controlled by the adder 20 and the subtractor to supply a new bitstream.

Here, the execution time Tps of the decoder structure of the variable-length-length signal based on the decoded parallel programmable logic array 5 'of the present invention is defined as follows.

① When receiving a new bit stream from the input buffer,

Tps = Tpm + max (Tips, Tops, Td) + Tor

② In case of not receiving new bit stream from input buffer,

Tps = Tpm + max (Tips, Tops, Td)

As described above, the execution time (Tps) of the decoder structure of the present invention is defined.

Here, Tips and Tops are the bitstream movement time in the input plane 11 and the logic sum plane 17, Td is the time required to determine whether to supply a new bitstream, and Tor is the logic sum gate portion of the logic sum plane 17. This is the time taken to perform the logical sum operation in (14).

The decoding execution time of the present invention is not the sum of Tips, Tops, and Td, but the longest of the respective execution times.

As described above, according to the present invention, in the decoding process of a variable long-length signal based on a parallel programmable logic array, the plane of the data input unit to be decoded is divided into two planes to perform a corresponding decoding process in each plane at the same time. During the decoding process of the multimedia, the decoding time can be shortened, so that the real time storage, editing, and compression / restore of data such as HDTV can be implemented quickly.

Claims (8)

In the fast variable length code decoder, Two separate input planes into which data is input, A programmable logic array (PLA) connected to one input plane of the separated input planes, A subtractor connected to the programmable logic array PLA; An adder connected to the subtractor, Among the information decoded in the programmable logic array PLA, a code length signal is simultaneously supplied to each input plane and subtractor, By the code length signal supplied from the programmable logic array PLA, each input plane examines the remaining bit stream by the rotation of the data. A fast variable length decoder using plane division, characterized by simultaneously performing supply control of a bitstream to be decoded by subtracting and subtracting data from the subtractor and the adder by the code length signal supplied from the programmable logic array PLA. . The method according to claim 1, wherein one of the two input planes, A first barrel shifter supplied with a code length signal representing a length equal to the number of bits decoded by the PLA; An input register connected to supply the bitstream output to the barrel splitter; A high speed variable length code using a plane splitter, comprising: a first multiplexer connected between the barrel splitter and the input register and outputting a rotation stream decoded into the input register by the bitstream supplied from the input register; Decoder. The method of claim 2, wherein the other input plane, A logic sum gate portion including a plurality of logic sum gates, A second multiplexer connected to the logic sum gate unit and an output register to output an input of an output register using the output signal as an input terminal, and inputting a bit stream remaining in the output register to a second barrel shifter; A second barrel shifter connected to the second multiplexer and moving to one side by the number of coded bits to cut a bitstream; And an output register connected to the second barrel shifter and outputting data to the second multiplexer so that the second barrel shifter can move the number of bits. The method according to claim 1, The amount of the bitstream remaining in the input plane is a fast variable length code decoder using plane division, characterized in that the following equation. n: sequence number of the data to be decoded When CRL (n) = CRL (n-1)-CL (n)> Lmax RL (n) = CRL (n-1)-CL (n) CRL (n): Number of bits remaining in each input plane CL (n): Decoded code length signal Lmax: Maximum code length signal to be decoded The method according to claim 4, The amount of the bitstream remaining in the input plane is a fast variable length code decoder using plane division, characterized in that the following equation. CRL (n) = CRL (n-1)-CL (n) + Lmax The method according to claim 4 or 5, And a number of bits of Lmax is 16 bits. The method according to claim 1 or 4, The execution time (Tps) of the decoder structure of the fast variable length signal is a fast variable length code decoder using plane division, characterized in that the following equation. Tps = Tpm + max (Tips, Tops, Td) Tips, Tops: Bitstream movement time in input plane and logical sum plane Td: time taken to decide whether to supply a new bitstream The method according to claim 1 or 5, The execution time (Tps) of the decoder structure of the fast variable length signal is a fast variable length code decoder using plane division, characterized in that the following equation. Tps = Tpm + max (Tips, Tops, Td) + Tor Tor: Time taken to perform the OR operation in the OR block of the OR plane