JP2002111509A - Variable length code decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed variable length code decoder which is capable of decoding variable long codes at a high speed. SOLUTION: A data input is divided into two parts, a first input part 11 and a second input part (logical OR input) 17, and data move processing and control processing, which controls the supply of a bit stream to the input parts 11 and 17 by code length signals, that undergo addition/subtraction operation through an adder 20 and a subtractor 19 are both executed at the same time, at the input parts 11 and 17 (logical OR input). A decoding time is determined, according to the longest time among the traveling times of a bit stream at the first input part 11, the traveling time of a bit stream at the second input part (logical OR input) 17, and a time required for determining whether a bit stream is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable-length code decoder, and more particularly, to a data input part which is divided into two parts, a data moving process at each input part and a data supply to each input part. The present invention relates to a variable-length code decoder in which the control process of permission / inhibition is performed simultaneously to improve the speed of variable-length code decoding.

[0002]

2. Description of the Related Art Recently, multimedia products such as a multimedia PC, a custom video (VOD), and a high-definition TV (HDTV) have been spotlighted. When storing or transmitting the video signal and the audio signal, which are the main contents of such multimedia products, by processing with pulse code modulation, a large amount of data is stored and a large amount of transfer time is consumed. Therefore, information signals such as video signals and audio signals are compressed and stored or transferred. Further, in a decoder for restoring a compressed information signal, various decoding methods using a parallel or pipeline structure are used. As a method for compressing / decompressing an information signal or the like, a variable-length encoding / decoding method using a weighted probability of occurrence of original data is generally used.

FIG. 3 shows prior art Sun and Ray.
FIG. 2 is a circuit diagram of a variable-length decoder based on a programmable logic array (PLA) developed by J. (Lei).

As shown in FIG. 3, a conventional variable length decoder includes an input buffer 1 to which a bit stream to be decoded is supplied, and a first and a first buffer 1 to which a bit stream is supplied from the input buffer 1. The second registers 2 and 3 and the first
A barrel shifter 4, a programmable logic array 5 for performing a decoding process on data supplied from the first barrel shifter 4 using a codeword table 5a, a code length table 5b, and a decoded word table 5c; And a logical AND gate 10 for controlling the supply of a new bit stream. Here, the input buffer 1 of the moving path of the bit stream to be decoded, the first and second registers 2,
3 and the first barrel shifter 4 constitute a data input unit.

In the bit stream to be decoded supplied from the input buffer 1, first, a 16-bit bit stream is input to the first register 2, and the 16-bit bit stream input to the first register 2 is stored in the second register 3. At the same time, a different 16-bit bit stream is supplied from the input buffer 1 to the first register 2.

Here, the code length signal in the decoded information stored in the third register 8 is reset, and the second barrel shifter 6 becomes 0 bit. The code length signal is generated from the decoding process in the programmable logic array 5 and is a signal indicating the length of the bit stream to be decoded in the next stage.

The first barrel shifter 4 has a first register 2
The input data of the bit stream stored in the second register 3 is moved to the code word table 5a of the programmable logic array 5 by the length of the code length signal supplied from the third register 8. Here, the input data output from the first barrel shifter 4 and decoded is the most significant 16 bits.

The codeword table 5a of the programmable logic array 5 performs a parallel pattern matching process that finds data to be decoded at this stage using the input data of the bit stream supplied from the first barrel shifter 4. The decoded data found in the codeword table 5a is a code length signal for notifying the length of the bit stream to be decoded in the next stage in the code length table 5b and the decoded data. Execute Here, the code length signal is supplied to the second barrel shifter 6, and the decoded data is output via the decoded word table 5c.

Further, the supplied code length signal is used to determine the number of cases in which a decoding process should be performed in the next stage or a read signal should be generated.
It is calculated by the barrel shifter 6 as shown in equation (1). D2 (n) = {D2 (n-1) + L} modulo 16 (1) where D2 is the amount of the bit stream stored in the third register 8. N is the sequential number of the data to be decoded.

If D2 (n-1) + L <16 (bits) in the above equation (1), the amount of the bit stream that can be decoded in the next stage is stored in the second register 3. Means that. The code length signal obtained by the calculation of the above equation (1) is supplied to the first barrel shifter 4, and reports the length of the bit stream to be decoded in the next stage.
That is, the second decoding process is performed without the next 16-bit bit stream from the input buffer 1.

However, in the above equation (1), D2 (n-1) + L>
In the case of 16 (bits), the bit stream supply signal for executing the supply of the 16-bit bit stream to the first register 2 is transmitted through the OR gate 7 to the fourth register 9.
To supply. The bit stream supply signal supplied to the fourth register 9 is configured to generate a read signal at the AND gate 10 and supply the read signal to the first register 2.

According to the supplied read signal, the 16-bit bit stream stored in the first register 2 is converted into a second bit stream.
A new 16-bit bit stream is supplied from the input buffer 1 to the register 3. Further, the code length signal in the decoded information stored in the third register 8 is reset, and the second barrel shifter 6 becomes 0 bits.

The variable length signal encoded by performing the above steps repeatedly performs a decoding process.

Here, the execution time Tsl of the decoder structure of the variable length signal based on the parallel programmable logic array 5 to be decoded is defined as follows. When a new bit stream is supplied from the input buffer 1, Tsl = Tpm + Tsu + Tcd + Tiu + Tis When a new bit stream is not supplied from the input buffer 1, Tsl = Tpm + Tsu + Tcd + Tis

Here, Tpm is the time for performing parallel pattern matching in the programmable logic array 5,
Is the time to execute equation (1) in the second barrel shifter 2, Tcd
Is the time required for the second barrel shifter 2 to determine whether a new bit stream can be supplied from the first register 1,
Tiu is the time required to update the bit stream to the first register 2 and the second register 3 when a new bit stream is supplied to the first register 2, and Tis is the execution time of the first barrel shifter 4.

As described in detail, conventionally, the execution processing for decoding the bit stream which is one of the encoded variable length signals is performed after each execution processing of the decoder structure is sequentially completed. It is configured to execute the next stage of the decoding process, and the execution time for decoding the variable length signal is the total time of each of the above execution processes.

[0017]

As described above, in a conventional decoding process of a variable length signal based on a parallel programmable logic array, a decoder structure indicating a time for executing a current decoding process is used. After the execution time elapses, the next stage of the decoding process is executed, so that there is a problem that the decoding processing speed is limited.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to input data to be decoded in a process of decoding a variable length signal by a parallel programmable logic array. Is divided into two, and a process of moving data in each input unit and a process of controlling whether to supply new data to be decoded to each input unit are simultaneously executed, so that the entire decoding process is performed. An object of the present invention is to provide a variable length code decoder capable of improving the speed.

[0019]

According to a first aspect of the present invention, there is provided a variable length code decoder, comprising: two separated input units to which data to be decoded is input; and one of the two input units. A programmable logic array connected to the programmable logic array for decoding the data, and a subtractor and an adder connected to an output end of the programmable logic array. A code length signal indicating the number of bits of the data decoded in is supplied to the two input units and the subtracter at the same time, and data is moved by the two input units based on the supplied code length signal. And the process of controlling the input of the data to be decoded to the two input units based on the addition and subtraction operations in the subtractor and the adder using the supplied code length signal. Characterized by being adapted to.

According to a second aspect of the present invention, in the variable length code decoder according to the first aspect, each of the two input units has one barrel shifter, one multiplexer, and one output latch.

According to a third aspect of the present invention, in the variable length code decoder according to the second aspect, one of the two input units is a logical sum input unit having a logical sum gate circuit. I do.

According to a fourth aspect of the present invention, in the variable length code decoder according to the first aspect, the number of bits CRL (n) of the data remaining in each of the two input units is represented by the following equation. When CRL (n) = CRL (n-1) -CL (n)> Lmax, CRL (n) = CRL (n-1) -CL (n) where n is the sequential number of data to be decoded CL (n): decoded code length signal Lmax: decoded maximum code length signal

According to a fifth aspect of the present invention, in the variable length code decoder according to the fourth aspect, the number of bits CRL (n) of data remaining in each of the two input units is represented by the following equation. If CRL (n) = CRL (n-1) -CL (n) <Lmax, CRL (n) = CRL (n-1) -CL (n) + Lmax

According to a sixth aspect of the present invention, in the variable length code decoder according to the fourth or fifth aspect, the number of bits of Lmax is 16 bits.

The variable-length code decoder according to claim 7 is characterized in that, in claim 1 or 4, the entire processing time Tps is given by the following equation. If CRL (n) = CRL (n-1) -CL (n)> Lmax, then Tps = Tpm + max (Tips, Tops, Td), where Tpm: time for performing pattern matching in the programmable logic array Tips, Tops: moving time of data at each of the two input sections Td: time required to determine whether new data can be input

The variable-length code decoder according to claim 8 is characterized in that, in claim 1 or 5, the entire processing time Tps is represented by the following equation. If CRL (n) = CRL (n-1) -CL (n) <Lmax, then Tps = Tpm + max (Tips, Tops, Td) + Tor, where Tor: one of the two input units is a logical sum A logical sum input unit having a gate circuit, and a time required to execute a logical sum operation in the logical sum gate circuit of the logical sum input unit

In the variable-length code decoder according to the present invention, the code lengths of the first and second input sections to which the bit stream to be decoded is supplied and the bit stream supplied from the second input section are provided. A programmable logic array for performing a decoding process on the signal and the decoded data, and an adder and a subtractor for controlling a bit stream by adding and subtracting a code length signal supplied from the programmable logic array. (2) The process of rotating (shifting) the data at the two input units and the process of controlling the bit stream supply to the two input units are simultaneously executed to reduce the time required for the decoding process.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings showing the structure and operation of the embodiments. FIG. 1 is a circuit diagram of a variable-length code decoder according to the present invention in which an input section is divided to improve a decoding processing speed. The description of the same components and operations as those in FIG. 3 except for the characteristic portions of the present invention will be omitted.

As shown in FIG. 1, the first bit stream supplied from the input buffer 1 'is supplied to the output register 16. Further, the second bit stream is sequentially supplied to the input register 13. Here, output register 16
, A 32-bit bit stream is latched, and the input register 13 latches a 16-bit bit stream.

The 32-bit bit stream latched in output register 16 is provided to a codeword table 5a 'of a programmable logic array (PLA) 5'. The codeword table 5a 'performs a parallel pattern matching process in which input data of the supplied 32-bit bit stream is searched for data to be decoded at this stage.

The code length table 5b 'of the programmable logic array 5' has a code length representing the number of decoded bits having the data to be decoded found in the code word table 5a '. A decoding process is performed on the signal and the decoded data. Here, for example, if two bits in a 32-bit bit stream are decoded, a code length signal representing the length of the decoded bit number is supplied to the first barrel shifter 4 'and the second barrel shifter 6'. By doing so, each of the two bit streams is configured to rotate by movement.

The data moved to rotate the second barrel shifter 6 'by 2 bits is output from the output register 16 and supplied to the second multiplexer 15. A second multiplexer 15 that receives as input the signal output from the OR gate circuit 14 and the signal output from the output register 16
Outputs the input from the output register 16 so that the 32-bit bit stream remaining in the output register 16 is input to the second barrel shifter 6 ', and the 32-bit bit stream supplied in the first stage is The bit stream is input to the second barrel shifter 6 'and moved to the left by 2 bits by the second barrel shifter 6' to cut the bit stream.

The process of moving and rotating two bits by the first barrel shifter 4 'is configured to be the same as the process of rotating the second barrel shifter 6'. That is, the 32-bit bit stream output from the input register 13 is supplied to the first barrel shifter 4 '. Also, the input register
For the 32-bit bit stream supplied from 13, the first multiplexer 12 also outputs a bit stream in which 2 bits are rotated to the input register 13.

The amount of data rotated by the first barrel shifter 4 'and the second barrel shifter 6' is determined by the code length signal CL (n) generated by the decoding process in the code length table 5b 'of the programmable logic array 5'. ). Further, the amount of data lost by moving to the left by the second barrel shifter 6 'of the second input unit 17 as the OR input unit is filled with the least significant bit in the first input unit 11.

The amount of bits remaining at the input is calculated as follows. If CRL (n) = CRL (n-1) -CL (n)> Lmax, CRL (n) = CRL (n-1) -CL (n) CRL (n) = CRL (n-1)- If CL (n) <Lmax, CRL (n) = CRL (n-1) -CL (n) + Lmax where CRL (n) is the number of bits remaining in each input section, and CL (n) n) is the decoded code length signal,
Lmax is the maximum code length signal to be decoded in the present invention.
Defined by 16 bits. N is the sequential number of the data to be decoded.

In the above case, that is, when the bits moved for rotation in the output register 16 are excluded and the remaining bits are 16 bits or more, the maximum number of bits to be decoded is
Since it is defined by 16 (Lmax) bits, the operation at the second input unit (logical sum input unit) 17 is not performed, and the next decoding process is performed by the code length table 5b 'of the programmable logic array 5'. Execute.

In the above case, that is, when the bits that have been moved for rotation in the output register 16 are excluded and the number of remaining bits is 16 bits or less, the second input unit (logical sum input unit) 17 outputs the existing rotation. Code length table 5 of the programmable logic array 5 '
The decoding process is continuously executed at b '.

The number of remaining bits is controlled by the total output of the input register 13 and the output register 16 input to the OR gate circuit 14. That is, when the decoding process is performed stepwise, the lower bits latched in the output register 16 are gradually filled with '0' bits by rotation, and the number of bits latched in the output register 16 becomes 16 bits or less. If so, the OR gate circuit 14 is configured to output a meaningful output value.

The generation of a meaningful output value in the OR gate circuit 14 is caused by the fact that the number of bits in the output register 16 disappears due to the rotation of the second barrel shifter 6 'and the first barrel shifter 4' also rotates by the same number of bits. Input register 13
However, if the number of bits is rotated and each bit number is 16 bits or less, the OR gate circuit 14
Means that an output value meaning that the bit stream is to be stored again is output to the second input unit (OR input unit) 17.

Here, when a meaningful bit stream output value is output from the OR gate circuit 14, a signal indicating that 16 bits have been exceeded is also generated in the adder 20 and the subtracter 19 due to the addition / subtraction calculation of the number of bits. It is configured to be. By controlling the first multiplexer 12 and the second multiplexer 15 by the signals generated by the adder 20 and the subtracter 19, the bit stream is input to the respective register sections in the input buffer 1 '. .

The decoding process can be repeatedly executed by a series of processes as described above.

FIG. 2 is a table showing an embodiment in which a decoding process is performed using two divided input units. As shown in FIG. 2, the sequential number n of the data to be decoded, the symbol representing the decoded data, and the CL representing the code length signal in the decoded information,
A second input unit (logical OR) comprising a CRL indicating the number of remaining bits, a Carry indicating whether or not a bit stream can be supplied from the input buffer, and an arrangement of the number of bits stored in the order of data numbers. (Input unit) 17, and the serial number n of the data to be decoded, a symbol representing the decoded data, a CW of a codeword represented by a binary number, and a code length in the decoded information. CL representing the signal
And a first input unit 11 composed of an arrangement of the number of bits stored in the data in the order of the number.

When n = 0 of the second input section (OR input section) 17, the output register 16 receives two 16-bit supplies. Here, the CRL is 32 bits, and the next 16 bits are stored in the upper 16 bits of the input register 13.

Until n = 4, the decoding process is performed on the programmable logic array 5 'without inputting an additional bit stream.

When n = 5, the input register 13 rotates 18 bits to the left. That is, since the remaining bit length is smaller than 16 bits, the output register 16 is re-saved by the result of executing the logical sum of the input register 13 and the output register 16 by the OR gate circuit 14, and at the same time, the input buffer 1 ′ To the first input 11.

The most significant bit (32-CRL (n)) input for the first time in the supply of the bit stream of the first input unit 11 is moved to the least significant bit (32-CRL (n)) of the first input unit 11. The second input bit is moved to the most significant bit of the first input unit 11. That is, in the second input unit (OR input unit) 17 of FIG. 2, the CRL 6 is 27 bits, the most significant 5 bits of the supplied bit stream are moved to the least significant 5 bits of the first input unit 11, and Are moved to the most significant 11 bits of the first input unit 11.

Here, the input alignment process in the first barrel shifter 4 'of the first input unit 11 is an ancillary execution process, and the input alignment process is decoded by the code word table 5a' of the programmable logic array 5 '. It does not affect the overall decoding execution time since it occurs simultaneously with the process of examining the data.

As described in detail, the variable-length code decoder based on the programmable logic array 5 'of the present invention uses the code length signal CL (n) to generate the first input 11 and the second input. (OR input unit) Two shifts are simultaneously executed by each of the 17 units. The CRL (n) is controlled by an adder 20 and a subtractor 19 to determine whether a new bit stream can be supplied.

Here, the execution time Tps of the decoder structure of the variable-length signal based on the parallel programmable logic array 5 'to be decoded according to the present invention is defined as follows. When a new bit stream is supplied from the input buffer, Tps = Tpm + max (Tips, Tops, Td) + Tor When a new bit stream is not supplied from the input buffer, Tps = Tpm + max (Tips, Tops, Td) where Tips, Tops Is the bit stream moving time at the first input unit 11 and the second input unit (logical sum input unit) 17, Td is the time required to determine whether a new bit stream can be supplied, and Tor is the second input unit (logical sum). This is the time required for the OR gate circuit 14 of the input unit 17 to execute the OR operation.

The decoding execution time in the present invention is defined not by the sum of Tips, Tops and Td as in the prior art, but by the longest of these execution times.

[0051]

As described above in detail, in the present invention, in the process of decoding a variable length signal based on a parallel programmable logic array, the data input to be decoded is separated into two parts, and each input part is decoded. Since the process of moving data and the process of controlling data supply to each input unit are simultaneously executed, the decoding time of compressed multimedia is shortened, the decoding time is reduced, and storage and editing in real time are performed. During data compression / decompression such as HDTV, there is an effect that a fast decoding process can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a variable-length code decoder according to an embodiment of the present invention, in which an input unit is divided to improve a decoding processing speed.

FIG. 2 is a diagram illustrating an embodiment of performing a decoding process using two divided input units according to the present invention.

FIG. 3 is a circuit diagram of a variable length code decoder based on a prior art programmable logic array.

[Explanation of symbols]

 1 'input buffer 4' first barrel shifter 5 'programmable logic array 5a' codeword table 5b 'code length table 5c' decoded word table 6 'second barrel shifter 11 first input section 12 first multiplexer 13 input register 14 logic Sum gate circuit 15 Second multiplexer 16 Output register 17 Second input unit (OR input unit) 18 Fifth register 19 Subtractor 20 Adder 21 Sixth register

Continuing on the front page (72) Inventor Park Gen-Asahi 1005 F-term (reference) No. 1305, Hanbit Apartment 130, Yueok-dong, Yuseong-gu, Daejeon, Republic of Korea 5J064 AA03 BA09 BC01 BC03 BC04 BC08 BC25 BD01

Claims (8)

[Claims] 1. A program which is connected to two separated input units to which data to be decoded is input and one of the two input units, and performs a decoding process on the data. A programmable logic array, and a subtractor and an adder connected to an output end of the programmable logic array, and a code length signal indicating the number of bits of data decoded by the programmable logic array. A process of simultaneously supplying data to the two input units and the subtractor, and moving data at the two input units based on the supplied code length signal; and using the supplied code length signal. A variable-length code decoder characterized by simultaneously executing a process of controlling input of data to be decoded to the two input units based on addition and subtraction operations in a subtractor and an adder. 2. The variable length code decoder according to claim 1, wherein each of said two input units has one barrel shifter, one multiplexer and one output latch. 3. The variable length code decoder according to claim 2, wherein one of the two input units is a logical sum input unit having a logical sum gate circuit. 4. The variable length code decoder according to claim 1, wherein the number of bits CRL (n) of the data remaining in each of the two input units is given by the following equation. When CRL (n) = CRL (n-1) -CL (n)> Lmax, CRL (n) = CRL (n-1) -CL (n), where n is a sequential number CL of data to be decoded. (n): decoded code length signal Lmax: decoded maximum code length signal 5. The variable length code decoder according to claim 4, wherein the number of bits CRL (n) of data remaining in each of the two input units is represented by the following equation. If CRL (n) = CRL (n-1) -CL (n) <Lmax, CRL (n) = CRL (n-1) -CL (n) + Lmax 6. The variable length code decoder according to claim 4, wherein the number of bits of said Lmax is 16 bits. 7. The variable length code decoder according to claim 1, wherein the entire processing time Tps is given by the following equation. If CRL (n) = CRL (n-1) -CL (n)> Lmax, then Tps = Tpm + max (Tips, Tops, Td), where Tpm: time for performing pattern matching in the programmable logic array Tips, Tops: moving time of data at each of the two input sections Td: time required to determine whether new data can be input 8. The variable length code decoder according to claim 1, wherein the entire processing time Tps is given by the following equation. If CRL (n) = CRL (n-1) -CL (n) <Lmax, then Tps = Tpm + max (Tips, Tops, Td) + Tor, where Tor: one of the two input units is a logical sum A logical sum input unit having a gate circuit, and a time required to execute a logical sum operation in the logical sum gate circuit of the logical sum input unit