KR100379006B1 - Manufacturing Method of Semiconductor Device with Improved Capacitance Using Hemispherical Particle Silicon Layer - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device with improved capacitance by responding a semi-spherical particulate silicon layer, the configuration of which deposits the doped polysilicon layer, patterning the doped polysilicon layer to the capacitor lower electrode After limiting the range of N, the capacitor of the DRAM cell of the present invention is formed by depositing a first hemispherical particulate polycrystalline silicon layer (HSG-Si) on the doped polysilicon layer. The growth of the first HSG-Si layer is stopped and then the second HSG-Si layer is grown.

According to one embodiment of the present invention, growth of the first HSG-Si layer may be stopped by cooling the deposition substrate or stopping deposition for a predetermined time and then restarting deposition to grow the second HSG-Si layer on the electrode surface. Can be.

The interruption of growth of the first layer is sufficient as long as the resumed growth is made separately from the first process, either by cooling or by delay, ie, the second HSG-Si layer grows separately.

According to another embodiment of the present invention, growth of the first layer is stopped by removing the electrode from the deposition system and performing a reetch operation. After reetching, the electrode is reintroduced into the deposition system and a second HSG-Si layer is grown on the etched surface. This textured silicon structure forms the bottom electrode of the DRAM capacitor.

Description

Manufacturing method of semiconductor device with improved capacitance using hemispherical particulate silicon layer

The present invention relates to a method of forming a structure having a large capacitance in an integrated circuit device, and more particularly, an electrode integrated on one or more rugged surfaces using a hemispherical particulate silicon layer (HSG-Si). The present invention relates to a method for manufacturing a semiconductor device in which the capacitance of the resultant electrode is improved by manufacturing the same.

Increasing the density of conventional integrated circuit devices has been partially achieved by miniaturizing structures such as wiring and transistor gates, and by reducing the space between structures that make up integrated circuit devices. Miniaturization of the circuit structure is also commonly referred to as reducing the "design rule" used in the manufacture of integrated circuit devices.

In the case of dynamic random access memory (DRAM), information is typically stored by selectively charging or discharging each capacitor in a capacitor array formed on a semiconductor substrate surface. In most cases, a single bit of binary information is stored in each capacitor by associating the discharged capacitor state to logic 0 and the charged capacitor state to logic 1. The plate surface area of the memory capacitors determines the amount of charge that can be stored in each capacitor at the normally set operating voltage of the memory, the electrode spacing that can be reliably produced, and the dielectric constant of the capacitor dielectric typically used in the capacitor. Reducing the surface area occupied by such DRAM capacitors with reduced design rules tends to reduce the surface area of the capacitor plate and the amount of charge (ie, capacitance) that can be stored in the memory capacitor.

The amount of charge stored in such a memory capacitor must be large enough to ensure reliable memory operation. In recent ultra-large integrated ("ULSI") DRAM designs, further reductions in the amount of charge stored in the DRAM memory capacitor can interfere with reliable reading of the information stored in the capacitor. In addition, because charge inevitably flows out of the memory capacitor, the DRAM needs to periodically recharge the charge stored in each capacitor in the DRAM so that the stored charge remains above a minimum detection level. As the capacitance is further reduced, recharging to the DRAM will be more frequent, which is undesirable since at least some of the DRAM is not available for reading and writing information during the recharging operation.

To meet the demand for miniaturization, employ capacitors with vertical extensions on top of the substrate surface (ie, "overlapped" capacitors) or capacitors with vertical extensions on bottom of the substrate surface (i.e., "trench" capacitors). One DRAM design is proposed. By adopting a more three-dimensional structure, the DRAM design provides a memory capacitor with greater capacitance while reducing substrate surface area. Although nested capacitors and trench capacitor designs have a complex structure that is much more difficult to manufacture, these designs have recently been successfully adopted in part. As an alternative, a structure that is less expensive, easier to fabricate, and provides increased capacitance is desirable. Moreover, it is desirable to reduce the vertical range of the storage capacitor so that a flatter device structure can be manufactured. There still remains a need to increase the capacitance of the DRAM storage capacitor while reducing the surface area occupied by the DRAM storage capacitor on the surface of the semiconductor substrate.

One technique proposed to increase the capacitance obtained at such a fixed substrate surface area is to use rugged or textured silicon as the base plate for the memory capacitor. An advantage of this technique is shown in part in FIG. 1, which is shown as a partial cross-sectional view of a DRAM having a memory capacitor with a base plate electrode made of textured silicon. The illustrated DRAM comprises a silicon substrate 10, a field oxide region 12, a source / drain regions 14 and 16, a gate electrode 18 and the field oxide region of a transfer field effect transistor (" FET ") of a memory cell. It consists of the wiring 20 formed in one kind of (12). The wiring 20 interconnects portions of the DRAM in a known manner, and the transfer FET acts as a switch during the read and write operations of the capacitor.

In such DRAMs, memory capacitors may be connected to the source / drain regions 16 of the transfer FETs by vertically extending interconnects 22 terminating in layers 24 formed of conventional polysilicon. The bumpy silicon layer 26 is formed on the top surface of the conventional polysilicon layer 24 to complete the bottom electrode of the charge storage capacitor. The thin film dielectric layer 28 also covers both the bumpy silicon layer 26 and the exposed surface of the polysilicon layer 24, and a doped polysilicon layer 30 is formed on the dielectric layer 28 to form an upper portion of the capacitor. It serves as an electrode. The use of rugged silicon in the lower electrode of the capacitor here increases the surface area of the capacitor without extending the capacitor electrode laterally, thereby increasing the capacitance at a fixed surface area.

Various techniques have been used to fabricate bumpy silicon for use in semiconductors, such as the DRAM shown in FIG. Watanabe et al., "Device Application and Structure Observation for Hemispherical-Grained Si," contains hemispherical granular polycrystalline silicon ("HSG-Si", hereinafter unevenly textured silicon by silane CVD (SiH ₄ ) by low pressure chemical vapor deposition (LPCVD). Is described).

In this specification, the maximum capacitance is obtained in the case of polysilicon (HSG-Si) deposited at a substrate temperature of 590 ° C. by maximizing the surface roughness or texture of the HSG-Si film so that the HSG-Si film can be used as a layer of a DRAM memory capacitor. Increasing or decreasing the deposition temperature of the substrate by 10 ° C above 590 ° C results in an unacceptable surface texture, and under these conditions, an undesirably flat surface that cannot provide a significantly larger capacitance electrode than conventional polysilicon is obtained. do. Capacitors fabricated using HSG-Si lower electrodes deposited on a substrate at 590 ° C. using LPCVD were fabricated using flat lower electrodes deposited at a substrate temperature of 580 ° C. or 600 ° C. (or higher). The capacitance per unit area is almost twice that of the fabricated capacitor.

Pazan et al. &Quot; Electric Characterization of Textured Interpoly Capacitors for Advanced Stacked DRAMs " describe another method for forming a rugged surface on a doped polycrystalline silicon layer. That is, an oxide film is grown on the surface of the doped polysilicon layer using a wet oxidation method at 907 ° C., and then the oxide film is etched to form an uneven surface on polycrystalline silicon.

The etching of the oxide layer grown in the polysilicon layer thus removes the oxide continuously from the polysilicon grain boundary, and at the same time, a highly oxidized reaction occurs along the grain boundaries of the doped polysilicon layer, resulting in an uneven polysilicon surface. Since the degree of surface roughness produced in this process is directly related to the size of the polysilicon particles, a film of small particles is required to obtain a desirable texture.

In Sakao et al., "A Capacitor-Over-Bit-Line (COB) Cell with a Hemisphe rical-Grain Storage Node for 64Mb DRAMs" (1990 IEDM), DRAM integrated with HSG-Si to provide increased storage capacity. A method of manufacturing a capacitor is disclosed. Sakao's capacitor manufacturing process involves the following steps. That is, a source, a drain, and a gate of the transfer FET are formed, and then an oxide layer is formed on the gate and the word line. Contact vias are opened to the drain of the transfer FET and vertical interconnectors extend from the drain to the oxide layer surface.

Conventional polysilicon layers are deposited by LPCVD at 600 ° C. in contact with the vertical interconnects. Conventional polysilicon layers are patterned by lithography or reactive ion etching to form core storage nodes that are connected to the drain of the transfer FET through vertical interconnects.

The hemispherical particulate polycrystalline silicon is formed on the surface of the core storage node by LPCVD deposition using silane diluted with helium at a pressure of 1 Torr and a substrate temperature of 550 ° C. The deposited HSG-Si has a particle size of 80 nm and the layer has a thickness of 80 nm or more that exceeds the thickness of conventional polysilicon of the core storage node. HSG-SI is then reetched by reactive ion etching using HBr as an etching gas to remove HSG-Si from the surface of the oxide layer adjacent to the core storage node.

Reetching also removes HSG-Si from the surface of the storage node to reconstruct the surface texture of the original HSG-Si on the conventional polysilicon surface in the core storage node. Therefore, the lower electrode of the DRAM capacitor by Sakao is a conventional polysilicon having substantially the same surface structure (texture, roughness) as HSG-Si having a printing size of 80 nm.

The use of HSG-Si at the bottom electrode of a DRAM capacitor succeeded in nearly doubling the capacitance of the DRAM capacitor, but the capacitance using HSG-Si is no longer improved. One factor of doubled capacity is difficult to justify the increased complexity of maintaining the precise deposition conditions needed to form HSG-Si.

Accordingly, it is an object of the present invention to provide an electrode integrated with one or more uneven surfaces while providing increased capacitance using an HSG-Si layer during the process of manufacturing the electrode.

1 is a partial cross-sectional view of a DRAM using a memory capacitor having a lower electrode integrated into a semi-spherical particulate polycrystalline silicon layer;

2 is a cross-sectional view showing a manufacturing process step of a capacitor electrode according to the prior art,

3 is a cross-sectional view showing a manufacturing process step of a capacitor electrode according to the present invention;

4 is a sectional view showing another embodiment of the process shown in FIG. 3, and

5 is a cross-sectional view showing another embodiment of the process shown in FIG. 3.

According to one aspect of the invention,

Forming a doped polysilicon layer on the silicon substrate;

Depositing a first semispherical particulate silicon layer on the polysilicon layer;

Stopping deposition of a first semi-spherical particulate silicon layer on the polysilicon layer; And

Depositing a second hemispherical particulate silicon layer on the portion where the first hemispherical particulate silicon layer is formed such that independent particles of hemispherical particulate silicon are formed on the first layer particles of the hemispherical particulate silicon; Provided is a method of manufacturing a semiconductor device having improved capacitance using a semi-spherical particulate silicon layer comprising a.

According to the second aspect of the present invention,

Forming a deposited substrate containing silicon;

Depositing a first semi-spherical particulate silicon layer on the deposition substrate;

Stopping deposition of a first hemispherical particulate silicon layer on the deposition substrate;

Depositing a second semispherical particulate silicon layer on the portion where the first semispherical particulate silicon layer is formed such that independent particles of the semispherical particulate silicon are formed on the first layer particles of the semispherical particulate silicon;

Patterning the deposited substrate;

Forming a dielectric layer on the second hemispherical particulate silicon layer; And

A method of manufacturing a semiconductor device having improved capacitance using a hemispherical particulate silicon layer comprising the step of depositing a conductive layer on the dielectric layer is provided.

Hereinafter, the present invention will be described in more detail.

In the present invention, a first hemispherical particulate polycrystalline silicon layer (HSG-Si) is formed on the surface of the polysilicon layer. After the growth of the first HSG-Si layer is stopped, the second HSG-Si layer grows.

In one embodiment of the present invention, the growth of the first HSG-Si layer by cooling the deposition substrate or by stopping the deposition process for a predetermined time and then restarting the deposition process to form a second HSG-Si layer on the electrode surface. Stop. If this resumed growth is initiated independently of the first process, i.e., if the second HSG-Si layer grows independently, growth of the first layer can be sufficiently stopped by cooling or by delay.

This independent growth of the second layer means starting the growth of the crystalline of the second HSG-Si layer from the new nucleation site rather than continuing to grow the existing crystalline. Therefore, at least some of the particles of the second HSC-Si layer grow as HSG-Si particles which are distinguished from the particle surface of the first HSG-Si layer.

In another embodiment of the present invention, growth of the first HSG-Si layer can be stopped by growing an amorphous silicon ultrathin layer on the particle surface of the first HSG-Si layer. Subsequently, particles of the second HSG-Si layer grow from the surface of the amorphous silicon thin layer.

According to another embodiment of the present invention, a capacitor electrode is prepared by growing a first HSG-Si layer on a doped polysilicon layer. The growth of the first HSG-Si layer may be stopped by stopping the deposition process or preferably by removing the electrode from the deposition system and performing a reetch process. Following this reetching operation, the electrode can be reintroduced into the deposition system, with the second HSG-Si layer growing on the etched surface. For example, it is possible to reetch the first HSG-Si layer in such a way as to essentially reconstruct the surface morphology of the first HSG-Si layer into the doped polysilicon layer.

Alternatively, the undoped first HSG-Si layer can be used as a mask for selectively etching the doped polysilicon base layer. Suitable etching systems include those that supply chlorine ions into the corrosion solution for the purpose of exploiting the selectivity of the chlorine etching system. The system etches doped polysilicon at a faster rate than undoped polysilicon.

When such an etch system is applied to etch the undoped first HSG-Si layer covering the doped polysilicon layer, the exposed portions of the doped polysilicon base layer etch very rapidly while the HSG-Si layer is etched slowly. Therefore, if the etching process continues until all HSG-Si is removed, the surface of the doped polysilicon layer will have an irregular arrangement of cones and truncated cones of a height greater than the particle size of the originally deposited HSG-Si layer.

Since the first HSG-Si layer is removed prior to the growth of the second HSG-Si layer, the continuous growth of the second HSG-Si layer on the surface of the doped rugged polysilicon layer is naturally equivalent to the first HSG-Si layer growth. Is distinct. As with other embodiments of the present invention, the growth of the second HSG-Si layer on the etch surface of such embodiments further increases the capacitor electrode surface area.

2 to 4 are diagrams showing a preferred embodiment of the present invention. The drawings are inevitably schematically and exaggerated in various respects to facilitate an easier understanding of the present invention. 2-4 show a portion of the lower electrode structure of a capacitor that can replace the lower electrode of FIG. 1 composed of a polysilicon lower layer 24 and an HSG-Si upper layer 26.

As shown in FIG. 2, a conventional polysilicon layer 40 is deposited on a silicon oxide layer (not shown) deposited on the silicon substrate by low pressure chemical vapor deposition (LPCVD) at 620 ° C. from silane (SiH ₄ ). Is calm.

The conventional polysilicon layer 40 is preferably doped in situ during the deposition process by known ion implantation and annealing processes, or thermal diffusion processes. For example, the polysilicon layer 40 may be highly doped N-type by rapid thermal annealing at about 1,000 to 1,100 ° C. for about 10 to 30 seconds following implantation of P ions. The conventional polysilicon layer 40 forming the core of the lower electrode is formed through a photomask process and an etching process. The first HSG-Si layer is to be deposited on the conventional polysilicon layer 40.

The HSG-Si growth process as described above is preferably initiated on the clean silicon surface by removing the natural oxide from the surface of the polysilicon layer 40 prior to depositing the HSG-Si. If the growth of the HSG-Si layer is initiated immediately after the formation of the silicon base layer, or if the surface of the silicon base layer is maintained in a sufficient vacuum to prevent the growth of oxides, a separate washing step is unnecessary. More specifically, it is expected that there will be a predetermined time interval between the growth of the silicon base layer and the start of growth of the HSG-Si layer. Alternatively, when the polysilicon layer is doped by ion implantation and annealing or by a heat diffusion process, the oxide layer grows on the surface of the polysilicon layer.

Therefore, the surface of the silicon base layer is preferably washed before the growth of HSG-Si is started. Natural oxides can be removed from the polysilicon surface by a variety of techniques including HF immersion, spin-etching with HF, steam HF cleaning or H ₂ plasma cleaning.

The surface of the silicon base layer is preferably hydrogenated as a result of the cleaning process, since the hydrogenated surface serves to protect the polysilicon surface from reoxidation. Each cleaning technique described above will perform the desired hydrogenation of the polysilicon surface.

After washing, an HSG-Si layer 42 is formed on the surface of the conventional polysilicon layer 40. The layer may be formed by any known methods, the method comprising depositing HSG-Si by low pressure chemical vapor deposition from a silane source gas on a substrate maintained at a temperature of about 570 to about 585 ° C. . The resulting structure is shown in FIG. 2 and has an irregular surface of HSG-Si.

Because of the random nature of nucleation for HSG-Si growth, the doped polysilicon base layer 40 may be exposed at certain sparse sites in the HSG-Si layer, indicated by reference numeral 44 in FIG. 2. The growth of the HSG-Si layer 42 on the surface of the polysilicon layer 40 was observed to have an increased capacitance of about 1.8 times the capacitance provided by the flat surface of the polysilicon layer 40.

Perhaps it is believed that due to the loss of surface area the crystalline of the first HSG-Si layer grows large enough to grow adjacent crystalline surfaces together, so it is difficult to increase the capacitance anymore through the growth of the HSG-Si layer.

Thus, according to a preferred embodiment of the present invention, the capacitance is reduced by stopping the growth of the first HSG-Si layer and then resuming the growth of the second HSG-Si layer growing in a manner similar to that of the first HSG-Si layer. Can be increased. Growth of the second HSG-Si layer is initiated in a manner independent of the growth of the first HSG-Si layer. Therefore, the growth of the second HSG-Si layer generally contributes little to further growing the crystalline of the first HSG-Si layer.

Rather, growth of the second HSG-Si layer causes new particles to grow on the electrode surface including the particle surface of the first HSG-Si layer. In FIG. 3 this second HSG-Si layer shows the formation of separate HSG-Si particles 46.

The second HSG-Si layer is also nucleated for particle 48 growth at a new location on the polysilicon layer 40 surface. Most preferably, the particles grown in the second HSG-Si layer are smaller than the particles of the first layer, which may be performed by growing the second layer in a shorter time than the time required for the growth of the first layer. By repeating the growth stop process of the HSG-Si layer and the resumption of growth of the HSG-Si layer several times, the third and fourth independent continuous layers may be grown on the existing second HSG-Si layer.

In carrying out the present invention, rather than continuously growing the HSC-Si layer, the deposition of the first HSG-Si layer is interrupted by a specific method so that the capacitor electrode is continuously present in the HSG-Si deposition environment. It is important to contribute to the growth of two new crystalline layers. Many other techniques can be used to stop the growth of the first HSG-Si layer. For example, if continuous reintroduction of the reactor for sufficient time under deposition conditions does not resume growth at the new nucleation site, the influx of the reactor (eg SiH ₄ ) into the deposition chamber is stopped and the capacitor electrode is placed in the deposition chamber. May remain. This can happen, for example, for 30 minutes.

Conventional low pressure chemical vapor deposition systems operate under a pressure of about 10 ^-4 Torr, which allows contaminants to collect on the surface of the already deposited HSG-Si particles to prevent further growth of the particles upon resumption of the growth process. Enough to do Instead of waiting for some time, cooling the capacitor electrodes and reheating them to the HSG-Si deposition temperature can cause a similar process.

Another method for stopping growth of the first HSG-Si layer is to deposit a layer of interruption material of several thicknesses on the particle surface of the first HSG-Si layer so that the second HSG-Si layer grows on the stop material layer. To do that. The most easily produced and suitable stopper layer is an amorphous silicon layer.

A few milliseconds to about 200 milliseconds of amorphous silicon layer can be deposited in the same low pressure chemical vapor deposition system used for the deposition of HSG-Si. In general, reducing the electrode temperature of a capacitor below 550 ° C. can result in the deposition of amorphous silicon on the electrode.

Preferably, one or more additional HSG-Si layers are grown on the surface of the capacitor electrode by suitably stopping the growth of the first HSG-Si layer and then forming smaller particles in each successive layer. 4 shows an amorphous silicon thin film 50 formed on the exposed portions of the particles 42 and the polysilicon layer 40 of the first HSG-Si layer.

Subsequently, the first composition includes particles 52 formed on the particulate amorphous silicon layer 50 of the first HSG-Si layer 42 and particles 54 formed on the amorphous silicon layer 50 on the polysilicon layer 40. 2 form an HSG-Si layer. All bumpy surfaces are formed on the capacitor electrode and then the HSG-Si layer is doped in situ during the deposition process by known ion implantation and annealing from the surface of the HSG-Si layer or the polysilicon base layer 40 or by a thermal diffusion process. do. If the polysilicon layer 40 is not doped in advance, the polysilicon layer 40 may be doped by ion implantation, for example.

In addition, when the amorphous silicon layer 50 is integrated into the structure, the HSG-Si layer is doped and at the same time the amorphous silicon layer is doped. If not already patterned, the process of patterning the electrodes, forming a dielectric layer on the surface of the capacitor lower electrode, and forming the capacitor upper electrode is continued. Further discussions relating to the process are described below, and other embodiments of the invention are described first.

According to another embodiment of the present invention, as a step of stopping the growth of the first HSG-Si layer, the first HSG-Si layer is deposited and then the surface of the HSC-Si / polysilicon structure as shown in FIG. 2 is etched. It includes a process to make. The etching process is preferably anisotropic and is selectively / non-selectively performed between the HSG-Si particles 42 and the polysilicon layer 40. In the case where the etching process is non-selective, the etching process simply reconstructs the shape of the HSG-Si particles 42 in the polysilicon layer 40. As another alternative, the HSG-Si particles 42 are undoped and doped with the polysilicon layer 40, which can be used to selectively etch the structure of FIG. In this process, the HSG-Si particles 42 serve as a mask for the etching process, and the exposed portion of the polysilicon layer 40 is etched faster than the HSG-Si particles. The etching process forms an electrode surface having a higher surface roughness or integrated circuit than the HSG-Si layer on the polysilicon layer as shown in FIG. 2.

For a suitable etching environment for the selective etching process, reactive ion corrosion solutions such as P5000, a self-reinforced reactive ion corrosion solution manufactured by Applied Materials, can be used. In this case, the etching gas may contain Cl ₂ and HBr in a Cl ₂ / HBr ratio of 70 sccm / 30 sccm at a total pressure of 60 mTorr and an input energy level of 300 W. These conditions are exemplary and other conditions may also be appropriately applied. The selectivity ratio of the etch rate of the doped polysilicon to the etch rate of the undoped HSG-Si is about 2: 1 under the above conditions.

It is desirable to continue the etching process to completely etch the HSG-Si particles 42 to form a raised surface 60 and a recessed surface 62 on the surface of the doped polysilicon layer 40 (FIG. 5). Do. An advantage of completely removing the HSG-Si layer is that it does not need to undergo an additional doping step to make the HSG-Si layer conductive.

In any of the above cases, the second HSG-Si layer 64 is grown on the etched surface of the polysilicon layer 40. The HSG-Si layer 64 is then doped. If not previously patterned, the electrode is patterned, a dielectric layer is formed on the surface of the capacitor lower electrode, and the capacitor upper electrode is continued.

3 to 5, when the surface of the structure is covered with a thin film dielectric layer and a conductive material upper layer is deposited on the dielectric layer, a high capacitance may be coupled between the rugged polysilicon layer and the conductive material upper layer. .

It is preferable that a highly doped N-type second polysilicon layer is formed to form a capacitor structure as shown in FIG. The structure preferably uses a thin dielectric layer compared to the rugged scale of the surface. The layer having a surface structure of about 100 nm in size preferably uses a dielectric layer having a thickness of less than about 8 nm.

It is also desirable to form the dielectric layer with a material having a high dielectric constant. For example, an appropriate dielectric layer can be formed by depositing a silicon nitride layer on the surface of the HSG-Si layer by chemical vapor deposition (CVD) and then growing an oxide thin layer on the surface of the silicon nitride layer.

Sometimes a "NO" layer is formed on top of an oxide layer covering the surface of a rugged polysilicon layer, such as a natural oxide layer, so the dielectric film actually formed may have an "ONO" structure. According to Rosato et al., "Ultra-High Capacitance Nitride Films Utilizing Surface passivation on Rugged Polysilicon" (J. Electrochem, Soc. Vol 139, No. 12, pp 3678-82, Dec. 1992), An "ONO" structure can be formed. Rosato et al., Which describe techniques for forming ONO dielectric layers on rugged polysilicon and passivation of natural oxide surfaces prior to deposition of CVD nitride layers, are incorporated herein by reference.

As another alternative, a thin layer of tantalum pentoxide or other high dielectric constant material may serve as the dielectric layer and capacitor dielectric covering the uneven polysilicon surface.

In the present specification, the method for manufacturing the bumpy polysilicon is specifically described in connection with the formation of a capacitor as shown in the DRAM structure of FIG. 1, but the bumpy polysilicon according to the present invention may be used in other structures.

For example, bumpy silicon can also be used in other capacitor structures, such as fins of various stack capacitor structures. In addition, the bumpy silicon layer according to an embodiment of the present invention can be used for floating gate surfaces in EEFROM or flash memory.

That is, the use of the ONO dielectric layer and the rugged polysilicon surface between the polysilicon floating gate formed on the ONO dielectric layer and the polysite control gate improves the coupling force between the floating gate and the control gate as compared to the conventional flash memory device structure. .

Thus, while the invention has been described in connection with specific preferred embodiments, it is apparent that the invention is not limited to the specific embodiments described above.

Claims (16)

Forming a doped polysilicon layer on the silicon substrate; Depositing a first semispherical particulate silicon layer on the polysilicon layer; Stopping deposition of a first semi-spherical particulate silicon layer on the polysilicon layer; And A portion in which no hemispherical particulate silicon layer is formed at all on the polysilicon layer by resuming deposition, a portion in which only the first hemispherical particulate silicon layer is formed in the form of particles, a portion in which only the second hemispherical particulate silicon layer is formed in the form of particles, and The first hemispherical particulate silicon layer and the second hemispherical particulate silicon layer all have a portion formed by overlapping in sequence in the form of particles. Forming independent particles of the second hemispherical particulate silicon layer on top of the first hemispherical particulate silicon layer and on the polysilicon layer in which the first hemispherical particulate silicon layer is not formed; A method of manufacturing a semiconductor device having improved capacitance by using a semi-spherical particulate silicon layer comprising a. The method of claim 1, wherein the first hemispherical particulate silicon layer is grown on the polysilicon layer by chemical vapor deposition. The method of claim 2, wherein the second hemispherical particulate silicon layer is formed by chemical vapor deposition. The semiconductor device according to claim 1, wherein the stopping of the deposition of the first hemispherical particulate silicon layer is performed by cooling the polysilicon layer. Manufacturing method. The semiconductor of claim 1, wherein the stopping of the deposition of the first hemispherical particulate silicon layer is performed by stopping the deposition process during the first period. Method of manufacturing the device. The method of claim 2, wherein the deposition of the second hemispherical particulate silicon layer is performed by resuming chemical vapor deposition of the hemispherical particulate silicon layer to provide a growth process separately from the chemical vapor deposition of the first hemispherical particulate silicon layer. A method for manufacturing a semiconductor device having improved capacitance by using a semispherical particulate silicon layer. The semiconductor of claim 1, wherein the first and second hemispherical particulate silicon layers are both grown by low pressure chemical vapor deposition at a temperature of less than 600 ° C. 6. Method of manufacturing the device. Forming a deposited substrate containing silicon; Depositing a first semi-spherical particulate silicon layer on the deposition substrate; Stopping deposition of a first hemispherical particulate silicon layer on the deposition substrate; A portion in which no hemispherical particulate silicon layer is formed at all on the deposited substrate by resuming deposition, a portion in which only the first hemispherical particulate silicon layer is formed in the form of particles, a portion in which only the second hemispherical particulate silicon layer is in the form of particles, and The first hemispherical particulate silicon layer and the second hemispherical particulate silicon layer all have a portion formed by overlapping in sequence in the form of particles. Forming independent particles of the second hemispherical particulate silicon layer on the deposited substrate on which the upper portion of the first hemispherical particulate silicon layer and the first hemispherical particulate silicon layer are not formed; Patterning the deposited substrate; Forming a dielectric layer on the second hemispherical particulate silicon layer; And Depositing a conductive layer on the dielectric layer; a method of manufacturing a semiconductor device having improved capacitance using a semi-spherical particulate silicon layer comprising a. 10. The method of claim 9, wherein stopping the deposition of the first hemispherical particulate silicon layer is performed by etching the first hemispherical particulate silicon layer prior to depositing the second hemispherical particulate silicon layer. A method of manufacturing a semiconductor device having improved capacitance by using a semispherical particulate silicon layer. 10. The method of claim 9, wherein the etching step is continued until the first hemispherical particulate silicon layer is removed. 10. The method of claim 8, wherein the deposited substrate contains doped silicon and has a first hemispherical particulate shape using a selective etching process that preferentially etches the doped silicon at a faster rate than the selective etching process of etching the undoped silicon. Further comprising etching the silicon layer, 12. A method of manufacturing a semiconductor device with improved capacitance by using the semispherical particulate silicon layer, wherein the second semispherical particulate silicon layer is deposited successively in the etching step. 12. The semiconductor device according to claim 11, wherein the etching step etches the deposited substrate to a depth at least equal to the thickness of the first hemispherical particulate silicon layer. Manufacturing method. The method of claim 8, further comprising forming a dielectric layer on the second hemispherical particulate silicon layer, followed by forming a doped polysilicon layer on the dielectric layer; And And patterning the doped polysilicon layer to provide an upper electrode of the capacitor. The method of manufacturing a semiconductor device with improved capacitance using a semi-spherical particulate silicon layer, characterized in that it further comprises. 15. The method of claim 13, wherein the forming of the doped polysilicon layer comprises etching the doped polysilicon to define a range of electrode structures on the side. Manufacturing method of semiconductor device having improved capacitance. The semiconductor device of claim 8, wherein both of the first and second hemispherical particulate silicon layers are deposited at a temperature of about 570 ° C. to about 585 ° C. 10. Way. The method of claim 8, wherein further stopping the deposition of the first hemispherical particulate silicon layer deposits an amorphous silicon layer on the surface of the first hemispherical particulate silicon layer and another second half on the amorphous silicon layer. A method for manufacturing a semiconductor device with improved capacitance using a semi-spherical particulate silicon layer, which is performed by depositing a spherical particulate silicon layer.