KR100378095B1 - Substrate and fabricating method and semiconductor package using the same - Google Patents

Substrate and fabricating method and semiconductor package using the same Download PDF

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Publication number
KR100378095B1
KR100378095B1 KR1020010039442A KR20010039442A KR100378095B1 KR 100378095 B1 KR100378095 B1 KR 100378095B1 KR 1020010039442 A KR1020010039442 A KR 1020010039442A KR 20010039442 A KR20010039442 A KR 20010039442A KR 100378095 B1 KR100378095 B1 KR 100378095B1
Authority
KR
South Korea
Prior art keywords
plane
same
insulator
circuit patterns
substrate
Prior art date
Application number
KR1020010039442A
Other languages
Korean (ko)
Inventor
Sang Ho Lee
Jun Young Yang
Original Assignee
Amkor Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amkor Technology Inc filed Critical Amkor Technology Inc
Priority to KR1020010039442A priority Critical patent/KR100378095B1/en
Application granted granted Critical
Publication of KR100378095B1 publication Critical patent/KR100378095B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE: A substrate and a fabricating method and a semiconductor package using the same are provided to enhance the quality of circuit patterns by plating sequentially plural metallic materials. CONSTITUTION: A plurality of circuit patterns(2) have the first plane(2a) and the second plane(2b). The circuit patterns(2) is formed by plating sequentially Au, Ni, Cu, and Ni on the first plane(2a) or Au, Cu, Ni, and Au on the first plane(2a). An insulator(4) includes the first plane(4a) and the second plane(4b). The second plane(2b) and a side are covered with the insulator(4). The first plane(4a) of the insulator(4) is located on the same plane as the first plane(2a) of the circuit patterns(2). The second plane(4b) of the insulator(4) is located under the second plane(2b) of the circuit patterns(2). A plurality of openings(5) are formed on the second plane(4b) of the insulator(4).
KR1020010039442A 2001-07-03 2001-07-03 Substrate and fabricating method and semiconductor package using the same KR100378095B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010039442A KR100378095B1 (en) 2001-07-03 2001-07-03 Substrate and fabricating method and semiconductor package using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010039442A KR100378095B1 (en) 2001-07-03 2001-07-03 Substrate and fabricating method and semiconductor package using the same

Publications (1)

Publication Number Publication Date
KR100378095B1 true KR100378095B1 (en) 2003-03-29

Family

ID=37417015

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010039442A KR100378095B1 (en) 2001-07-03 2001-07-03 Substrate and fabricating method and semiconductor package using the same

Country Status (1)

Country Link
KR (1) KR100378095B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10643937B2 (en) 2018-05-08 2020-05-05 Advanced Semiconductor Engineering, Inc. Wiring structure, electronic device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10643937B2 (en) 2018-05-08 2020-05-05 Advanced Semiconductor Engineering, Inc. Wiring structure, electronic device and method for manufacturing the same
US11031326B2 (en) 2018-05-08 2021-06-08 Advanced Semiconductor Engineering, Inc. Wiring structure, electronic device and method for manufacturing the same

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