KR100377161B1 - Mask rom and method for fabricating the same - Google Patents
Mask rom and method for fabricating the same Download PDFInfo
- Publication number
- KR100377161B1 KR100377161B1 KR10-2000-0086637A KR20000086637A KR100377161B1 KR 100377161 B1 KR100377161 B1 KR 100377161B1 KR 20000086637 A KR20000086637 A KR 20000086637A KR 100377161 B1 KR100377161 B1 KR 100377161B1
- Authority
- KR
- South Korea
- Prior art keywords
- junction
- mask rom
- source
- drain
- channel region
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 9
- 238000005468 ion implantation Methods 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 3
- -1 boron ions Chemical class 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 241000047703 Nonion Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
- H10B20/387—Source region or drain region doping programmed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 숏채널길이를 갖는 낸드형 마스크롬에 있어서 숏채널 효과, 핫ㄱ캐리어 효과를 개선시키도록 한 마스크롬 및 그 제조 방법에 관한 것으로, 이를 위한 본 발명의 마스크롬은 반도체기판, 상기 반도체기판상의 게이트산화막, 상기 게이트산화막상의 게이트전극, 상기 게이트전극 하부의 상기 반도체기판내에 일측으로 도핑농도가 기울어진 채널영역, 상기 채널영역의 타측에 접하는 p+ 접합, 및 상기 채널영역에 의해 서로 분리되되 상기 p+ 접합에 의해 비대칭 구조를 갖는 두 개의 n+ 접합을 포함하여 구성된다.The present invention relates to a mask rom and a method of manufacturing the same for improving a short channel effect and a hot carrier effect in a NAND type mask rom having a short channel length. It is separated from each other by a gate oxide film on a substrate, a gate electrode on the gate oxide film, a channel region having a doping concentration inclined to one side in the semiconductor substrate under the gate electrode, a p + junction in contact with the other side of the channel region, and the channel region. The p + junction comprises two n + junctions having an asymmetric structure.
Description
본 발명은 비휘발성 메모리 소자의 제조 방법에 관한 것으로, 특히 숏채널효과를 개선시키도록 한 마스크롬(Mask ROM)의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly to a method of manufacturing a mask ROM to improve the short channel effect.
통상적으로 마스크롬의 셀 구조는 NOR형과 NAND형으로 크게 분류되며, 일반적으로, 고집적 마스크롬에서는 NAND형 메모리 셀 구조를 채택하고 있다.In general, a mask ROM cell structure is largely classified into a NOR type and a NAND type. In general, a highly integrated mask ROM employs a NAND type memory cell structure.
도 1은 종래 기술의 NAND형 마스크롬의 셀 어레이를 도시한 등가 회로도로서, NAND형 마스크롬 셀은 워드라인(WL)에 게이트가 연결된 복수개의 셀 트랜지스터가 직렬로 연결되어 각각 제 1 스트링(S1) 및 제 2 스트링(S2)을 이루고, 제 1 및 제 2 스트링(S1, S2)이 비트라인 콘택을 통해 비트라인(BL)에 병렬로 연결되어 메모리 셀 어레이의 기본 단위를 이루고 있다.1 is an equivalent circuit diagram illustrating a cell array of a NAND type mask ROM according to the related art, in which a plurality of cell transistors having gates connected to a word line WL are connected in series to each other to form a first string S1. ) And the second string S2, and the first and second strings S1 and S2 are connected in parallel to the bit line BL through bit line contacts to form a basic unit of the memory cell array.
이 때, 하나의 스트링 내에는 다수의 증가형 트랜지스터(Enhancement Transistor)들과 공핍형 트랜지스터(Depletion Transistor)들이 불순물접합, 즉 N+ 소스/드레인 접합을 통하여 직렬 접속된 구조를 가지며, 비트라인에 접속된 트랜지스터와 이웃한 트랜지스터는 워드라인(WL)을 선택하기 위한 두 개의 워드라인선택라인(WL선택1, WL선택2)이 게이트에 접속되고, 나머지 트랜지스터들은 롬코드(ROM code) 부분이다.At this time, in one string, a plurality of enhancement transistors and depletion transistors have a structure connected in series through an impurity junction, that is, an N + source / drain junction, and connected to a bit line. Two word line select lines WL select 1 and WL select 2 for selecting a word line WL are connected to a gate of a transistor adjacent to the transistor, and the other transistors are a ROM code part.
도면에 도시되지 않았지만, 두 개의 스트링 선택 트랜지스터를 구비하여 제 1 스트링 및 제 2 스트링을 선택적으로 선택할 수 있다. 스트링 선택 트랜지스터는 이온주입 공정을 통해 공핍형 트랜지스터와 증가형 트랜지스터로 구분되고, 1개의 비트라인으로 2개의 스트링을 제어할 수 있다.Although not shown in the figure, two string selection transistors may be provided to selectively select the first string and the second string. The string select transistor is divided into a depletion transistor and an increment transistor through an ion implantation process, and two strings can be controlled by one bit line.
상술한 NAND형 마스크-롬에 있어서, 셀의 데이터 코딩(Data Coding)은 셀트랜지스터의 게이트 형성후 소스/드레인에 보론(B)이나 인(P)을 이온주입하므로써 이루어지는 AGP(After Gate Program) 공정에 의해 실시된다.In the above-described NAND mask-ROM, data coding of a cell is performed after ion gate implantation of boron (B) or phosphorus (P) into a source / drain after gate formation of the cell transistor. Is carried out by.
자세히 설명하면, 감광막패턴을 이용하여 노출된 셀트랜지스터에 이루어지는 불순물의 이온주입은 셀랜지스터의 게이트를 통과하여 채널 영역의 불순물 성질을 결정하므로써 공핍형 트랜지스터 또는 증가형 트랜지스터를 형성한다. 즉, 이온주입된 트랜지스터는 공핍형 트랜지스터이고, 이온주입되지 않은 트랜지스터는 증가형 트랜지스터이다. 이러한, 트랜지스터들을 사용하여 '0', '1'의 데이터를 결정한다.In detail, the ion implantation of impurities in the cell transistor exposed using the photosensitive film pattern passes through the gate of the cell transistor to determine the impurity properties of the channel region, thereby forming a depletion transistor or an incremental transistor. That is, the ion implanted transistor is a depletion transistor, and the non-ion implanted transistor is an incremental transistor. These transistors are used to determine the data of '0' and '1'.
도 2는 종래기술에 따른 낸드형 마스크롬의 셀 구조를 도시한 단면도로서, 반도체기판(11)상에 게이트산화막(12)이 형성되고, 게이트산화막(12)상에 다수의 게이트전극(워드라인)(12)이 형성되며, 게이트전극(12) 하부에는 소스/드레인(14)이 형성되고, 층간절연막(15)을 식각하여 형성된 콘택에 비트라인(16)이 소스/드레인(14) 중 어느 하나와 접속된다.2 is a cross-sectional view illustrating a cell structure of a NAND mask ROM according to the prior art, in which a gate oxide film 12 is formed on a semiconductor substrate 11, and a plurality of gate electrodes (word lines) are formed on the gate oxide film 12. 12 is formed, a source / drain 14 is formed under the gate electrode 12, and a bit line 16 is formed at any of the source / drain 14 in a contact formed by etching the interlayer insulating layer 15. Is connected with one.
그러나, 특성면에서는 이러한 구조는 미세화되면서 핫캐리어 효과(Hot carrier effect), 숏채널 효과(Short channel effect)에 취약하고 특히 소스/드레인간의 직렬저항이 커 전류구동력이 저하되는 문제점이 있다.However, in terms of characteristics, such a structure is miniaturized, which is vulnerable to a hot carrier effect and a short channel effect. In particular, the series resistance between the source and the drain is large, resulting in a decrease in current driving force.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 소스/드레인 접합간의 직렬저항 증가에 따른 전류구동력 저하를 방지하는데 적합한 마스크롬 및 그의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a mask rom and a manufacturing method thereof suitable for preventing the current driving force from being decreased due to the increase in series resistance between the source and drain junctions.
도 1은 통상적인 낸드형 마스크롬 셀 어레이의 회로도,1 is a circuit diagram of a conventional NAND mask ROM cell array;
도 2는 종래기술에 따른 마스크롬의 소자 단면도,2 is a cross-sectional view of an element of a mask rom according to the prior art;
도 3은 본 발명의 실시예에 따른 마스크롬의 소자 단면도,3 is a cross-sectional view of an element of a mask rom according to an embodiment of the present invention;
도 4a 내지 도 4c는 본 발명의 실시예에 따른 마스크롬의 제조 방법을 도시한 도면.4A to 4C illustrate a method of manufacturing a mask rom according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 31a : 채널영역31 semiconductor substrate 31a channel region
32 : 게이트산화막 33 : 게이트전극32: gate oxide film 33: gate electrode
34a : n+ 소스접합 34b : n+ 드레인접합34a: n + source junction 34b: n + drain junction
35a, 35b : p+ 접합35a, 35b: p + junction
상기의 목적을 달성하기 위한 본 발명의 마스크롬은 반도체기판, 상기 반도체기판상의 게이트산화막, 상기 게이트산화막상의 게이트전극, 상기 게이트전극 하부의 상기 반도체기판내에 일측으로 도핑농도가 기울어진 채널영역, 상기 채널영역의 타측에 접하는 p+ 접합, 및 상기 채널영역에 의해 서로 분리되되 상기 p+ 접합에 의해 비대칭 구조를 갖는 두 개의 n+ 접합을 포함하여 구성됨을 특징으로 한다.According to an embodiment of the present disclosure, a mask region includes a semiconductor substrate, a gate oxide film on the semiconductor substrate, a gate electrode on the gate oxide film, a channel region in which a doping concentration is inclined toward one side in the semiconductor substrate below the gate electrode, and P + junctions in contact with the other side of the channel region, and two n + junctions separated from each other by the channel region but having an asymmetric structure by the p + junction.
본 발명의 마스크롬의 제조 방법은 반도체기판상에 게이트산화막, 게이트전극을 순차적으로 형성하는 단계, 상기 반도체기판에 n형 불순물을 틸트 이온주입하여 소스/드레인접합을 형성하는 단계, 및 상기 소스접합에 p형 불순물을 틸트 주입하여 비대칭 소스/드레인 접합을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of manufacturing a mask rom of the present invention, the method includes sequentially forming a gate oxide film and a gate electrode on a semiconductor substrate, forming a source / drain junction by tilting n-type impurities into the semiconductor substrate, and forming the source / drain junction. And tilting the p-type impurity into the asymmetric source / drain junction.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3은 본 발명의 실시예에 따른 마스크롬의 구조 단면도로서, 반도체기판(31) 상의 소정 부분에 게이트산화막(32)이 형성되고, 게이트산화막(32)상에 게이트전극(33)이 형성되며, 게이트전극(33) 하부의 반도체기판(31)에 소스측에서 드레인측으로 기울어진 도핑농도를 갖는 채널영역(31a), 채널영역(31a)에 의해 비대칭을 이루는 n+ 소스접합(34a) 및 n+ 드레인접합(34b)이 형성된다. 그리고, n+ 소스접합(34a)에만 보론이온이 틸트 이온주입된 p+ 접합(35a, 35b)이 각각 형성된다. 여기서, n+ 드레인접합(34b)에 접하는 p+ 접합(35b)은 이웃한 트랜지스터의 소스접합에 포함된다.3 is a cross-sectional view of a structure of a mask rom according to an embodiment of the present invention, in which a gate oxide film 32 is formed on a predetermined portion on a semiconductor substrate 31, and a gate electrode 33 is formed on the gate oxide film 32. The channel region 31a having the doping concentration inclined from the source side to the drain side on the semiconductor substrate 31 under the gate electrode 33, the n + source junction 34a and the n + drain asymmetrically by the channel region 31a. The junction 34b is formed. In addition, p + junctions 35a and 35b in which boron ions are tilt-implanted only in n + source junction 34a are formed, respectively. Here, the p + junction 35b in contact with the n + drain junction 34b is included in the source junction of the neighboring transistors.
이와 같이, 트랜지스터를 제조하면, 마스크롬의 각 트랜지스터의 소스접합과 드레인접합을 비대칭으로 형성할 수 있다.In this way, when the transistor is manufactured, the source junction and the drain junction of each transistor of the mask rom can be formed asymmetrically.
도 4a 내지 도 4c는 본 발명의 실시예에 따른 마스크롬의 제조 방법을 도시한 도면이다.4A to 4C illustrate a method of manufacturing a mask rom according to an embodiment of the present invention.
도 4a에 도시된 바와 같이, 반도체기판(31)상에 게이트산화막(32), 게이트전극(33)을 순차적으로 형성한다. 이 때, 도면에 도시되지 않았지만, 소자간 격리를 위한 필드산화막(Field oxide)과 트윈웰(Twin well)을 형성한다.As shown in FIG. 4A, the gate oxide film 32 and the gate electrode 33 are sequentially formed on the semiconductor substrate 31. In this case, although not shown in the figure, field oxide and twin wells are formed for isolation between devices.
도 4b에 도시된 바와 같이, 게이트전극(33)을 마스크로 이용한 n+ 불순물의 이온주입을 실시하는데, 이 때 30°∼60°도로 틸트(Tilt)하여 즉, 소스측으로 향하도록 일방향에서만 이온주입을 실시하여 n+ 소스접합(34a) 및 n+ 드레인접합(34b)을 형성한다. 이 때, 틸트이온주입으로 인해 n+ 소스접합(34a)과 n+ 드레인접합(34b) 사이의 채널영역(31a)은 소스측에서 드레인측으로 기울어진 비대칭 형태로 형성된다.As shown in FIG. 4B, ion implantation of n + impurities using the gate electrode 33 as a mask is performed. At this time, the ion implantation is performed only in one direction so as to tilt to 30 ° to 60 °, that is, toward the source side. To form an n + source junction 34a and an n + drain junction 34b. At this time, due to the tilt ion implantation, the channel region 31a between the n + source junction 34a and the n + drain junction 34b is formed in an asymmetrical form inclined from the source side to the drain side.
도 4c에 도시된 바와 같이, 게이트전극(33)을 마스크로 이용한 p+ 불순물의 포켓이온주입(Pocket implantation)을 실시하여 n+ 소스/드레인접합(34a, 34b)을비대칭으로 형성하는데, 이 때 30°∼60°도로 틸트하여 즉, n+ 소스접합(34a)측으로 향하도록 일방향에서만 이온주입을 실시하여 n+ 소스접합(34a) 및 n+ 드레인 접합(34b)에 접하는 p+ 접합(35a,35b)을 형성한다. 여기서, n+ 드레인접합(34b)에 접하는 p+ 접합(35b)는 이웃한 트랜지스터의 비대칭 n+ 소스접합을 이룬다.As illustrated in FIG. 4C, pocket implantation of p + impurities using the gate electrode 33 as a mask is performed to form n + source / drain junctions 34a and 34b asymmetrically, at which time 30 ° Tilt to ˜60 °, that is, ion implantation is performed in only one direction so as to be directed toward the n + source junction 34a to form p + junctions 35a and 35b in contact with the n + source junction 34a and the n + drain junction 34b. Here, the p + junction 35b in contact with the n + drain junction 34b forms an asymmetric n + source junction of a neighboring transistor.
이 때, p+ 접합(35) 형성시 포켓이온주입을 실시하였으나, 다른 방법으로 틸트하여 카운터도핑(Counter doping)법을 이용할 수 있으며, 틸트이온주입으로 p+ 접합(35)을 형성하면 n+ 소스접합(34a)측에서 채널영역으로 기울기를 가진 접합이 형성된다.At this time, the pocket ion implantation was carried out when the p + junction 35 was formed, but by using a different method, the counter doping method can be used. If the p + junction 35 is formed by the tilt ion implantation, the n + source junction ( A junction with a slope from the side of 34a) to the channel region is formed.
상술한 바와 같이, n+ 소스접합(34a)측으로부터 n+ 드레인접합(34b)측으로 카운터도핑 또는 포켓이온주입의 농도를 줄여나가면, n+ 드레인접합(34b)에 고전압이 인가될 때 n+ 드레인접합(34b) 모서리 부근에서 핀치오프(Pinch off)가 발생되는 현상, 즉, 바디 효과(Body effect)를 보상하면서 핀치오프 전압을 증가시킬 수 있다. 이처럼, 핀치오프 전압을 증가시키면 포화전류(Saturation current)가 증가하게 된다.As described above, if the concentration of counter doping or pocket ion implantation is reduced from the n + source junction 34a side to the n + drain junction 34b side, the n + drain junction 34b when a high voltage is applied to the n + drain junction 34b. A pinch off voltage may be increased while compensating for a phenomenon in which pinch off occurs near the edge, that is, a body effect. As such, increasing the pinch-off voltage increases the saturation current.
그리고, n+ 드레인접합(34b)에서의 측면 전계(Lateral electric field)가 저채널농도(Low channel concentration)에 의해 펀치쓰루(Punch-through) 전압의 감소없이 저하되는데, 이는 n+ 소스접합(34a)측이 고농도로 도핑되므로 소스측의 공핍영역(Depletion region)이 커지는 것을 방지하기 때문이다.And, the lateral electric field in the n + drain junction 34b is lowered without decreasing the punch-through voltage due to the low channel concentration, which is the n + source junction 34a side. This is because the doping at a high concentration prevents the depletion region on the source side from growing.
전술한 바와 같이, 비대칭 소스/드레인 접합을 형성하면, 숏채널 효과나 핫캐리어 효과를 억제할 수 있다.As described above, by forming an asymmetric source / drain junction, the short channel effect and the hot carrier effect can be suppressed.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 반도체 소자의 제조 방법은 소스측에서 드레인측으로 기울어지는 접합을 형성한 후, 추가로 보론 이온을 소스측을 위주로 틸트이온주입하므로써 소스와 드레인의 직렬저항을 감소시켜 소자의 전류구동력을 향상시킬 수 있는 효과가 있다.In the method of manufacturing a semiconductor device as described above, after forming a junction inclined from the source side to the drain side, by further injecting boron ions with the tilt ion around the source side, the series resistance of the source and drain is reduced to improve the current driving force of the device. There is an effect that can be improved.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0086637A KR100377161B1 (en) | 2000-12-30 | 2000-12-30 | Mask rom and method for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0086637A KR100377161B1 (en) | 2000-12-30 | 2000-12-30 | Mask rom and method for fabricating the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020058528A KR20020058528A (en) | 2002-07-12 |
| KR100377161B1 true KR100377161B1 (en) | 2003-03-26 |
Family
ID=27689622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0086637A KR100377161B1 (en) | 2000-12-30 | 2000-12-30 | Mask rom and method for fabricating the same |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100377161B1 (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0214530A (en) * | 1988-06-30 | 1990-01-18 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0621476A (en) * | 1992-07-01 | 1994-01-28 | Seiko Epson Corp | Fabrication of semiconductor device |
| JPH06275636A (en) * | 1993-03-24 | 1994-09-30 | Sharp Corp | Manufacture of semiconductor device |
| JPH08264561A (en) * | 1995-03-20 | 1996-10-11 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and fabrication thereof |
| JPH08330457A (en) * | 1995-06-02 | 1996-12-13 | Hyundai Electron Ind Co Ltd | Formation of junction of flash eeprom cell |
| JPH0982950A (en) * | 1995-09-11 | 1997-03-28 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| KR980012451A (en) * | 1996-07-24 | 1998-04-30 | 김광호 | Method for manufacturing nonvolatile memory device |
| KR19990005492A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Flash memory device and manufacturing method thereof |
-
2000
- 2000-12-30 KR KR10-2000-0086637A patent/KR100377161B1/en not_active IP Right Cessation
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0214530A (en) * | 1988-06-30 | 1990-01-18 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0621476A (en) * | 1992-07-01 | 1994-01-28 | Seiko Epson Corp | Fabrication of semiconductor device |
| JPH06275636A (en) * | 1993-03-24 | 1994-09-30 | Sharp Corp | Manufacture of semiconductor device |
| JPH08264561A (en) * | 1995-03-20 | 1996-10-11 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and fabrication thereof |
| JPH08330457A (en) * | 1995-06-02 | 1996-12-13 | Hyundai Electron Ind Co Ltd | Formation of junction of flash eeprom cell |
| JPH0982950A (en) * | 1995-09-11 | 1997-03-28 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| KR980012451A (en) * | 1996-07-24 | 1998-04-30 | 김광호 | Method for manufacturing nonvolatile memory device |
| KR19990005492A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Flash memory device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020058528A (en) | 2002-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5051793A (en) | Coplanar flash EPROM cell and method of making same | |
| KR930007195B1 (en) | Semiconductor device and its manufacturing method | |
| US5946558A (en) | Method of making ROM components | |
| US5264384A (en) | Method of making a non-volatile memory cell | |
| US6351017B1 (en) | High voltage transistor with modified field implant mask | |
| EP1939934A2 (en) | Nonvolatile memory device and method of fabricating the same | |
| KR100510541B1 (en) | High voltage transistor and method for manufacturing the same | |
| JPH11330280A (en) | Manufacture of flash memory cell structure by erasing/ writing channel and its operation method | |
| KR100360398B1 (en) | Cell array region of NOR-type Mask ROM device and method for fabricating the same | |
| KR100585097B1 (en) | EEPROM device and method for fabricating the same | |
| US20050037581A1 (en) | Multibit ROM cell and method therefor | |
| JP2581411B2 (en) | Semiconductor memory circuit device and method of manufacturing the same | |
| KR100377161B1 (en) | Mask rom and method for fabricating the same | |
| EP0021776B1 (en) | Semiconductor memory device and method of making same | |
| KR100546496B1 (en) | Nonvolatile semiconductor memory device and manufacturing method thereof | |
| JPH09102555A (en) | Electrically rewritable nonvolatile semiconductor memory device and its manufacture | |
| US5610428A (en) | Semiconductor integrated circuit | |
| KR960012261B1 (en) | Mos-depletion type cut-off transistor | |
| US6777762B2 (en) | Mask ROM structure having a coding layer between gates and word lines | |
| KR100204541B1 (en) | Semiconductor device and its making method | |
| KR100390046B1 (en) | Mask ROM cell structure and method for manufacturing same | |
| US7602004B2 (en) | Semiconductor device and methods for forming the same | |
| EP0957521A1 (en) | Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process | |
| KR100399415B1 (en) | Nonvolatile Memory Device and Method of fabricationg the Same | |
| KR20090007868A (en) | High voltage transistor and method of fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |