KR100374542B1 - Semiconductor package and method for manufacturing the same - Google Patents
Semiconductor package and method for manufacturing the same Download PDFInfo
- Publication number
- KR100374542B1 KR100374542B1 KR10-2000-0065023A KR20000065023A KR100374542B1 KR 100374542 B1 KR100374542 B1 KR 100374542B1 KR 20000065023 A KR20000065023 A KR 20000065023A KR 100374542 B1 KR100374542 B1 KR 100374542B1
- Authority
- KR
- South Korea
- Prior art keywords
- chip
- lead
- bonding pad
- wire
- mounting plate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로서, 하프 에칭된 리드프레임의 칩탑재판에 동일한 크기의 반도체 칩을 본딩패드 자리가 없는 후면끼리 서로 맞대어지게 적층하고, 리드프레임의 리드 상면과 상부칩의 본딩패드, 그리고 리드프레임의 리드 저면과 하부칩의 본딩패드간의 와이어 본딩이 순차적으로 이루어진 새로운 구조의 반도체 패키지 및 그 제조방법을 제공하고자 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, wherein a semiconductor chip of the same size is stacked on a chip-mounted board of a half-etched lead frame so that the rear surfaces without bonding pads face each other. The present invention provides a semiconductor package having a new structure and a method for manufacturing the same, in which a bonding pad of a wire and a wire bonding between a lead bottom surface of a lead frame and a bonding pad of a lower chip are sequentially formed.
이에, 기존에 동일한 크기의 칩 적층에 사용되던 인터포져의 삽입 작업공수를 절감하는 동시에 비용을 절감할 수 있고, 또한, 칩탑재판의 상면 두께를 에칭처리하여 감소시킴으로써, 반도체 패키지의 두께를 줄일 수 있으며, 또한, 상기 리드의 외측면과 저면, 칩탑재판의 저면등이 외부로 노출됨에 따라, 반도체 칩에서 발생하는 열의 방출을 극대화시킬 수 있는 효과를 얻어낼 수 있게 된다.Therefore, it is possible to reduce the cost of inserting the interposer, which is used for stacking chips of the same size, and to reduce the cost, and to reduce the thickness of the semiconductor package by reducing the thickness of the upper surface of the chip mounting plate by etching. In addition, as the outer surface and the bottom surface of the lead, the bottom surface of the chip mounting plate is exposed to the outside, it is possible to obtain the effect of maximizing the emission of heat generated in the semiconductor chip.
Description
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 동일한 크기의 반도체 칩을 적층하여 이루어진 새로운 구조의 반도체 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package having a new structure formed by stacking semiconductor chips of the same size and a method for manufacturing the same.
통상적으로 반도체 패키지는 전자기기의 집약적인 발달과 소형화 경향으로 고집적화, 소형화, 고기능화를 실현할 수 있는 제조 추세에 있는 바, 리드프레임, 인쇄회로기판, 필름등의 부재를 이용하여 칩탑재판의 저면이 외부로 노출된 구조의 반도체 패키지, 솔더볼과 같은 인출단자를 포함하는 볼 그리드 어레이 반도체 패키지, 다수개의 칩이 적층된 구조의 패키지등, 그 밖에 다양한 종류의 패키지가 경박단소화로 개발되어 왔고, 개발중에 있다.In general, semiconductor packages have been manufactured to realize high integration, miniaturization, and high functionality due to the intensive development and miniaturization of electronic devices. The bottom surface of the chip mounting board is formed by using members such as lead frames, printed circuit boards, and films. Various types of packages have been developed with light and small size, such as semiconductor packages with exposed structure, ball grid array semiconductor packages with lead terminals such as solder balls, and packages with multiple chips stacked. There is.
특히, 최근에는 다수개의 칩을 적층한 구조의 반도체 패키지로서, 서로 다른 크기 또는 동일한 크기의 반도체 칩을 적층한 구조의 반도체 패키지의 개발이 계속요구되고 있다.In particular, in recent years, development of semiconductor packages having a structure in which semiconductor chips having a different size or the same size are stacked as semiconductor packages having a structure in which a plurality of chips are stacked is continuously demanded.
따라서, 종래에는 동일한 칩을 적층하기 위하여 적층될 칩 사이에 인터포져와 같은 부재를 끼워넣어 적층되는 칩 사이의 상하 간격을 유지하고, 각각 위쪽을 향해 위치된 칩의 본딩패드와 리드간을 와이어로 본딩하여 반도체 패키지를 제조함에 따라, 인터포져에 의한 반도체 패키지의 두께가 증가하는 단점이 있고, 상부칩 밑에 좁은 간격으로 위치되어 있는 하부칩의 본딩패드과 리드간을 와이어로 본딩하는 작업이 어려워 와이어의 손상을 초래하는 단점이 있었다Accordingly, in order to stack the same chip, a member such as an interposer is sandwiched between chips to be stacked to maintain vertical gaps between the stacked chips, and wires between the bonding pads and the leads of the chips positioned upwards, respectively, are wired. As the semiconductor package is manufactured by bonding, the thickness of the semiconductor package due to the interposer increases, and it is difficult to bond the wires between the bonding pads and the leads of the lower chip, which are located at a narrow interval under the upper chip, to prevent the wire from being connected. Had the disadvantages of causing damage
따라서, 본 발명은 상기와 같은 점을 감안하여, 하프에칭된 리드프레임의 칩탑재판에 동일한 크기의 반도체 칩을 본딩패드 자리가 없는 후면끼리 서로 맞대어지게 적층하고, 리드프레임의 리드 상면과 상부칩의 본딩패드, 그리고 리드프레임의 리드 저면과 하부칩의 본딩패드간의 와이어 본딩이 순차적으로 이루어진 구조의 반도체 패키지 및 그 제조방법을 제공하는데 그 목적이 있다.Therefore, in view of the above, the present invention stacks semiconductor chips of the same size on the chip mounting board of the half-etched lead frame so that the back surfaces without bonding pads face each other, and the lead upper surface and the upper chip of the lead frame The purpose of the present invention is to provide a semiconductor package having a structure in which a bonding pad of, and a wire bonding between a lead bottom surface of a lead frame and a bonding pad of a lower chip are sequentially formed.
도 1은 본 발명에 따른 반도체 패키지의 제조방법을 순서대로 나타내는 단면도,1 is a cross-sectional view sequentially showing a method for manufacturing a semiconductor package according to the present invention;
도 2는 도 1의 반도체 패키지를 나타내는 단면도,FIG. 2 is a cross-sectional view illustrating the semiconductor package of FIG. 1; FIG.
도 3은 본 발명에 따른 반도체 패키지의 제조방법의 다른 실시예를 나타내는 단면도,3 is a cross-sectional view showing another embodiment of a method of manufacturing a semiconductor package according to the present invention;
도 4는 도 3의 반도체 패키지를 나타내는 단면도.4 is a cross-sectional view illustrating the semiconductor package of FIG. 3.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 반도체 체키지 12 : 리드10: semiconductor package 12: lead
14 : 지지부재 16 : 제1칩14 support member 16 first chip
18 : 제2칩 20 : 제2와이어18: second chip 20: second wire
22 : 제1와이어 24 : 수지22: first wire 24: resin
26 : 인출단자 28 : 칩탑재판26: withdrawal terminal 28: chip mounting board
이하, 첨부도면을 참조로 본 발명을 상세하게 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
상기한 목적을 달성하기 위한 본 발명의 반도체 패키지는:The semiconductor package of the present invention for achieving the above object is:
저면의 일부가 에칭 처리된 리드(12)와; 상면이 일정 두께로 에칭 처리된 칩탑재판(28)과; 상기 리드(12)의 상면 테두리에 부착되는 지지부재(14)와; 상기 칩탑재판(28)에 실장되는 제1칩(16)과; 이 제1칩(16)의 상면에 접착수단으로 적층 부착되는 제2칩(18)과; 상기 제2칩(18)의 본딩패드와 리드(12)의 상면간에 연결된 제2와이어(20)와; 상기 제1칩(16)의 본딩패드와 리드(12)의 저면간에 연결된 제1와이어(22)와; 상기 리드(12)의 외측면과 저면, 상기 칩탑재판(28)의 저면, 상기 지지부재(14)의 상면과 외측면을 외부로 노출시키면서 반도체 칩들과 와이어등을 몰딩하고 있는 수지(24)로 구성된 것을 특징으로 한다.A portion of the bottom 12 which has been etched; A chip mounting plate 28 whose upper surface is etched to a predetermined thickness; A support member 14 attached to an upper edge of the lid 12; A first chip 16 mounted on the chip mounting plate 28; A second chip 18 laminated on the upper surface of the first chip 16 by adhesion means; A second wire 20 connected between a bonding pad of the second chip 18 and an upper surface of the lead 12; A first wire 22 connected between the bonding pad of the first chip 16 and the bottom surface of the lid 12; The resin 24 molding the semiconductor chips and the wires while exposing the outer surface and the bottom surface of the lid 12, the bottom surface of the chip mounting plate 28, and the top and outer surfaces of the support member 14 to the outside. Characterized in that consisting of.
본 발명의 바람직한 구현예로서, 상기 외부로 노출된 리드(12)의 저면에는인출단자(26)가 부착되고, 또한 상기 제1칩(16)과 제2칩(18)은 본딩패드가 없는 후면끼리 서로 접촉되어 부착된 것을 특징으로 한다.In a preferred embodiment of the present invention, a drawing terminal 26 is attached to a bottom surface of the lead 12 that is exposed to the outside, and the first chip 16 and the second chip 18 have a backside without a bonding pad. Characterized in that the contact is attached to each other.
또 다른 구현예로서, 상기 지지부재(14)는 비전도성의 플라스틱으로 성형된 것을 특징으로 한다.In another embodiment, the support member 14 is characterized in that it is molded from a non-conductive plastic.
상기한 목적을 달성하기 위한 본 발명의 반도체 패키지 제조방법은:The semiconductor package manufacturing method of the present invention for achieving the above object is:
리드프레임의 리드(12) 저면 일부와 칩탑재판(28)의 상면 소정두께를 에칭처리하는 공정과; 상기 리드(12)의 상면에 지지부재(14)를 부착하는 공정과; 상기 칩탑재판(28)에 본딩패드가 없는 후면이 위쪽을 향하도록 제1칩(16)을 부착하는 공정과; 상기 제1칩(16)의 후면에 본딩패드가 없는 후면이 접촉되게 제2칩(18)을 부착하는 공정과; 상기 제2칩(18)의 본딩패드와 리드(12)의 상면간을 제2와이어(20)로 본딩하는 공정과; 상기 제1,2칩(16,18)의 부착공정과 제2칩(18)의 와이어 본딩 공정이 끝난 상태의 리드프레임을 뒤집어서 지지부재(14)가 리드프레임의 리드를 받치면서 지지하도록 한 공정과; 상기 제1칩(16)의 본딩패드와 리드(12)의 저면간을 제1와이어(22)로 본딩하는 공정과; 상기 리드(12)의 외측면과 저면, 상기 칩탑재판(28)의 저면, 상기 지지부재(14)의 상면과 외측면을 외부로 노출시키면서 상기 반도체 칩들(16,18)과 와이어(20,22)등을 수지(24)로 몰딩하는 공정으로 이루어진 것을 특징으로 한다.Etching a portion of the bottom surface of the lead 12 of the lead frame and a predetermined thickness of the upper surface of the chip mounting plate 28; Attaching a support member (14) to an upper surface of the lead (12); Attaching a first chip (16) to the chip mounting plate (28) such that a rear surface without a bonding pad faces upward; Attaching a second chip (18) to the back of the first chip (16) so that the back without a bonding pad contacts; Bonding a bonding pad of the second chip (18) and an upper surface of the lead (12) with a second wire (20); The support frame 14 is supported while supporting the lead of the lead frame by inverting the lead frame after the attachment process of the first and second chips 16 and 18 and the wire bonding process of the second chip 18 are completed. and; Bonding a bonding pad of the first chip (16) and a bottom surface of the lead (12) with a first wire (22); The semiconductor chips 16 and 18 and the wire 20 may be exposed while exposing the outer surface and the bottom surface of the lead 12, the bottom surface of the chip mounting plate 28, and the top and outer surfaces of the support member 14 to the outside. 22) and the like, characterized in that the step of molding a resin (24).
또한, 상기 외부로 노출된 리드(12)의 저면에 인출단자(26)를 부착하는 공정이 더 진행되는 것을 특징으로 한다.In addition, the step of attaching the withdrawal terminal 26 to the bottom of the lead 12 exposed to the outside is characterized in that the further progress.
여기서, 본 발명을 실시예로서, 첨부한 도면을 참조로 더욱 상세하게 설명하면 다음과 같다.Herein, the present invention will be described in more detail with reference to the accompanying drawings.
첨부한 도 1은 본 발명에 따른 반도체 패키지의 제조방법을 순서대로 나타낸 단면도로서, 먼저 상기 반도체 패키지의 제조하기 위한 리드프레임을 구비하게 된다.1 is a cross-sectional view sequentially illustrating a method of manufacturing a semiconductor package according to the present invention. First, a lead frame for manufacturing the semiconductor package is provided.
상기 리드프레임의 리드(12)의 저면 일부를 에칭 처리하여, 에칭 처리되지 않은 리드(12)의 저면을 입출력 단자로 활용할 수 있도록 한다.A portion of the bottom surface of the lead 12 of the lead frame is etched so that the bottom surface of the lead 12 which is not etched can be utilized as an input / output terminal.
또한, 상기 리드프레임의 칩탑재판(28)의 상면 전체를 소정의 두께로 에칭처리하여, 그 두께를 감소시키게 된다.In addition, the entire upper surface of the chip mounting plate 28 of the lead frame is etched to a predetermined thickness to reduce the thickness thereof.
다음으로, 상기와 같이 구비된 리드프레임을 이용하여 본 발명의 반도체 패키지와 그 제조방법을 순서대로 설명하면 다음과 같다.Next, the semiconductor package of the present invention and a manufacturing method thereof will be described in order using the lead frame provided as described above.
상기 리드프레임의 리드(12) 상면에 지지부재(14)를 부착시키는 공정을 진행하게 되는데, 상기 지지부재(14)는 형상에 관계없이 비전도성의 플라스틱 재질을 사용하여 성형된 것을 부착시키는 것이 바람직하다.The process of attaching the support member 14 to the upper surface of the lead 12 of the lead frame is carried out, the support member 14 is preferably attached to the molded using a non-conductive plastic material regardless of the shape. Do.
그 다음 공정으로서, 상기 리드프레임의 칩탑재판(28)에 접착수단을 사용하여 제1칩(16)을 부착하는 공정을 진행하는 바, 상기 제1칩(16)의 크기는 상기 칩탑재판(28)의 크기보다 큰 것을 부착하게 된다.Next, as a step of attaching the first chip 16 to the chip mounting plate 28 of the lead frame by using an adhesive means, the size of the first chip 16 is the chip mounting plate. The larger than the size of (28) will be attached.
특히, 상기 제1칩(16)은 본딩패드 자리가 없는 후면이 위쪽을 향하도록 부착되어, 상면의 본딩패드 자리는 칩탑재판(28)의 주변에서 밑쪽을 향하여 노출된 상태가 된다.In particular, the first chip 16 is attached so that the rear surface without the bonding pad seat faces upward, and the bonding pad seat on the upper surface is exposed downward from the periphery of the chip mounting plate 28.
다음으로, 상기 제1칩(16)의 후면에 접착수단을 사용하여 동일한 크기를 갖는 제2칩(18)을 부착하는 공정을 진행하게 되는 바, 제2칩(18)의 후면이 상기 제1칩(16)의 후면과 접촉하도록 부착하여, 제2칩(18)의 본딩패드 자리가 위쪽을 향하도록 한다.Next, a process of attaching the second chip 18 having the same size to the rear surface of the first chip 16 is performed. The rear surface of the second chip 18 is the first chip. Attached so as to be in contact with the back of the chip 16, so that the bonding pad seat of the second chip 18 faces upward.
다음 공정으로, 상기 제2칩(18)의 본딩패드와 리드(12)의 상면간을 제2와이어(20)로 본딩하는 공정을 진행하는 바, 상기 제2와이어(20)의 최대 높이는 상기 지지부재(14)의 높이보다 낮은 위치가 되도록 한다.In the next process, a process of bonding a bonding pad of the second chip 18 and an upper surface of the lead 12 to the second wire 20 is performed, and the maximum height of the second wire 20 is the support. The position is lower than the height of the member 14.
이어서, 상기 제1칩(16)과 제2칩(18)이 적층되어 부착되고, 제2칩(18)의 본딩패드와 리드(12)의 상면이 제2와이어(20)로 본딩된 상태에서, 리드프레임을 뒤집는 공정을 진행하게 된다.Subsequently, the first chip 16 and the second chip 18 are stacked and attached, and the bonding pads of the second chip 18 and the upper surfaces of the leads 12 are bonded with the second wire 20. Then, the lead frame is inverted.
따라서, 상기 지지부재(14)가 리드(12)를 받치면서 바닥면에 안착되고, 상기 칩탑재판(28)과 제1칩(16)의 본딩패드가 위쪽을 향하며 위치된다.Accordingly, the support member 14 rests on the bottom surface while supporting the lid 12, and the bonding pads of the chip mounting plate 28 and the first chip 16 are positioned upward.
다음 공정으로, 상기 제1칩(16)의 본딩패드와 위쪽을 향하고 있는 리드(12)의 저면간을 제1와이어(22)로 본딩하는 공정을 진행하게 되는 바, 상기 제1와이어(22)의 최대높이는 리드(12)의 저면보다 낮은 위치가 되도록 한다.In the next step, a process of bonding the first pad 22 between the bonding pad of the first chip 16 and the bottom surface of the lead 12 facing upward is performed. The maximum height of is to be lower than the bottom of the lid 12.
그 다음으로, 상기 제1칩(16)과 제2칩(18), 그리고 상기 제1와이어(22)와 제2와이어(20)등을 수지(24)로 몰딩하는 공정을 진행하게 되는 바, 상기 리드(12)의 외측면과 저면, 상기 칩탑재판(28)의 저면, 상기 지지부재(14)의 외측면과 상면이 외부로 노출되도록 몰딩함으로써, 첨부한 도 2에 도시한 바와 같은 동일한 크기의 칩 적층형 반도체 패키지(10)가 완성된다.Next, a process of molding the first chip 16 and the second chip 18 and the first wire 22 and the second wire 20, etc. with resin 24 is performed. By molding the outer surface and the bottom surface of the lid 12, the bottom surface of the chip mounting plate 28, the outer surface and the upper surface of the support member 14 to be exposed to the outside, the same as shown in Figure 2 A chip stacked semiconductor package 10 of size is completed.
이때, 상기 외부로 노출된 리드(12)의 저면은 마더보드에 실장되는 입출력단자 역할을 하게 되고, 또한 상기 리드(12)의 외측면과 저면, 그리고 칩탑재판(28)의 저면이 외부로 노출된 상태가 됨에 따라, 반도체 칩에서 발생하는 열을 효과적으로 방출시킬 수 있게 된다.At this time, the bottom surface of the lead 12 exposed to the outside serves as an input / output terminal mounted on the motherboard, the outer surface and the bottom surface of the lead 12, and the bottom surface of the chip mounting plate 28 to the outside As the exposed state, it is possible to effectively release the heat generated in the semiconductor chip.
또한, 상기 리드프레임의 칩탑재판(28)의 상면이 소정의 두께로 에칭처리됨에 따라, 적층된 제1칩(16)과 제2칩(18)의 실장높이를 줄일수 있게 되어, 결국 반도체 패키지의 두께를 줄일 수 있게 된다.In addition, as the upper surface of the chip mounting plate 28 of the lead frame is etched to a predetermined thickness, the mounting height of the stacked first chip 16 and the second chip 18 can be reduced, resulting in semiconductor The thickness of the package can be reduced.
한편, 첨부한 도 3과 도 4는 본 발명의 다른 실시예로서, 상기와 같이 제조된 반도체 패키지에서 외부로 노출된 리드(12) 저면에 솔더볼과 같은 인출단자(26)를 부착하는 공정을 더 진행시켜 달성된다.On the other hand, Figures 3 and 4 attached as another embodiment of the present invention, in addition to the process of attaching the lead terminal 26, such as solder ball on the bottom surface of the lead 12 exposed to the outside in the semiconductor package manufactured as described above Proceed by proceeding.
이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지 및 그 제조방법에 의하면, 동일한 크기의 칩을 본딩패드 자리가 없는 후면끼리 적층한 후, 각각 상면과 저면을 향해있는 칩의 본딩패드와 리드간을 순차적으로 와이어 본딩할 수 있도록 함으로써, 기존에 동일한 크기의 칩 적층에 사용되던 인터포져의 삽입 작업공수를 절감하는 동시에 비용을 절감할 수 있다.As described above, according to the semiconductor package and the method of manufacturing the same according to the present invention, after stacking chips of the same size with each other without a bonding pad seat, the bonding pad and the lead of the chip facing the upper and lower surfaces, respectively, By enabling wire bonding in sequence, it is possible to reduce the cost of inserting the interposer that has been used for stacking chips of the same size.
또한, 칩탑재판의 상면두께를 에칭처리하여 감소시킴으로써, 반도체 패키지의 두께를 줄일 수 있다.In addition, by reducing the thickness of the upper surface of the chip mounting plate by etching, the thickness of the semiconductor package can be reduced.
또한, 상기 리드의 외측면과 저면, 칩탑재판의 저면등이 외부로 노출됨에 따라, 반도체 칩에서 발생하는 열의 방출을 극대화시킬 수 있다.In addition, as the outer surface and the bottom surface of the lead, the bottom surface of the chip mounting plate is exposed to the outside, it is possible to maximize the emission of heat generated in the semiconductor chip.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0065023A KR100374542B1 (en) | 2000-11-02 | 2000-11-02 | Semiconductor package and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0065023A KR100374542B1 (en) | 2000-11-02 | 2000-11-02 | Semiconductor package and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020034617A KR20020034617A (en) | 2002-05-09 |
| KR100374542B1 true KR100374542B1 (en) | 2003-03-04 |
Family
ID=19697002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0065023A KR100374542B1 (en) | 2000-11-02 | 2000-11-02 | Semiconductor package and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100374542B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101010204B1 (en) * | 2007-06-18 | 2011-01-21 | 민승기 | Drainage pipe of bank using river |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990006141A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Stacked ball grid array package and its manufacturing method |
| JPH11219984A (en) * | 1997-11-06 | 1999-08-10 | Sharp Corp | Semiconductor device package, its manufacture and circuit board therefor |
| KR20000020479A (en) * | 1998-09-21 | 2000-04-15 | 김영환 | Stack package |
| KR20000027503A (en) * | 1998-10-28 | 2000-05-15 | 김영환 | Stacked package |
| KR20000060748A (en) * | 1999-03-19 | 2000-10-16 | 어드밴스트 세미콘덕터 엔지니어링 인코포레이티드 | Structure for stacking electric elements |
-
2000
- 2000-11-02 KR KR10-2000-0065023A patent/KR100374542B1/en active IP Right Grant
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990006141A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Stacked ball grid array package and its manufacturing method |
| JPH11219984A (en) * | 1997-11-06 | 1999-08-10 | Sharp Corp | Semiconductor device package, its manufacture and circuit board therefor |
| KR20000020479A (en) * | 1998-09-21 | 2000-04-15 | 김영환 | Stack package |
| KR20000027503A (en) * | 1998-10-28 | 2000-05-15 | 김영환 | Stacked package |
| KR20000060748A (en) * | 1999-03-19 | 2000-10-16 | 어드밴스트 세미콘덕터 엔지니어링 인코포레이티드 | Structure for stacking electric elements |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020034617A (en) | 2002-05-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101076062B1 (en) | Offset integrated circuit package-on-package stacking system | |
| KR100460063B1 (en) | Stack ball grid arrary package of center pad chips and manufacturing method therefor | |
| US6972214B2 (en) | Method for fabricating a semiconductor package with multi layered leadframe | |
| TWI430425B (en) | Integrated circuit package system employing bump technology | |
| US6740973B1 (en) | Stacked structure for an image sensor | |
| US5889333A (en) | Semiconductor device and method for manufacturing such | |
| US20030234442A1 (en) | Semiconductor package and method for fabricating the same | |
| JP2000299423A (en) | Lead frame, semiconductor device using the same and manufacture thereof | |
| KR100374542B1 (en) | Semiconductor package and method for manufacturing the same | |
| US8148208B2 (en) | Integrated circuit package system with leaded package and method for manufacturing thereof | |
| JP3203200B2 (en) | Semiconductor device | |
| JPH10256473A (en) | Semiconductor device | |
| KR0182506B1 (en) | Method of manufacturing high density mounting package | |
| KR20010025861A (en) | Stack type chip scale semiconductor package | |
| KR100464561B1 (en) | Semiconductor package and manufacturing method the same | |
| KR100375168B1 (en) | Semiconductor package and method for manufacturing the same | |
| KR100522838B1 (en) | Semiconductor package and method for manufacturing the same | |
| KR102233649B1 (en) | Stacked semiconductor package and manufacturing method of the same | |
| KR100401145B1 (en) | Semiconductor package and method for manufacturing the same | |
| US8148825B2 (en) | Integrated circuit package system with leadfinger | |
| KR100373149B1 (en) | Semiconductor package | |
| KR100508733B1 (en) | Semiconductor package and method for manufacturing the same | |
| KR100456815B1 (en) | Semiconductor package and method for attaching chip | |
| KR100355745B1 (en) | Semiconductor package | |
| KR100508261B1 (en) | Semiconductor package and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130204 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20140204 Year of fee payment: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20150203 Year of fee payment: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20160202 Year of fee payment: 14 |
|
| FPAY | Annual fee payment |
Payment date: 20170209 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20180207 Year of fee payment: 16 |
|
| FPAY | Annual fee payment |
Payment date: 20190212 Year of fee payment: 17 |
|
| FPAY | Annual fee payment |
Payment date: 20200218 Year of fee payment: 18 |