KR100370153B1 - Device for Programming and Reading of Flash Memory - Google Patents

Abstract

The present invention provides a flash memory write / read device for accurately reading data of each memory cell at an accurate reference voltage, comprising: a memory cell array unit including a plurality of memory cells; A reference cell array unit including a plurality of reference cells; A voltage generator connected between the memory cell array unit and the reference cell array unit to generate a voltage for writing each data; An average circuit unit for generating a reference value by taking an average of voltages or currents between two adjacent reference cells of the reference cell array unit; And a sensing circuit unit configured to output data of the main cell of the corresponding level by comparing the reference value made by the average circuit unit with a voltage or current level of the memory cell array unit.

Description

Device for programming and reading of flash memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to flash memory, and more particularly, to a flash memory write / read device for accurately reading data of a multi-level memory.

Hereinafter, with reference to the accompanying drawings as follows.

First, a structure and a write operation of a memory cell constituting a flash memory write / read device will be described.

In the configuration of the memory cell, the source / drain regions are formed of impurities of a different type from the semiconductor substrate, and the floating gate is present on the semiconductor substrate between the source and drain regions.

A control gate is formed on the floating gate, and a gate oxide film is interposed between the semiconductor substrate and the floating gate to insulate each other.

The region between the source and the drain under the floating gate is called a channel, and the size of the floating gate is usually larger than the distance between the source and the drain, that is, the channel length.

Referring to the flash memory cell shown in the equivalent circuit, it is as shown in FIG.

1 is an equivalent circuit of a memory cell, as shown in FIG. 1, in general, a flash memory cell has a control gate 4 for controlling the floating gate 3 and the floating gate 3, and a source 1 and a drain. It consists of (2).

The electron is injected into the floating gate 3 using the voltage applied between the terminal of the control gate 4 and the source / drain (1, 2) terminal to write to the cell. As the threshold voltage of the cell increases, the write operation is stopped when the desired threshold voltage is reached.

Next, the configuration and operation principle of a write / read device of a flash memory using the memory cell will be described.

2 is a block diagram showing the configuration of a write / read device of a flash memory.

As shown in FIG. 2, a first voltage generator 21 for supplying write and read voltages to a word line WL and a plurality of data in which data is written in accordance with the voltage of the first voltage generator 21. A reference cell in which reference data is written, comprising a memory cell array unit 23 consisting of two memory cells 23a, 23b, 23c, and 23d, and a plurality of reference cells 24a, 24b, and 24c for distinguishing each level data. Outputs the programmed data (00, 01, 10, 11) by comparing the array unit 24 with each of the memory cells 23a, 23b, 23c, 23d and the reference cells 24a, 24b, 24c. And a second voltage generator 22 that supplies write and read voltages to the word line WL of the reference cell array unit 24.

The operation principle of a device for writing / reading a flash memory cell according to the related art is as follows.

First, a program operation of each cell of the flash memory will be described. Four levels of data (00, 01, 10, 11) are written to each memory cell 23a, 23b, 23c, 23d. Voltage is required.

For example, in the case where the first voltage generator 21 generates a voltage of 2, 4, 6, or 8 V and performs a write operation, a voltage (for example, 2, 4, 6, 8 V) is applied to each other. If the write operation is stopped when the same current flows through the memory cells 23a, 23b, 23c, and 23d, the threshold voltages of the respective multilevel memory cells 23a, 23b, 23c, and 23d are four levels (1, 3, 5). , 7V).

Thus, when reading the memory cells 23a, 23b, 23c, and 23d as 00, 01, 10, and 11, respectively, two data are written and read in one memory cell 23a, 23b, 23c, and 23d. Can be implemented.

At this time, in order to make different voltages of 2, 4, 6, and 8 V in the first voltage generator 21, there must be at least four different voltage generator circuits.

Three reference values (ref1, ref2, ref3) are required to distinguish the data (00, 01, 10, 11) of each level written in the memory cell array unit (23). In order to distinguish between 00 and 01, there must be a cell in which the middle reference value (ref1) of 00 and 01 is written. Similarly, the intermediate reference values (ref2 and ref3) to distinguish 01 and 10, 10 and 11 are necessary.

In order to create these three reference values ref1, ref2, and ref3, the reference cell array unit 24 is the intermediate voltage value in the second voltage generator 22, similarly to the write operation of the multilevel memory cell array unit 23. When a write operation is generated by generating voltages of 3, 5, and 7 V, three reference values (ref1, ref2, and ref3) having different threshold voltages are generated.

At this time, the second voltage generator 22 must have at least three voltage generator circuits to generate different voltages of 3, 5, and 7V.

Meanwhile, in order to read the data of the memory cell array unit 23, the same voltage is applied to the word line WL of the memory cell array unit 23 and the word line WL of the reference cell array unit 24. The bit values of the memory cells 23a, 23b, 23c, and 23d are compared with the current values applied to the bit lines of the respective reference cells 24a, 24b, and 24c.

At this time, since the threshold voltages are different between the memory cells 23a, 23b, 23c, and 23d and the reference cells 24a, 24b, and 24d that are written for each level, there is a difference in cell current.

For example, in the case of the main cell 23a at the level of 00, the cell current will flow the most because the threshold voltage is the lowest, and in the case of the main cell 23d at the level 11, the current is increased because the threshold voltage is the highest. It will flow little or very finely, and the current flowing through the reference cells 24a, 24b, 24c will be distributed between each of the memory cells 23a, 23b, 23c, 23d.

Accordingly, the sensing circuit unit 25 outputs any one of 00, 01, 10, and 11 by comparing current values of the memory cell array unit 23 and the reference cell array unit 24.

However, the above conventional write / read device of the flash memory has the following problems.

First, it is necessary to make and supply different voltages to the memory cell array unit and the reference cell array unit. The voltage value may vary depending on the collector voltage Vcc, or may vary slightly depending on process characteristics.

In addition, since the threshold voltage of the cell is not kept constant but has a certain degree of distribution, the threshold voltage of each level may move to the left and right while having a certain degree of distribution.

Therefore, the voltage value supplied by the second voltage generator may be shifted to either side rather than having an intermediate reference value, thereby causing a problem in the data read operation when the reference level value overlaps with the level data value of the memory cell.

Second, different circuits are needed to produce various different voltages, and the voltages produced in this way also make it difficult to maintain a constant level difference.

An object of the present invention is to provide a flash memory write / read device for accurately reading data of each memory cell by generating an accurate reference value.

1 is a circuit diagram showing an equivalent circuit of a flash memory cell

2 is a block diagram showing a configuration of a device for writing / reading a flash memory according to the related art

3 is a block diagram showing the configuration of a flash memory write / read device according to the present invention

4 is a graph showing the cell number distribution according to the threshold voltage of a multilevel memory cell according to a flash memory write / read device according to the present invention.

Explanation of symbols for the main parts of drawings

31: voltage generator 32: memory cell array

32a, 32b, 32c, and 32d: memory cell 33: reference cell array portion

33a, 33b, 33c, 33d: reference cell 34: sensing circuit

35: average circuit part

The flash memory write / read device according to the present invention for achieving the above object is a memory cell array portion consisting of a plurality of memory cells, a reference cell array portion consisting of a plurality of reference cells, the memory cell array portion and a reference cell A voltage generator which is connected between array units to generate a voltage for writing data, an average circuit unit which averages a voltage or current between two adjacent reference cells of the reference cell array unit to generate a reference value, and And a sensing circuit unit configured to output main cell data of a corresponding level by comparing the reference value made by the average circuit unit with a voltage or current level of the memory cell array unit.

Hereinafter, a write / read device of a flash memory will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing the configuration of a device for writing / reading a flash memory according to the present invention.

As shown in FIG. 3, the reference cell array unit including the memory cell array unit 32 including the plurality of memory cells 32a, 32b, 32c, and 32d and the plurality of reference cells 33a, 33b, 33c, and 33d. And a memory cell array 32a connected between the memory cell array unit 32 and the reference cell array unit 33 to write each level data (00, 01, 10, 11). The voltage or current between the voltage generator 31 for applying a voltage to the respective reference cells 33a, 33b, 33c, 33d, and adjacent reference cells of the reference cell array 33; An average circuit unit 35 that takes an average to produce three reference values ref1, ref2, and ref3, and compares the reference value made by the average circuit unit 35 with the voltage or current level of the memory cell array unit 32 The sensing circuit unit 34 outputs (sensing output) data of the corresponding level main cell.

The operation principle of the flash memory write / read device according to the present invention will be described as follows.

First, a write operation of each memory cell of the flash memory will be described. Four levels of data (00, 01, 10, 11) are stored in each of the memory cells 32a, 32b, 32c, and 32d of each memory cell array unit 32. Four different voltages are required for the program operation.

When the voltage generator 31 generates a voltage of 2, 4, 6, or 8 V to perform a write operation, when the write operation is stopped when the same current flows at each voltage, the cells of the memory cell array unit 32 ( Threshold voltages of 32a, 32b, 32c, and 32d are set at four levels (1, 3, 5, 7V). In this case, the same voltage is applied to one main cell of the main cell array unit 32 and one of the reference cell array unit 33.

Therefore, in the reference cell array unit 33 to which the same voltage as that of the memory cell array unit 32 is applied, the threshold voltages of the respective reference cells 33a, 33b, 33c, and 33d are different from those of the memory cells 32a, 32b, 32c, and 32d. The same level data (00, 01, 10, 11) is written in the same manner as the threshold voltage.

On the other hand, when reading the memory cells 32a, 32b, 32c, and 32d as level data of 00, 01, 10, and 11, respectively, two data (") are stored in one of the memory cells 32a, 32b, 32c, and 32d. 0 "," 1 ") to write and read.

Here, the voltage generator 31 which applies voltage to the memory cell array unit 32 and the reference cell array unit 33 simultaneously has four voltage generator circuits equal to the number of cells in order to generate different levels of voltage. need.

The following is a method of reading the data recorded in the memory cell array unit 32.

FIG. 4 is a graph showing the distribution of cell numbers according to threshold voltages. As shown in FIG. 4, four levels written in each memory cell 32a, 32b, 32c, and 32d of the memory cell array unit 32 are shown. Three reference values (ref1, ref2, ref3) are needed to distinguish the data (00,01,10,11).

That is, a reference value ref1, which is an average value of 00 and 01 for dividing 00 and 01, is required, and reference values ref2 and ref3, which are average values for dividing 01 and 10, 10 and 11, are also required.

The three reference values ref1, ref2, and ref3 are simultaneously applied to the memory cell array unit 32 and the reference cell array unit 33 by the voltage generator 31 to perform a write operation of the memory cell array unit 32. Similarly, the reference cell array unit 33 writes four levels of data 00, 01, 10, and 11, and the average circuit unit 35 uses the reference cell array to generate the reference values ref1, ref2, and ref3. The voltage or current of each drain stage between the adjacent reference cells 33a and 33b, 33b and 33c, 33c and 33d of the unit 33 is averaged, and the average value is output as the reference values ref1, ref2 and ref3.

At this time, the average circuit portion is composed of an average circuit of one less than the number of cells of the reference cell array unit 33, and here is composed of three average circuits.

Subsequently, the voltage or current of the main cell of the memory cell array unit 32 and the voltage or current of the reference values ref1, ref2, and ref3 output from the average circuit unit 35 are compared / amplified by the sensing circuit unit 34. Any data value recorded in each of the main cells 32a, 32b, 32c, and 32d representing the four level data (00, 01, 10, 11) is outputted to the output (sensing output) for reading operation.

As described above, the flash memory write / read device according to the present invention has the following effects.

First, the chip size can be reduced because the number of voltage generating circuits that occupy a relatively large layout area is reduced from seven to four.

Second, even if the level data distribution of 00, 01, 10, 11 changes, the reference value is made by using the voltage or current values according to the four levels of data of the reference cell part which writes with the same voltage value simultaneously with the memory cell part. The reference value can always be located at the center of each level (see FIG. 4).

Third, an error generated by threshold voltage distributions of the memory cell array unit and the reference cell array unit may be reduced during a read operation, thereby improving read characteristics and yield.

Claims (4)

A memory cell array unit comprising a plurality of memory cells; A reference cell array unit including a plurality of reference cells; A voltage generator connected between the memory cell array unit and the reference cell array unit to generate a voltage for writing each data; An average circuit unit for generating a reference value by taking an average of voltages or currents between two adjacent reference cells of the reference cell array unit; And And a sensing circuit unit which compares the reference value made by the average circuit unit with a voltage or current level of the memory cell array unit and outputs data of a main cell of a corresponding level. The method of claim 1, And the average circuit unit comprises an average circuit of one number less than the number of reference cells in the reference cell array unit. The method of claim 1, And the voltage generator comprises a voltage generator circuit having the same number of memory cells as the memory cells of the memory cell array unit. delete