KR100368609B1 - semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a trench type transverse double diffusion morph transistor. In this way, the first conductive epitaxial layer is grown on the first conductive semiconductor substrate, and the second conductive first diffusion layer is selectively formed on a portion of the epitaxial layer, and the first conductive second layer is formed on a portion of the first diffusion layer. Forming a diffusion layer, forming a first trench that penetrates the first and second diffusion layers, stacking a gate oxide film on the inner surface of the first trench, forming a gate electrode on the gate oxide film, and removing the bottom center portion of the gate electrode. A first conductive third diffusion layer is formed on the epitaxial layer below, an insulating film is stacked on the gate electrode, and the second trench is etched by partially etching the center portion of the bottom surface of the insulating film, the gate oxide film below it, and the high concentration diffusion layer below it. The second trench may be formed by etching the center portion of the bottom surface of the insulating film and the gate oxide film under the insulating film.

Therefore, the present invention does not require a large area diffusion layer for electrically connecting the output terminal to an external circuit, and does not bring about an increase in the required area of the IC chip. As a result, the degree of integration of the IC chip can be improved. In addition, it is possible to reduce the spreading resistance component in the drift region and further reduce the on-resistance value, thereby improving the current driving capability.

Description

Semiconductor device and method for manufacturing same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, a semiconductor device in which a trench type lateral double diffused MOS transistor is embedded in an IC chip without causing an increase in required area. And to a method for producing the same.

In general, power MOS transistors, such as trench lateral double diffused MOS transistors (hereinafter referred to as LD MOS transistors), provide faster operating speed and simplified control circuits than power bipolar junction transistors. Because of the advantages, such as the form of discrete devices (discrete device) is gradually expanding its field of use. More recently, LD morph transistors are embedded in IC chips to meet system-level demands.

However, disposing an output terminal of the LD MOS transistor does not cause any problem such as an increase in the required area in the case of individual devices, but in the case of an IC chip, it is difficult to embed an LD MOS transistor in the IC chip due to the increase in required area. It acts as a barrier.

That is, as shown in FIG. 1, in the conventional LD MOS transistor, for example, an n-type epitaxial layer 11 is epitaxially grown on an n-type semiconductor substrate 10, and a portion of the epitaxial layer 11 is formed. The p-type diffusion layer 13 diffuses, and the n + type diffusion layer 15 diffuses in a portion of the p-type diffusion layer 13 to be shallower than the junction depth of the P-type diffusion layer 13, and also in a portion of the n-type epilayer 11 In addition, the n + type diffusion layer 17 diffuses together. The gate oxide film 19 is laminated with a uniform thickness on the inner surface of the trench that penetrates a portion of the n + type diffusion layer 15 and the p type diffusion layer 13 to the junction of the p type diffusion layer 13, and the gate oxide film 19 The gate electrode 21 is stacked on the filling the trench. The source electrode 25 is electrically connected to the n + type diffusion layer 15 and the p type diffusion layer 13 via the contact hole of the insulating film 23, and the drain electrode 27 connects the contact hole of the insulating film 23. And is electrically connected to the n + type diffusion layer 17.

However, in the conventional LD morph transistor, only the gate electrode 21 is disposed in the trench and the drain electrode 27 is disposed outside the p-type diffusion layer 13 spaced apart from the trench in the lateral direction. A large area diffusion layer 17 is required for electrical connection with an external circuit. This leads to an enlargement of the area of the LD MOS transistor, and also to the area of an IC chip incorporating the LD MOS transistor. In addition, the spreading resistance component in the drift region is large, the on resistance value is high, and the current driving capability is low.

Accordingly, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, in which an LD morph transistor is embedded in an IC chip while preventing the area of the IC chip from expanding.

Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which reduce the on resistance and improve the current driving capability.

1 is a cross-sectional view showing a semiconductor device according to the prior art.

2 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

3 to 9 are process diagrams showing a method for manufacturing a semiconductor device according to the present invention.

10 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

11 to 13 are process drawings showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.

**** Explanation of symbols for the main parts of the drawing ****

10: semiconductor substrate 11: N-type epi layer

13, 33: p-type diffusion layer 15, 17, 35, 47: n + type diffusion layer

19 and 41: gate oxide films 21 and 45: gate electrodes

23, 37, 39, 49, 53: insulating film 25, 55: source electrode

27, 51: drain electrode 52: silicide layer

54: undercoat

The semiconductor device according to the embodiment of the present invention for achieving the above object is

A first conductive semiconductor substrate having a first conductive epitaxial layer;

A second conductivity type first diffusion layer diffused in a portion of the epi layer;

A first conductive type second diffusion layer having a high concentration diffused in a portion of the first diffusion layer;

A gate oxide film formed on an inner surface of the first trench that penetrates together with the second diffusion layer and the first diffusion layer;

A gate electrode formed on the gate oxide layer and defined at a side portion of the first trench;

A first conductive type third diffusion layer having a high concentration formed in the epitaxial layer under the first trench;

A drain electrode filled in the first trench defined by the insulating film stacked on the gate electrode and filled in the second trench formed in the third diffusion layer and penetrating the center portion of the bottom surface of the insulating film and the gate oxide film; And

And a source electrode electrically connected to the second diffusion layer via a contact hole of an underlayer.

Preferably, the drain electrode may be made of a high melting point metal, and the insulating film between the drain electrode and the gate electrode may be formed of a nitride film or an oxide film.

Method for manufacturing a semiconductor device according to an embodiment of the present invention

Growing a first conductive epitaxial layer on a first conductive semiconductor substrate and then forming a second conductive first diffusion layer in a portion of the epitaxial layer;

Forming a high concentration of a first conductivity type second diffusion layer in a portion of the first diffusion layer;

Forming a first trench that penetrates the second diffusion layer and the second diffusion layer together, and then forming a gate oxide film on an inner surface of the first trench;

Forming a gate electrode on the gate oxide layer in the first trench, forming an opening in which a portion of the bottom surface of the gate electrode is removed, and then forming a high concentration of the first conductivity type third diffusion layer in the epi layer under the opening;

Stacking an insulating film on the gate electrode and forming a second trench in the third diffusion layer;

Forming a drain electrode filled in the first and second trenches together; And

And forming a source electrode electrically connected to the second diffusion layer through a contact hole of an underlayer.

Preferably, the drain electrode may be formed of a high melting point metal, and an insulating film between the drain electrode and the gate electrode may be formed of a nitride film or an oxide film.

A semiconductor device according to another embodiment of the present invention

A first conductive semiconductor substrate having a first conductive epitaxial layer;

A second conductivity type first diffusion layer diffused in a portion of the epi layer;

A first conductive type second diffusion layer having a high concentration diffused in a portion of the first diffusion layer;

A gate oxide film formed on an inner surface of the first trench that penetrates the second diffusion layer and the second diffusion layer together;

A gate electrode formed on the gate oxide layer and defined at a side portion of the first trench;

A first concentration type third diffusion layer having a high concentration formed in a portion of the epi layer under the first trench;

A drain electrode filled in a first trench defined by an insulating film stacked on the gate electrode and filled in an opening through which a portion of the surface of the third diffusion layer is exposed through a central portion of a bottom surface of the insulating film and the gate oxide film; And

And a source electrode electrically connected to the second diffusion layer via a contact hole of an underlayer.

Preferably, the drain electrode may be made of a high melting point metal, and the insulating film between the drain electrode and the gate electrode may be formed of a nitride film or an oxide film. It is also possible to form a silicide layer of a high melting point metal layer between the drain electrode and the third diffusion layer.

Method for manufacturing a semiconductor device according to another embodiment of the present invention

Growing a first conductive epitaxial layer on a first conductive semiconductor substrate and then forming a second conductive first diffusion layer in a portion of the epitaxial layer;

Forming a high concentration of a first conductivity type second diffusion layer in a portion of the first diffusion layer;

Forming a first trench through a center of the second diffusion layer and the first diffusion layer, and then forming a gate oxide film on an inner surface of the first trench;

Forming a gate electrode on the gate oxide layer, forming an opening from which a portion of the bottom surface of the gate electrode is removed, and then forming a third diffusion layer on the epitaxial layer under the opening;

Stacking an insulating film on the gate electrode and etching a portion of the insulating film and the gate oxide film to expose the third diffusion layer;

Forming a drain electrode filled in the first trench; And

And a source electrode electrically connected to the second diffusion layer via a contact hole of an underlayer.

Preferably, the drain electrode may be formed of a high melting point metal, and an insulating film between the drain electrode and the gate electrode may be formed of a nitride film or an oxide film. It is also possible to form a silicide layer of a high melting point metal layer between the drain electrode and the third diffusion layer.

Therefore, according to the embodiment of the present invention and other embodiments, since the large area of the diffusion layer is not required to connect the output terminal to the external circuit by forming the drain electrode together with the gate electrode in the trench, it is necessary to embed the LD MOS transistor in the IC chip. It does not lead to an increase in chip area. In addition, the spreading resistance component in the drift region is reduced, the on-resistance value is lowered, and the current driving capability is improved.

Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part of the same structure and the same action as the conventional part.

2 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, Figures 3 to 9 are process charts showing a method for manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2, in the semiconductor device of the present invention, an n-type epitaxial layer 11 is epitaxially grown by a predetermined thickness on a first conductive semiconductor substrate 10, for example, an n-type silicon substrate. The p-type first diffusion layer 33 of the second conductivity type is diffused into a portion of the first diffusion layer 33 in a thickness smaller than that of the epi layer 11, and n + is formed in a portion of the first diffusion layer 33 in a thickness smaller than the first diffusion layer 33. The type second diffusion layer 35 is diffused. The gate oxide film 41 is formed only on the inner surface of the first trench that penetrates the center of the second diffusion layer 35 and the first diffusion layer 33 thereunder, and the gate oxide film 41 is formed on the side surface of the first trench. A gate electrode 45 made of a material such as polycrystalline silicon is formed in the n-type, and the n + type third diffusion layer 47 is diffused into a part of the epi layer 11 under the first trench. An insulating film 49, such as an oxide film, is stacked on the gate electrode 45, and the drain electrode 51 is filled in the first trench defined by the insulating film 49, and at the center of the bottom surface of the insulating film 49 and the gate thereunder. The second trench penetrates the oxide film 41 and extends into the third diffusion layer 47. The source electrode 55 is electrically connected to the second diffusion layer 35 via the contact hole of the underlying film 53 such as an oxide film.

The drain electrode 51 may be formed of a high melting point metal layer such as tungsten (W), cobalt (Co), or the like, and the insulating film 49 may be formed of a nitride film or an oxide film.

Referring to FIGS. 3 to 9, the method of manufacturing the semiconductor device configured as described above will be described with reference to FIGS. 3 through 9. First, as shown in FIG. After the epitaxial layer 11 is epitaxially grown by a predetermined thickness, a second conductivity type p-type first diffusion layer 33 is formed in a portion of the epitaxial layer 11 to a thickness smaller than that of the epitaxial layer 11. Then, an oxide film is deposited as the diffusion mask layer 37 on the epitaxial layer 11, and a photolithography process is performed on the portion of the epitaxial layer 11 for the n + type second diffusion layer 35 by the photolithography process. After the opening 38 is formed, a second diffusion layer having a thickness smaller than that of the first diffusion layer 33 is formed by ion implanting impurities such as phosphorus into the first diffusion layer 33 in the opening 38 through the opening 38. 35).

As shown in FIG. 4, after the second diffusion layer 35 is formed, an insulating film 39, for example an oxide film, is deposited on the second diffusion layer 35 as an etching mask layer for the first trench 40. In addition, a first trench 40 penetrating both the central portion of the second diffusion layer 35 and the first diffusion layer 33 thereunder is formed. Subsequently, a gate oxide film 41 is stacked on the inner surface of the first trench 40 and the insulating film 39, and a conductive layer for the gate electrode 45, for example, a polysilicon layer, is stacked thereon.

As shown in FIG. 5, after the polysilicon layers for the gate electrode 45 are stacked, the polysilicon layer is left in the first trench 40 using the chemical mechanical polishing process (CMP), leaving only the polycrystalline silicon layer outside. Remove all silicon layers. Thus, the gate electrode 45 is formed on the gate oxide film 41 in the first trench 40.

As shown in FIG. 6, after the gate electrode 45 is formed, the gate electrode 45 positioned on a portion of the epi layer 11 for the third diffusion layer 47 of FIG. 7 using a photolithography process. After the openings 46 are formed in the central portion of the bottom surface, impurities such as phosphorus, for example, are implanted into the first diffusion layer 33 via the openings 46. Here, the third diffusion layer 47 is to make ohmic contact between the drain electrode 51 and the epi layer 11 of FIG. 8.

As shown in FIG. 7, after the ion implantation process for the third diffusion layer 47 is completed, the third diffusion layer 47 is diffused to a thickness smaller than that of the epi layer 11 using a heat treatment process. Then, an insulating film 49 is deposited on the resultant structure to electrically insulate the gate electrode 45 from the drain electrode 51 of FIG. 8, and then, for the second trench 48 using a photolithography process. The insulating film 49 and the gate oxide film 41 of the portion are etched, and the third diffusion layer 47 is etched by a partial thickness to form the second trench 48.

As shown in FIG. 8, once the second trench 48 is formed, a conductive layer, for example tungsten, for the drain electrode 51 on the resulting structure to a thickness sufficient to completely fill the first and second trenches. A high melting point metal layer such as (W), cobalt (Co), etc. is laminated. Therefore, the drain electrode 51 makes ohmic contact with the epi layer 11 by the third diffusion layer 47.

After the high melting point metal layer for the drain electrode 51 is stacked, the high melting point metal layer is treated by a chemical mechanical polishing process or an etch back process to remove all the high melting point metal layers outside the trench and to form the drain electrode 51 in the trench. do.

As shown in FIG. 9, after the drain electrode 51 is formed, an oxide film is laminated as the underlying film 54 on the resulting structure and the underlying film is formed on a portion of the second diffusion layer 35 using a photolithography process. After forming the contact hole (54), a conductive layer, for example, an aluminum layer for the source electrode 55 is stacked thereon, and formed into a pattern of the source electrode 55 by a photolithography process, thereby forming the LD of the present invention. Complete the process for morph transistors.

Accordingly, the present invention forms a gate electrode and a drain electrode in the trench together with the external electrode in order to electrically connect the output terminal to the external circuit, unlike a conventional method requiring a large area diffusion layer outside the trench to electrically connect the output terminal to the external circuit. It does not require a large area diffusion layer, and furthermore, it does not lead to an increase in the required area of the IC chip. As a result, the degree of integration of the IC chip can be improved.

In addition, the spreading resistance component in the drift region can be reduced, and further, the on-resistance value can be reduced, and as a result, the current driving capability can be improved.

10 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention, and FIGS. 11 to 13 are process diagrams showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 10, in the semiconductor device of the present invention, the drain electrode 151 is filled in the first trench and electrically connected to the surface of the third diffusion layer 47, and the drain electrode 151 and the third diffusion layer 47 are formed. Except for forming the silicide layer 52 therebetween, it has the same structure as the semiconductor device of FIG.

A method of manufacturing a semiconductor device configured as described above will be described with reference to FIGS. 11 through 13. As shown in FIG. 11, first, the processes of FIGS. 3 through 6 are performed in the same manner. That is, the n-type epitaxial layer 11 is epitaxially grown by a predetermined thickness on the first conductive semiconductor substrate 10, for example, the n-type silicon substrate, and then p is a second conductive type in a portion of the epitaxial layer 11. The mold first diffusion layer 33 is formed to a thickness smaller than that of the epi layer 11. Then, an oxide film is deposited as the diffusion mask layer 37 on the epitaxial layer 11, and a photolithography process is performed on the portion of the epitaxial layer 11 for the n + type second diffusion layer 35 by the photolithography process. After the opening 38 is formed, a second diffusion layer having a thickness smaller than that of the first diffusion layer 33 is formed by ion implanting impurities such as phosphorus into the first diffusion layer 33 in the opening 38 through the opening 38. 35).

After the second diffusion layer 35 is formed, an insulating film 39, for example an oxide film, is stacked on the second diffusion layer 35 as an etching mask layer for the first trench 40, and the second diffusion layer 35 is formed. A first trench 40 is formed through the central portion of and the first diffusion layer 33 thereunder. Subsequently, a gate oxide film 41 is stacked on the inner surface of the first trench 40 and the insulating film 39, and a conductive layer for the gate electrode 45, for example, a polysilicon layer, is stacked thereon.

After the polysilicon layer for the gate electrode 45 is stacked, the polysilicon layer is removed from the outer side of the polysilicon layer only by leaving the polysilicon layer in the first trench 40 using a chemical mechanical polishing process (CMP). Thus, the gate electrode 45 is formed on the gate oxide film 41 in the first trench 40.

After the gate electrode 45 is formed, the opening 46 is formed in the center of the bottom surface of the gate electrode 45 positioned on a part of the epi layer 11 for the third diffusion layer 47 of FIG. 7 using a photolithography process. After forming the ion, impurities such as phosphorus are ion-implanted into the first diffusion layer 33 via the opening 46. Here, the third diffusion layer 47 is to make ohmic contact between the drain electrode 51 and the epi layer 11 of FIG. 8.

After the ion implantation process for the third diffusion layer 47 is completed, the third diffusion layer 47 is diffused to a thickness smaller than that of the epi layer 11 using a heat treatment process. Then, an insulating film 49 is deposited on the resultant structure to electrically insulate the gate electrode 45 from the drain electrode 51 of FIG. 12, and then, for the second trench 148 using a photolithography process. The insulating film 49 and the gate oxide film 41 in the portion are etched until the surface of the third diffusion layer 47 underneath is exposed to form the opening 148.

As shown in FIG. 12, once the opening 148 is formed, a conductive layer, for example tungsten (W), for the drain electrode 51 on the resulting structure to a thickness sufficient to completely fill the first trenches. A high melting point metal layer such as cobalt (Co) is laminated. Therefore, the drain electrode 51 makes ohmic contact with the epi layer 11 by the third diffusion layer 47.

After the high melting point metal layer for the drain electrode 51 is stacked, the high melting point metal layer is treated by a chemical mechanical polishing process or an etch back process to remove all the high melting point metal layers outside the trench and to form the drain electrode 51 in the trench. do.

As shown in FIG. 13, after the drain electrode 51 is formed, an oxide film is laminated as the base film 54 on the resultant structure, and the drain electrode 51 is heat-treated to heat the drain electrode 51 and the third diffusion layer. A silicide layer 52 of a high melting point metal layer is formed between the layers 47. Subsequently, a contact hole of the underlying layer 54 is formed on a portion of the second diffusion layer 35 using a photolithography process, and then a conductive layer, for example, an aluminum layer for the source electrode 55 is stacked thereon. Forming the pattern of the source electrode 55 by a photolithography process to complete the process for the LD MOS transistor of the present invention.

Accordingly, the present invention forms a gate electrode and a drain electrode in the trench together with the external electrode in order to electrically connect the output terminal to the external circuit, unlike a conventional method requiring a large area diffusion layer outside the trench to electrically connect the output terminal to the external circuit. It does not require a large area diffusion layer, and furthermore does not bring about an increase in the required area of the IC chip. As a result, the degree of integration of the IC chip can be improved. In addition, the spreading resistance component in the drift region can be reduced, and further, the on-resistance value can be reduced, and as a result, the current driving capability can be improved.

Meanwhile, in the exemplary embodiment of the present invention, the first conductive type is n-type and the second conductive type is p-type. However, the same applies to the case where the first conductive type is p-type and the second conductive type is n-type. Applicability is obvious and the description thereof will be omitted for the convenience of explanation in order to avoid duplication of explanation.

As described above, according to the present invention, a first conductivity type epitaxial layer is grown on a first conductivity type semiconductor substrate, and a second conductivity type first diffusion layer is selectively formed on a portion of the epitaxial layer, and Forming a first conductivity type second diffusion layer in a portion, forming a first trench that penetrates the first and second diffusion layers, stacking a gate oxide film on an inner surface of the first trench, and forming a gate electrode on the gate oxide film, The center portion of the bottom surface of the gate electrode is removed, and a first conductivity type third diffusion layer is formed on the epi layer under the gate electrode, an insulating film is laminated on the gate electrode, the center portion of the bottom surface of the insulating film and the gate oxide film under it and the high concentration diffusion layer thereunder. Is partially etched to form a second trench (or a second trench is formed by etching a center portion of the bottom surface of the insulating film and a gate oxide film below it) and filling the first and second trenches. The drain electrode is formed together, and a source electrode electrically connected to the second diffusion layer is formed.

Therefore, the present invention does not require a large area diffusion layer for electrically connecting the output terminal to an external circuit, and does not bring about an increase in the required area of the IC chip. As a result, the degree of integration of the IC chip can be improved. In addition, the spreading resistance component in the drift region can be reduced, and further, the on-resistance value can be reduced, and as a result, the current driving capability can be improved.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (10)

A first conductive semiconductor substrate having a first conductive epitaxial layer; A second conductivity type first diffusion layer diffused in a portion of the epi layer; A first conductive type second diffusion layer having a high concentration diffused in a portion of the first diffusion layer; A gate oxide film formed on an inner surface of the first trench that penetrates the second diffusion layer and the first diffusion layer together; A gate electrode formed on the gate oxide layer and defined at a side portion of the first trench; A first conductive type third diffusion layer having a high concentration formed in the epitaxial layer under the first trench; A drain electrode filled in a first trench defined by an insulating layer stacked on the gate electrode and filled in a second trench extending through the center portion of the bottom surface of the insulating film and the gate oxide film and extending in the third diffusion layer; And And a source electrode electrically connected to the second diffusion layer via a contact hole of an underlayer. The semiconductor device according to claim 1, wherein the drain electrode is made of a high melting point metal layer. Growing a first conductive epitaxial layer on a first conductive semiconductor substrate and then forming a second conductive first diffusion layer in a portion of the epitaxial layer; Forming a high concentration of a first conductivity type second diffusion layer in a portion of the first diffusion layer; Forming a first trench that penetrates the second diffusion layer and the second diffusion layer together, and then forming a gate oxide film on an inner surface of the first trench; Forming a gate electrode on the gate oxide layer in the first trench, forming an opening in which a portion of the bottom surface of the gate electrode is removed, and then forming a high concentration of the first conductivity type third diffusion layer in the epi layer under the opening; Stacking an insulating film on the gate electrode and forming a second trench in the third diffusion layer; Filling the first and second trenches together to form a drain electrode facing the gate electrode through the insulating film and extending to the third diffusion layer; And And forming a source electrode electrically connected to the second diffusion layer via a contact hole of an underlayer. 4. The method of claim 3, wherein the drain electrode is formed of a high melting point metal layer. A first conductive semiconductor substrate having a first conductive epitaxial layer; A second conductivity type first diffusion layer diffused in a portion of the epi layer; A first conductive type second diffusion layer having a high concentration diffused in a portion of the first diffusion layer; A gate oxide film formed on an inner surface of the first trench that penetrates the second diffusion layer and the second diffusion layer together; A gate electrode formed on the gate oxide layer and defined at a side portion of the first trench; A first concentration type third diffusion layer having a high concentration formed in a portion of the epi layer under the first trench; A drain electrode filled in a first trench defined by an insulating layer stacked on the gate electrode and filled in an opening through which a portion of the surface of the third diffusion layer is exposed through a central portion of a bottom surface of the insulating film and the gate oxide film; And And a source electrode electrically connected to the second diffusion layer via a contact hole of an underlayer. 6. The semiconductor device of claim 5, wherein the drain electrode is made of a high melting point metal layer. The semiconductor device according to claim 5, wherein a silicide layer of a high melting point metal layer is formed between the drain electrode and the third diffusion layer. Growing a first conductive epitaxial layer on a first conductive semiconductor substrate and then forming a second conductive first diffusion layer in a portion of the epitaxial layer; Forming a high concentration of a first conductivity type second diffusion layer in a portion of the first diffusion layer; Forming a first trench through a center of the second diffusion layer and the first diffusion layer, and then forming a gate oxide film on an inner surface of the first trench; Forming a gate electrode on the gate oxide layer, forming an opening from which a portion of the bottom surface of the gate electrode is removed, and then forming a third diffusion layer on the epitaxial layer under the opening; Stacking an insulating film on the gate electrode and etching a portion of the insulating film and the gate oxide film to expose the third diffusion layer; Forming a drain electrode in the first trench; And And a source electrode electrically connected to the second diffusion layer via a contact hole of an underlayer. 9. The method of claim 8, wherein the drain electrode is formed of a high melting point metal layer. 10. The method of claim 8, wherein a silicide layer of a high melting point metal layer is formed between the drain electrode and the third diffusion layer.