KR100365758B1 - Method for high speed wrire operating in semiconductor memory device - Google Patents

Abstract

The present invention relates to a method of driving a semiconductor memory device for quickly obtaining a ride operation by different row-to-column delays (tRCD) during read and write of a semiconductor memory device. The present invention can be applied to any semiconductor memory device in which the write latency and the bus transistor are sufficiently large so that the last data at the time of writing is after the tRCD.

Description

A method for driving a semiconductor memory device for a high-speed write operation {Method for high speed wrire operating in semiconductor memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a semiconductor memory device, and more particularly, to a method of driving a semiconductor memory device having an improved protocol for implementing a write operation at high speed.

In general, an operation of a semiconductor memory device may be classified into a read operation and a write operation. FIG. 1 is a block diagram illustrating a core circuit unit of a conventional memory device, in which each operation will be described. FIG.

The read operation is to output data stored in the cell, and the write operation is to store data in the cell. When reading or writing data, a read command or a write command is received from an external source. When writing, a write command is input, and after a few clock cycles, the write data is input. This is a write latency. When a read command is input, a read command is output after a few clock cycles. This is called a read latency or a CAS latency.

First, referring to a read operation, a command decoder receiving an external command receives a read command to activate a read command, receives an external address from an address buffer, and enables a word line WL of a cell through a predecoder. The preamplified address is input to generate a sense amplifier activation signal sae for activating the bit lines BL and / BL sense amplifiers SA from the sense amplifier activation signal generator. If a predetermined voltage is applied to the bit line while the word line is enabled and the applied voltage is amplified by the bit line sense amplifier SA, input / output through the column gate (Y-Gate) controlled by the column cell selection signal Yi After being transferred to the line, it is output to the outside of the chip through a series of data output paths such as data bus sense amplifiers, latches and output buffers.

Next, referring to the write operation, data input through a series of data input paths, such as an input buffer and a light driver, is loaded on an input / output line and then a bit line (Y-Gate) controlled by the column cell selection signal Yi. The word line WL, which is transferred to BL and / BL) and is activated, is stored in the cell CELL.

The read and write process of the DRAM is generally performed. It should be noted that the data may not be used in the read operation through the column gate (Y-Gate) when the column cell selection signal Yi is activated. In the write operation, the data is transferred from the input / output line to the bit lines BL and / BL.

The column cell selection signal Yi is a pulse signal that is activated when the bit line is sufficiently sensed and amplified by the sense amplifier SA. The word line WL and the sense amplifier activation signal sae are enabled by a row address. As a result, the bit lines BL and / BL are activated at a time when they are sufficiently sensed.

At this time, there is an AC parameter that defines a delay from when a row address is input until the column cell selection signal Yi is activated. This is called a low to column delay (tRCD). In the read operation, the tRCD margin must be sufficiently satisfied, but the cell data is transferred to the data line by the column cell selection signal after being sufficiently amplified by being loaded on the bit line.

On the other hand, the data is stored in the cell while satisfying tRCD at the time of writing. When the column cell selection signal Yi is activated, data is transferred from the input / output line to the bit line through the column gate. However, during the write operation, only the write data is transferred to the bit line of the cell while the row and column address assignment operation is in progress, so that tRCD is not required as much as the read operation.

Meanwhile, in the conventional semiconductor memory device, since the write operation is performed in accordance with the read operation, the write operation is performed after an unnecessarily long tRCD time is satisfied. That is, although the write operation can be performed more quickly after the row operation (from the low address to the bit line sensing), the failure prevents the system performance.

Especially in memory devices with long write latency (latency from write command to write data input) or memory devices that need to receive a large number of data in a single write operation, they are further detrimental to system performance. have.

2 is a timing diagram showing the timing of tRCD used in a conventional memory device.

Referring to FIG. 2, a low activation command ACT is input as a read and write timing of a synchronous memory device having a write latency of 2, a burst latency of 8, and a cas latency of 3. After that, the write command WR is inputted via tRCD. Similarly, after passing through tRCD, a read command is input. That is, the operation starts through the same tRCD at the time of writing and reading. When the read command is input, data is output through the data output path after the row and column addresses are designated. In addition, when a write command is input, data is transmitted to the bit line through the data input path.

As described above, in the conventional memory device, since the tRCD is applied to the read operation and the write operation in the same manner, the performance of the system is reduced by performing the write operation after satisfying the unnecessarily long tRCD time during the write operation. In particular, memory devices with long write latency or memory devices that need to receive a large amount of data in one write operation are becoming increasingly detrimental to system performance.

The present invention has been made to solve the above problems of the prior art, a semiconductor memory having a faster write operation than the conventional by different tRCD (Row to Column Delay) during the read and write driving Its purpose is to provide a method of driving a device.

1 is a configuration diagram showing a core circuit part of a conventional memory device.

Fig. 2 is a timing chart showing the timing of tRCD used in the prior art memory device.

Fig. 3 is a timing chart showing timing in the case of separately using tRCD during read and write according to the present invention.

According to the present invention for achieving the above object, in the method of driving a semiconductor memory device, a read command is input after a first low-to-column drive delay time (tRCDR), and outputs data corresponding to a bus trend after a cascade latency. Performing; After the second low-to-column drive delay time tRCDR is less than the second low-to-column drive delay time tRCDW, a light command is input, and after the light latency, a data corresponding to the bus trend is output to perform light driving. It is made to include.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a timing diagram showing timing in the case where tRCD is separately used for reading and writing according to the present invention.

Referring to FIG. 3, read and write timings of a synchronous memory device having a write latency of 2, a burst lang of 8, and a cas latency of 3 are shown. In the read operation, the low activation command ACT is input in the same manner as in the prior art, and then the read command RD is input through tRCDR (tRCD for READ) and data is output after the cascading time tCL. This is the same as the conventional lead drive.

It should be noted, however, that the write command WR is input via tRCDW (tRCD for WRITE) less than tRCDR (tRCD for READ) after the low activation command ACT is input during the write operation. Then, data after tWL is inputted in the write latency.

As described above, in the present invention, the write command WR is input immediately after the low activation command ACT is input. The reason for this is that after the write command WR is input, after the write latency tWL, the low activation occurs for a burst length BL = 8 so that the data in the cell is sufficiently sensed and amplified. This is because the margin of the time when the column cell selection signal (Yi in FIG. 1) is activated and the time when the write data is loaded on the bit line can be obtained.

That is, as soon as the low activation command is input, when the write command is input and the burst length is 8, the column cell selection signal is activated only until the 8th write data is input. You'll have plenty of time to light up. The tRCDW value can be set such that the sum of tRCDW, tWL, and BL is equal to or greater than tRCDR. In other words, the tRCDW value may be set such that the time at which the last write data is input is equal to or later than tRCDR.

As described above, the fast write operation can be efficiently performed by differentiating the tRCD time for the read and the tRCD time for the write.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, a faster write operation may be realized by different tRCD times between read and write, and the efficiency of the command bus may be improved since the time used in the conventional write operation may be used for another command.

Claims (2)

In the method of driving a semiconductor memory device, Performing a read operation by inputting a read command after a first low-to-column drive delay time tRCDR, and outputting data corresponding to a bus trend after a cascade latency; Performing a light drive by inputting a light command after a second low-to-column drive delay time tRCDW less than the first low-to-column drive delay time tRCDR, and outputting data corresponding to a bus trance after light latency. Method of driving a semiconductor memory device comprising a. The method of claim 1, The second low-to-column driving delay time tRCDW value is Wherein the second low-to-column drive delay time tRCDW and the value of the light latency and the bus transit are set to be at least equal to the first low-to-column drive delay time tRCDR. How to drive a memory device.